hc
2023-12-11 1f93a7dfd1f8d5ff7a5c53246c7534fe2332d6f4
kernel/drivers/memory/ti-emif-sram-pm.S
....@@ -14,12 +14,12 @@
1414 * GNU General Public License for more details.
1515 */
1616
17
-#include <generated/ti-emif-asm-offsets.h>
1817 #include <linux/linkage.h>
1918 #include <asm/assembler.h>
2019 #include <asm/memory.h>
2120
2221 #include "emif.h"
22
+#include "ti-emif-asm-offsets.h"
2323
2424 #define EMIF_POWER_MGMT_WAIT_SELF_REFRESH_8192_CYCLES 0x00a0
2525 #define EMIF_POWER_MGMT_SR_TIMER_MASK 0x00f0
....@@ -27,6 +27,7 @@
2727 #define EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK 0x0700
2828
2929 #define EMIF_SDCFG_TYPE_DDR2 0x2 << SDRAM_TYPE_SHIFT
30
+#define EMIF_SDCFG_TYPE_DDR3 0x3 << SDRAM_TYPE_SHIFT
3031 #define EMIF_STATUS_READY 0x4
3132
3233 #define AM43XX_EMIF_PHY_CTRL_REG_COUNT 0x120
....@@ -245,6 +246,46 @@
245246 ENDPROC(ti_emif_restore_context)
246247
247248 /*
249
+ * void ti_emif_run_hw_leveling(void)
250
+ *
251
+ * Used during resume to run hardware leveling again and restore the
252
+ * configuration of the EMIF PHY, only for DDR3.
253
+ */
254
+ENTRY(ti_emif_run_hw_leveling)
255
+ adr r4, ti_emif_pm_sram_data
256
+ ldr r0, [r4, #EMIF_PM_BASE_ADDR_PHYS_OFFSET]
257
+
258
+ ldr r3, [r0, #EMIF_READ_WRITE_LEVELING_CONTROL]
259
+ orr r3, r3, #RDWRLVLFULL_START
260
+ ldr r2, [r0, #EMIF_SDRAM_CONFIG]
261
+ and r2, r2, #SDRAM_TYPE_MASK
262
+ cmp r2, #EMIF_SDCFG_TYPE_DDR3
263
+ bne skip_hwlvl
264
+
265
+ str r3, [r0, #EMIF_READ_WRITE_LEVELING_CONTROL]
266
+
267
+ /*
268
+ * If EMIF registers are touched during initial stage of HW
269
+ * leveling sequence there will be an L3 NOC timeout error issued
270
+ * as the EMIF will not respond, which is not fatal, but it is
271
+ * avoidable. This small wait loop is enough time for this condition
272
+ * to clear, even at worst case of CPU running at max speed of 1Ghz.
273
+ */
274
+ mov r2, #0x2000
275
+1:
276
+ subs r2, r2, #0x1
277
+ bne 1b
278
+
279
+ /* Bit clears when operation is complete */
280
+2: ldr r1, [r0, #EMIF_READ_WRITE_LEVELING_CONTROL]
281
+ tst r1, #RDWRLVLFULL_START
282
+ bne 2b
283
+
284
+skip_hwlvl:
285
+ mov pc, lr
286
+ENDPROC(ti_emif_run_hw_leveling)
287
+
288
+/*
248289 * void ti_emif_enter_sr(void)
249290 *
250291 * Programs the EMIF to tell the SDRAM to enter into self-refresh