.. | .. |
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14 | 14 | * GNU General Public License for more details. |
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15 | 15 | */ |
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16 | 16 | |
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17 | | -#include <generated/ti-emif-asm-offsets.h> |
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18 | 17 | #include <linux/linkage.h> |
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19 | 18 | #include <asm/assembler.h> |
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20 | 19 | #include <asm/memory.h> |
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21 | 20 | |
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22 | 21 | #include "emif.h" |
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| 22 | +#include "ti-emif-asm-offsets.h" |
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23 | 23 | |
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24 | 24 | #define EMIF_POWER_MGMT_WAIT_SELF_REFRESH_8192_CYCLES 0x00a0 |
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25 | 25 | #define EMIF_POWER_MGMT_SR_TIMER_MASK 0x00f0 |
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.. | .. |
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27 | 27 | #define EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK 0x0700 |
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28 | 28 | |
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29 | 29 | #define EMIF_SDCFG_TYPE_DDR2 0x2 << SDRAM_TYPE_SHIFT |
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| 30 | +#define EMIF_SDCFG_TYPE_DDR3 0x3 << SDRAM_TYPE_SHIFT |
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30 | 31 | #define EMIF_STATUS_READY 0x4 |
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31 | 32 | |
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32 | 33 | #define AM43XX_EMIF_PHY_CTRL_REG_COUNT 0x120 |
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.. | .. |
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245 | 246 | ENDPROC(ti_emif_restore_context) |
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246 | 247 | |
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247 | 248 | /* |
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| 249 | + * void ti_emif_run_hw_leveling(void) |
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| 250 | + * |
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| 251 | + * Used during resume to run hardware leveling again and restore the |
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| 252 | + * configuration of the EMIF PHY, only for DDR3. |
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| 253 | + */ |
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| 254 | +ENTRY(ti_emif_run_hw_leveling) |
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| 255 | + adr r4, ti_emif_pm_sram_data |
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| 256 | + ldr r0, [r4, #EMIF_PM_BASE_ADDR_PHYS_OFFSET] |
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| 257 | + |
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| 258 | + ldr r3, [r0, #EMIF_READ_WRITE_LEVELING_CONTROL] |
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| 259 | + orr r3, r3, #RDWRLVLFULL_START |
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| 260 | + ldr r2, [r0, #EMIF_SDRAM_CONFIG] |
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| 261 | + and r2, r2, #SDRAM_TYPE_MASK |
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| 262 | + cmp r2, #EMIF_SDCFG_TYPE_DDR3 |
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| 263 | + bne skip_hwlvl |
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| 264 | + |
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| 265 | + str r3, [r0, #EMIF_READ_WRITE_LEVELING_CONTROL] |
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| 266 | + |
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| 267 | + /* |
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| 268 | + * If EMIF registers are touched during initial stage of HW |
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| 269 | + * leveling sequence there will be an L3 NOC timeout error issued |
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| 270 | + * as the EMIF will not respond, which is not fatal, but it is |
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| 271 | + * avoidable. This small wait loop is enough time for this condition |
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| 272 | + * to clear, even at worst case of CPU running at max speed of 1Ghz. |
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| 273 | + */ |
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| 274 | + mov r2, #0x2000 |
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| 275 | +1: |
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| 276 | + subs r2, r2, #0x1 |
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| 277 | + bne 1b |
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| 278 | + |
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| 279 | + /* Bit clears when operation is complete */ |
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| 280 | +2: ldr r1, [r0, #EMIF_READ_WRITE_LEVELING_CONTROL] |
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| 281 | + tst r1, #RDWRLVLFULL_START |
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| 282 | + bne 2b |
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| 283 | + |
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| 284 | +skip_hwlvl: |
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| 285 | + mov pc, lr |
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| 286 | +ENDPROC(ti_emif_run_hw_leveling) |
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| 287 | + |
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| 288 | +/* |
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248 | 289 | * void ti_emif_enter_sr(void) |
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249 | 290 | * |
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250 | 291 | * Programs the EMIF to tell the SDRAM to enter into self-refresh |
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