forked from ~ljy/RK356X_SDK_RELEASE
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2023-12-11 1f93a7dfd1f8d5ff7a5c53246c7534fe2332d6f4 
 kernel/drivers/media/platform/rockchip/cif/regs.h
....@@ -61,6 +61,9 @@
6161 	CIF_REG_DVP_FRM0_ADDR_UV_ID3,
6262 	CIF_REG_DVP_FRM1_ADDR_Y_ID3,
6363 	CIF_REG_DVP_FRM1_ADDR_UV_ID3,
64
+	CIF_REG_DVP_SAV_EAV,
65
+	CIF_REG_DVP_LINE_CNT1,
66
+	CIF_REG_DVP_LINE_INT_NUM1,
6467 	/* mipi & lvds registers index */
6568 	CIF_REG_MIPI_LVDS_ID0_CTRL0,
6669 	CIF_REG_MIPI_LVDS_ID0_CTRL1,
....@@ -134,6 +137,16 @@
134137 	CIF_REG_LVDS_SAV_EAV_BLK0_ID3,
135138 	CIF_REG_LVDS_SAV_EAV_ACT1_ID3,
136139 	CIF_REG_LVDS_SAV_EAV_BLK1_ID3,
140
+	CIF_REG_MIPI_EFFECT_CODE_ID0,
141
+	CIF_REG_MIPI_EFFECT_CODE_ID1,
142
+	CIF_REG_MIPI_EFFECT_CODE_ID2,
143
+	CIF_REG_MIPI_EFFECT_CODE_ID3,
144
+	CIF_REG_LVDS_ID0_CTRL0,
145
+	CIF_REG_LVDS_ID1_CTRL0,
146
+	CIF_REG_LVDS_ID2_CTRL0,
147
+	CIF_REG_LVDS_ID3_CTRL0,
148
+	CIF_REG_MIPI_ON_PAD,
149
+
137150 	CIF_REG_Y_STAT_CONTROL,
138151 	CIF_REG_Y_STAT_VALUE,
139152 	CIF_REG_MMU_DTE_ADDR,
....@@ -149,6 +162,35 @@
149162 	/* reg belowed is in grf */
150163 	CIF_REG_GRF_CIFIO_CON,
151164 	CIF_REG_GRF_CIFIO_CON1,
165
+	CIF_REG_GRF_CIFIO_VENC,
166
+	/* reg global control */
167
+	CIF_REG_GLB_CTRL,
168
+	CIF_REG_GLB_INTEN,
169
+	CIF_REG_GLB_INTST,
170
+	CIF_REG_SCL_CH_CTRL,
171
+	CIF_REG_SCL_CTRL,
172
+	CIF_REG_SCL_FRM0_ADDR_CH0,
173
+	CIF_REG_SCL_FRM1_ADDR_CH0,
174
+	CIF_REG_SCL_VLW_CH0,
175
+	CIF_REG_SCL_FRM0_ADDR_CH1,
176
+	CIF_REG_SCL_FRM1_ADDR_CH1,
177
+	CIF_REG_SCL_VLW_CH1,
178
+	CIF_REG_SCL_FRM0_ADDR_CH2,
179
+	CIF_REG_SCL_FRM1_ADDR_CH2,
180
+	CIF_REG_SCL_VLW_CH2,
181
+	CIF_REG_SCL_FRM0_ADDR_CH3,
182
+	CIF_REG_SCL_FRM1_ADDR_CH3,
183
+	CIF_REG_SCL_VLW_CH3,
184
+	CIF_REG_SCL_BLC_CH0,
185
+	CIF_REG_SCL_BLC_CH1,
186
+	CIF_REG_SCL_BLC_CH2,
187
+	CIF_REG_SCL_BLC_CH3,
188
+	CIF_REG_TOISP0_CTRL,
189
+	CIF_REG_TOISP0_SIZE,
190
+	CIF_REG_TOISP0_CROP,
191
+	CIF_REG_TOISP1_CTRL,
192
+	CIF_REG_TOISP1_SIZE,
193
+	CIF_REG_TOISP1_CROP,
152194 	CIF_REG_INDEX_MAX
153195 };
154196 
....@@ -298,6 +340,138 @@
298340 #define CIF_MMU_INT_STATUS		0x820
299341 #define CIF_MMU_AUTO_GATING		0x824
300342 
343
+/* RK3588 DVP Registers Offset */
344
+#define DVP_CTRL			0x10
345
+#define DVP_INTEN			0x14
346
+#define DVP_INTSTAT			0x18
347
+#define DVP_FOR				0x1C
348
+#define DVP_MULTI_ID			0x20
349
+#define DVP_SAV_EAV			0x24
350
+#define DVP_CROP_SIZE			0x28
351
+#define DVP_CROP			0x2C
352
+#define DVP_FRM0_ADDR_Y_ID0		0x30
353
+#define DVP_FRM0_ADDR_UV_ID0		0x34
354
+#define DVP_FRM1_ADDR_Y_ID0		0x38
355
+#define DVP_FRM1_ADDR_UV_ID0		0x3C
356
+#define DVP_FRM0_ADDR_Y_ID1		0x40
357
+#define DVP_FRM0_ADDR_UV_ID1		0x44
358
+#define DVP_FRM1_ADDR_Y_ID1		0x48
359
+#define DVP_FRM1_ADDR_UV_ID1		0x4C
360
+#define DVP_FRM0_ADDR_Y_ID2		0x50
361
+#define DVP_FRM0_ADDR_UV_ID2		0x54
362
+#define DVP_FRM1_ADDR_Y_ID2		0x58
363
+#define DVP_FRM1_ADDR_UV_ID2		0x5C
364
+#define DVP_FRM0_ADDR_Y_ID3		0x60
365
+#define DVP_FRM0_ADDR_UV_ID3		0x64
366
+#define DVP_FRM1_ADDR_Y_ID3		0x68
367
+#define DVP_FRM1_ADDR_UV_ID3		0x6C
368
+#define DVP_VIR_LINE_WIDTH		0x70
369
+#define DVP_LINE_INT_NUM_01		0x74
370
+#define DVP_LINE_INT_NUM_23		0x78
371
+#define DVP_LINE_CNT_01			0x7C
372
+#define DVP_LINE_CNT_23			0x80
373
+
374
+/* RK3588 CSI Registers Offset */
375
+#define CSI_MIPI0_ID0_CTRL0		0x100
376
+#define CSI_MIPI0_ID0_CTRL1		0x104
377
+#define CSI_MIPI0_ID1_CTRL0		0x108
378
+#define CSI_MIPI0_ID1_CTRL1		0x10C
379
+#define CSI_MIPI0_ID2_CTRL0		0x110
380
+#define CSI_MIPI0_ID2_CTRL1		0x114
381
+#define CSI_MIPI0_ID3_CTRL0		0x118
382
+#define CSI_MIPI0_ID3_CTRL1		0x11C
383
+#define CSI_MIPI0_CTRL			0x120
384
+#define CSI_MIPI0_FRM0_ADDR_Y_ID0	0x124
385
+#define CSI_MIPI0_FRM1_ADDR_Y_ID0	0x128
386
+#define CSI_MIPI0_FRM0_ADDR_UV_ID0	0x12C
387
+#define CSI_MIPI0_FRM1_ADDR_UV_ID0	0x130
388
+#define CSI_MIPI0_VLW_ID0		0x134
389
+#define CSI_MIPI0_FRM0_ADDR_Y_ID1	0x138
390
+#define CSI_MIPI0_FRM1_ADDR_Y_ID1	0x13C
391
+#define CSI_MIPI0_FRM0_ADDR_UV_ID1	0x140
392
+#define CSI_MIPI0_FRM1_ADDR_UV_ID1	0x144
393
+#define CSI_MIPI0_VLW_ID1		0x148
394
+#define CSI_MIPI0_FRM0_ADDR_Y_ID2	0x14C
395
+#define CSI_MIPI0_FRM1_ADDR_Y_ID2	0x150
396
+#define CSI_MIPI0_FRM0_ADDR_UV_ID2	0x154
397
+#define CSI_MIPI0_FRM1_ADDR_UV_ID2	0x158
398
+#define CSI_MIPI0_VLW_ID2		0x15C
399
+#define CSI_MIPI0_FRM0_ADDR_Y_ID3	0x160
400
+#define CSI_MIPI0_FRM1_ADDR_Y_ID3	0x164
401
+#define CSI_MIPI0_FRM0_ADDR_UV_ID3	0x168
402
+#define CSI_MIPI0_FRM1_ADDR_UV_ID3	0x16C
403
+#define CSI_MIPI0_VLW_ID3		0x170
404
+#define CSI_MIPI0_INTEN			0x174
405
+#define CSI_MIPI0_INTSTAT		0x178
406
+#define CSI_MIPI0_LINE_INT_NUM_ID0_1	0x17C
407
+#define CSI_MIPI0_LINE_INT_NUM_ID2_3	0x180
408
+#define CSI_MIPI0_LINE_CNT_ID0_1	0x184
409
+#define CSI_MIPI0_LINE_CNT_ID2_3	0x188
410
+#define CSI_MIPI0_ID0_CROP_START	0x18C
411
+#define CSI_MIPI0_ID1_CROP_START	0x190
412
+#define CSI_MIPI0_ID2_CROP_START	0x194
413
+#define CSI_MIPI0_ID3_CROP_START	0x198
414
+#define CSI_MIPI0_FRAME_NUM_VC0		0x19C
415
+#define CSI_MIPI0_FRAME_NUM_VC1		0x1A0
416
+#define CSI_MIPI0_FRAME_NUM_VC2		0x1A4
417
+#define CSI_MIPI0_FRAME_NUM_VC3		0x1A8
418
+#define CSI_MIPI0_EFFECT_CODE_ID0	0x1AC
419
+#define CSI_MIPI0_EFFECT_CODE_ID1	0x1B0
420
+#define CSI_MIPI0_EFFECT_CODE_ID2	0x1B4
421
+#define CSI_MIPI0_EFFECT_CODE_ID3	0x1B8
422
+#define CSI_MIPI0_ON_PAD		0x1BC
423
+
424
+/* RV1106 CONTROL Registers Offset */
425
+#define CIF_LVDS0_ID0_CTRL0		0x1D0
426
+#define CIF_LVDS0_ID1_CTRL0		0x1D4
427
+#define CIF_LVDS0_ID2_CTRL0		0x1D8
428
+#define CIF_LVDS0_ID3_CTRL0		0x1DC
429
+#define CIF_LVDS_SAV_EAV_ACT0_ID0_RV1106	0x1E0
430
+#define CIF_LVDS_SAV_EAV_BLK0_ID0_RV1106	0x1E4
431
+#define CIF_LVDS_SAV_EAV_ACT1_ID0_RV1106	0x1E8
432
+#define CIF_LVDS_SAV_EAV_BLK1_ID0_RV1106	0x1EC
433
+#define CIF_LVDS_SAV_EAV_ACT0_ID1_RV1106	0x1F0
434
+#define CIF_LVDS_SAV_EAV_BLK0_ID1_RV1106	0x1F4
435
+#define CIF_LVDS_SAV_EAV_ACT1_ID1_RV1106	0x1F8
436
+#define CIF_LVDS_SAV_EAV_BLK1_ID1_RV1106	0x1FC
437
+#define CIF_LVDS_SAV_EAV_ACT0_ID2_RV1106	0x200
438
+#define CIF_LVDS_SAV_EAV_BLK0_ID2_RV1106	0x204
439
+#define CIF_LVDS_SAV_EAV_ACT1_ID2_RV1106	0x208
440
+#define CIF_LVDS_SAV_EAV_BLK1_ID2_RV1106	0x20C
441
+#define CIF_LVDS_SAV_EAV_ACT0_ID3_RV1106	0x210
442
+#define CIF_LVDS_SAV_EAV_BLK0_ID3_RV1106	0x214
443
+#define CIF_LVDS_SAV_EAV_ACT1_ID3_RV1106	0x218
444
+#define CIF_LVDS_SAV_EAV_BLK1_ID3_RV1106	0x21C
445
+
446
+/* RK3588 CONTROL Registers Offset */
447
+#define GLB_CTRL			0X000
448
+#define GLB_INTEN			0X004
449
+#define GLB_INTST			0X008
450
+#define SCL_CH_CTRL			0x700
451
+#define SCL_CTRL			0x704
452
+#define SCL_FRM0_ADDR_CH0		0x708
453
+#define SCL_FRM1_ADDR_CH0		0x70C
454
+#define SCL_VLW_CH0			0x710
455
+#define SCL_FRM0_ADDR_CH1		0x714
456
+#define SCL_FRM1_ADDR_CH1		0x718
457
+#define SCL_VLW_CH1			0x71C
458
+#define SCL_FRM0_ADDR_CH2		0x720
459
+#define SCL_FRM1_ADDR_CH2		0x724
460
+#define SCL_VLW_CH2			0x728
461
+#define SCL_FRM0_ADDR_CH3		0x72C
462
+#define SCL_FRM1_ADDR_CH3		0x730
463
+#define SCL_VLW_CH3			0x734
464
+#define SCL_BLC_CH0			0x738
465
+#define SCL_BLC_CH1			0x73C
466
+#define SCL_BLC_CH2			0x740
467
+#define SCL_BLC_CH3			0x744
468
+#define TOISP0_CH_CTRL			0x780
469
+#define TOISP0_CROP_SIZE		0x784
470
+#define TOISP0_CROP			0x788
471
+#define TOISP1_CH_CTRL			0x78C
472
+#define TOISP1_CROP_SIZE		0x790
473
+#define TOISP1_CROP			0x794
474
+
301475 /* The key register bit description */
302476 
303477 /* CIF_CTRL Reg */
....@@ -307,6 +481,13 @@
307481 #define MODE_PINGPONG			(0x1 << 1)
308482 #define MODE_LINELOOP			(0x2 << 1)
309483 #define AXI_BURST_16			(0xF << 12)
484
+#define DVP_PRESS_EN			(0x1 << 12)
485
+#define DVP_HURRY_EN			(0x1 << 8)
486
+#define DVP_DMA_EN			(0x1 << 1)
487
+#define DVP_SW_WATER_LINE_75		(0x0 << 5)
488
+#define DVP_SW_WATER_LINE_50		(0x1 << 5)
489
+#define DVP_SW_WATER_LINE_25		(0x2 << 5)
490
+#define DVP_SW_WATER_LINE_00		(0x3 << 5)
310491 
311492 /* CIF_INTEN */
312493 #define INTEN_DISABLE			(0x0 << 0)
....@@ -335,7 +516,30 @@
335516 #define PRE_INF_FRAME_END_CLR		(0x01 << 8)
336517 #define PST_INF_FRAME_END_CLR		(0x01 << 9)
337518 #define INTSTAT_ERR			(0xFC)
519
+#define INTSTAT_ERR_RK3588		(DVP_SIZE_ERR |\
520
+					 DVP_FIFO_OVERFLOW |\
521
+					 DVP_BANDWIDTH_LACK)
522
+
338523 #define DVP_ALL_OVERFLOW		(IFIFO_OVERFLOW | DFIFO_OVERFLOW)
524
+
525
+#define DVP_FIFO_OVERFLOW		(0x01 << 16)
526
+#define DVP_BANDWIDTH_LACK		(0x01 << 17)
527
+
528
+#define DVP_SIZE_ERR_ID0		(0x1 << 22)
529
+#define DVP_SIZE_ERR_ID1		(0x1 << 23)
530
+#define DVP_SIZE_ERR_ID2		(0x1 << 24)
531
+#define DVP_SIZE_ERR_ID3		(0x1 << 25)
532
+
533
+#define DVP_SIZE_ERR			(DVP_SIZE_ERR_ID0 |\
534
+					 DVP_SIZE_ERR_ID1 |\
535
+					 DVP_SIZE_ERR_ID2 |\
536
+					 DVP_SIZE_ERR_ID3)
537
+
538
+#define DVP_SW_PRESS_VALUE(val)		(((val) & 0x7) << 13)
539
+#define DVP_SW_HURRY_VALUE(val)		(((val) & 0x7) << 9)
540
+#define DVP_SW_CAP_EN(ID)		(2 << ID)
541
+#define DVP_SW_DMA_EN(ID)		(0x100000 << ID)
542
+#define DVP_START_INTSTAT(ID)		(0x3 << ((ID) * 2))
339543 
340544 #define DVP_DMA_END_INTEN(id)	\
341545 	({ \
....@@ -351,7 +555,7 @@
351555 	mask; \
352556 	})
353557 
354
-#define DVP_LINE_INTEN		(0x01 << 10)
558
+#define DVP_LINE_INTEN			(0x01 << 10)
355559 
356560 #define DVP_DMA_END_INTSTAT(id)		\
357561 	({ \
....@@ -367,8 +571,8 @@
367571 	mask; \
368572 	})
369573 
370
-#define DVP_PST_INTSTAT		PST_INF_FRAME_END
371
-#define DVP_LINE_INTSTAT	(0x01 << 10)
574
+#define DVP_PST_INTSTAT			PST_INF_FRAME_END
575
+#define DVP_LINE_INTSTAT		(0x01 << 10)
372576 
373577 /* FRAME STATUS */
374578 #define FRAME_STAT_CLS			0x00
....@@ -433,6 +637,20 @@
433637 #define BT656_1120_MULTI_ID_2_MASK	~(0x03 << 20)
434638 #define BT656_1120_MULTI_ID_3_MASK	~(0x03 << 28)
435639 #define	CIF_HIGH_ALIGN			(0x01 << 18)
640
+#define	CIF_HIGH_ALIGN_RK3588		(0x01 << 21)
641
+#define BT656_DETECT_SAV		(0X01 << 13)
642
+#define BT656_DETECT_SAV_EAV		(0X00 << 13)
643
+
644
+#define BT1120_CLOCK_SINGLE_EDGES_RK3588	(0x00 << 11)
645
+#define BT1120_CLOCK_DOUBLE_EDGES_RK3588	(0x01 << 11)
646
+#define TRANSMIT_INTERFACE_RK3588		(0x01 << 9)
647
+#define TRANSMIT_PROGRESS_RK3588		(0x00 << 9)
648
+#define BT1120_YC_SWAP_RK3588			(0x01 << 12)
649
+#define INPUT_BT601_YUV422			(0x00 << 2)
650
+#define INPUT_BT601_RAW				(0x01 << 2)
651
+#define INPUT_BT656_YUV422			(0x02 << 2)
652
+#define INPUT_BT1120_YUV422			(0x03 << 2)
653
+#define INPUT_SONY_RAW				(0x04 << 2)
436654 
437655 /* CIF_SCL_CTRL */
438656 #define ENABLE_SCL_DOWN			(0x01 << 0)
....@@ -460,10 +678,32 @@
460678 #define DVP_CHANNEL3_F1_READY		(0x01 << 13)
461679 #define DVP_CHANNEL3_FRM_READ		(DVP_CHANNEL3_F0_READY | DVP_CHANNEL3_F1_READY)
462680 
681
+#define DVP_FRAME0_START_ID0		(0x1 << 0)
682
+#define DVP_FRAME1_START_ID0		(0x1 << 1)
683
+
463684 #define DVP_FRAME_END_ID0		(0x1 << 0)
464685 #define DVP_FRAME_END_ID1		(0x1 << 11)
465686 #define DVP_FRAME_END_ID2		(0x1 << 12)
466687 #define DVP_FRAME_END_ID3		(0x1 << 13)
688
+
689
+#define DVP_FRAME0_END_ID0		(0x1 << 8)
690
+#define DVP_FRAME1_END_ID0		(0x1 << 9)
691
+#define DVP_ALL_END_ID0			(DVP_FRAME0_END_ID0 | DVP_FRAME1_END_ID0)
692
+
693
+#define DVP_FRAME0_END_ID1		(0x1 << 10)
694
+#define DVP_FRAME1_END_ID1		(0x1 << 11)
695
+#define DVP_ALL_END_ID1			(DVP_FRAME0_END_ID1 | DVP_FRAME1_END_ID1)
696
+
697
+#define DVP_FRAME0_END_ID2		(0x1 << 12)
698
+#define DVP_FRAME1_END_ID2		(0x1 << 13)
699
+#define DVP_ALL_END_ID2			(DVP_FRAME0_END_ID2 | DVP_FRAME1_END_ID2)
700
+
701
+#define DVP_FRAME0_END_ID3		(0x1 << 14)
702
+#define DVP_FRAME1_END_ID3		(0x1 << 15)
703
+#define DVP_ALL_END_ID3			(DVP_FRAME0_END_ID3 | DVP_FRAME1_END_ID3)
704
+
705
+#define DVP_ALIGN_MSB			(0x01 << 21)
706
+#define DVP_ALIGN_LSB			(0x00 << 21)
467707 
468708 #define DVP_FRM_STS_ID0(x)		(((x) & (0x3 << 0)) >> 0)
469709 #define DVP_FRM_STS_ID1(x)		(((x) & (0x3 << 4)) >> 4)
....@@ -497,6 +737,28 @@
497737 #define CIF_CROP_Y_SHIFT		16
498738 #define CIF_CROP_X_SHIFT		0
499739 
740
+/* CIF SCALE*/
741
+#define SCALE_END_INTSTAT(ch)		(0x3 << ((ch + 1) * 2))
742
+#define SCALE_FIFO_OVERFLOW(ch)		(1 << (10 + ch))
743
+#define SCALE_TOISP_AXI0_ERR		(1 << 0)
744
+#define SCALE_TOISP_AXI1_ERR		(1 << 1)
745
+#define CIF_SCALE_SW_PRESS_VALUE(val)	(((val) & 0x7) << 13)
746
+#define CIF_SCALE_SW_PRESS_ENABLE	(0x1 << 12)
747
+#define CIF_SCALE_SW_HURRY_VALUE(val)	(((val) & 0x7) << 5)
748
+#define CIF_SCALE_SW_HURRY_ENABLE	(0x1 << 4)
749
+#define CIF_SCALE_SW_WATER_LINE(val)	(val << 1)
750
+#define CIF_SCALE_SW_SRC_CH(val, ch)	((val & 0x1f) << (3 + ch * 8))
751
+#define CIF_SCALE_SW_MODE(val, ch)	((val & 0x3) << (1 + ch * 8))
752
+#define CIF_SCALE_EN(ch)		(1 << (ch * 8))
753
+#define SW_SCALE_END(intstat, ch)	((intstat >> ((ch + 1) * 2)) & 0x3)
754
+#define SCALE_SOFT_RESET(ch)		(0x1 << (ch + 16))
755
+
756
+/* CIF TOISP*/
757
+#define CIF_TOISP0_FS(ch)		(BIT(14) << ch)
758
+#define CIF_TOISP1_FS(ch)		(BIT(17) << ch)
759
+#define CIF_TOISP0_FE(ch)		(BIT(20) << ch)
760
+#define CIF_TOISP1_FE(ch)		(BIT(23) << ch)
761
+
500762 /* CIF_CSI_ID_CTRL0 */
501763 #define CSI_DISABLE_CAPTURE		(0x0 << 0)
502764 #define CSI_ENABLE_CAPTURE		(0x1 << 0)
....@@ -507,16 +769,43 @@
507769 #define CSI_WRDDR_TYPE_YUV422		(0x4 << 1)
508770 #define CSI_WRDDR_TYPE_YUV420SP		(0x5 << 1)
509771 #define CSI_WRDDR_TYPE_YUV400		(0x6 << 1)
772
+#define CSI_WRDDR_TYPE_RGB565		(0x7 << 1)
510773 #define CSI_DISABLE_COMMAND_MODE	(0x0 << 4)
511774 #define CSI_ENABLE_COMMAND_MODE		(0x1 << 4)
512775 #define CSI_DISABLE_CROP		(0x0 << 5)
513776 #define CSI_ENABLE_CROP			(0x1 << 5)
777
+#define CSI_DISABLE_CROP_V1		(0x0 << 4)
778
+#define CSI_ENABLE_CROP_V1		(0x1 << 4)
514779 #define CSI_ENABLE_MIPI_COMPACT		(0x1 << 6)
515780 #define CSI_YUV_INPUT_ORDER_UYVY	(0x0 << 16)
516781 #define CSI_YUV_INPUT_ORDER_VYUY	(0x1 << 16)
517782 #define CSI_YUV_INPUT_ORDER_YUYV	(0x2 << 16)
518783 #define CSI_YUV_INPUT_ORDER_YVYU	(0x3 << 16)
519
-#define CSI_ENABLE_MIPI_HIGH_ALIGN	(0x1 << 31)
784
+#define CSI_HIGH_ALIGN			(0x1 << 31)
785
+#define CSI_HIGH_ALIGN_RK3588		(0x1 << 27)
786
+
787
+#define CSI_YUV_OUTPUT_ORDER_UYVY	(0x0 << 18)
788
+#define CSI_YUV_OUTPUT_ORDER_VYUY	(0x1 << 18)
789
+#define CSI_YUV_OUTPUT_ORDER_YUYV	(0x2 << 18)
790
+#define CSI_YUV_OUTPUT_ORDER_YVYU	(0x3 << 18)
791
+#define CSI_WRDDR_TYPE_RAW_COMPACT	(0x0 << 5)
792
+#define CSI_WRDDR_TYPE_RAW_UNCOMPACT	(0x1 << 5)
793
+#define CSI_WRDDR_TYPE_YUV_PACKET	(0x2 << 5)
794
+#define CSI_WRDDR_TYPE_YUV400_RK3588	(0x3 << 5)
795
+#define CSI_WRDDR_TYPE_YUV422SP_RK3588	(0x4 << 5)
796
+#define CSI_WRDDR_TYPE_YUV420SP_RK3588	(0x5 << 5)
797
+#define CSI_ALIGN_MSB			(0x01 << 27)
798
+#define CSI_ALIGN_LSB			(0x0 << 27)
799
+#define CSI_DMA_ENABLE			(0x1 << 28)
800
+
801
+#define CSI_NO_HDR			(0X0 << 22)
802
+#define CSI_HDR2			(0X1 << 22)
803
+#define CSI_HDR3			(0X2 << 22)
804
+
805
+#define CSI_HDR_MODE_VC			(0x0 << 20)
806
+#define CSI_HDR_MODE_LINE_CNT		(0x1 << 20)
807
+#define CSI_HDR_MODE_LINE_INFO		(0x2 << 20)
808
+#define CSI_HDR_VC_MODE_PROTECT		(0x1 << 29)
520809 
521810 #define LVDS_ENABLE_CAPTURE		(0x1 << 16)
522811 #define LVDS_MODE(mode)			(((mode) & 0x7) << 17)
....@@ -549,6 +838,37 @@
549838 #define LVDS_HDR_FRAME_X3		(0x1 << 28)
550839 #define LVDS_COMPACT			(0x1 << 29)
551840 
841
+#define LVDS_ENABLE_CAPTURE_RV1106		(0x1 << 0)
842
+#define LVDS_MODE_RV1106(mode)			(((mode) & 0x7) << 1)
843
+#define LVDS_LANES_ENABLED_RV1106(lanes)	\
844
+	({ \
845
+		unsigned int mask; \
846
+		switch (lanes) { \
847
+		case 1: \
848
+			mask = 0x1 << 4; \
849
+			break; \
850
+		case 2: \
851
+			mask = 0x3 << 4; \
852
+			break; \
853
+		case 3: \
854
+			mask = 0x7 << 4; \
855
+			break; \
856
+		case 4: \
857
+			mask = 0xf << 4; \
858
+			break; \
859
+		default: \
860
+			mask = 0x1 << 4; \
861
+			break; \
862
+		} \
863
+		mask; \
864
+	})
865
+
866
+#define LVDS_MAIN_LANE_RV1106(index)		(((index) & 0x3) << 8)
867
+#define LVDS_FID_RV1106(id)			(((id) & 0x3) << 10)
868
+#define LVDS_HDR_FRAME_X2_RV1106		(0x0 << 12)
869
+#define LVDS_HDR_FRAME_X3_RV1106		(0x1 << 12)
870
+#define LVDS_DMAEN_RV1106			(0x1 << 15)
871
+
552872 /* CIF_CSI_INTEN */
553873 #define CSI_FRAME1_START_INTEN(id)	(0x1 << ((id) * 2 + 1))
554874 #define CSI_FRAME0_END_INTEN(id)	(0x1 << ((id) * 2 + 8))
....@@ -561,14 +881,17 @@
561881 #define CSI_ALL_FRAME_START_INTEN	(0xff << 0)
562882 #define CSI_ALL_FRAME_END_INTEN		(0xff << 8)
563883 #define CSI_ALL_ERROR_INTEN		(0x1f << 16)
884
+#define CSI_ALL_ERROR_INTEN_V1		(0xf0f << 16)
564885 
565886 #define CSI_START_INTEN(id)		(0x3 << ((id) * 2))
566887 #define CSI_DMA_END_INTEN(id)		(0x3 << ((id) * 2 + 8))
567888 #define CSI_LINE_INTEN(id)		(0x1 << ((id) + 21))
889
+#define CSI_LINE_INTEN_RK3588(id)	(0x1 << ((id) + 20))
568890 
569891 #define CSI_START_INTSTAT(id)		(0x3 << ((id) * 2))
570892 #define CSI_DMA_END_INTSTAT(id)		(0x3 << ((id) * 2 + 8))
571893 #define CSI_LINE_INTSTAT(id)		(0x1 << ((id) + 21))
894
+#define CSI_LINE_INTSTAT_V1(id)		(0x1 << ((id) + 20))
572895 
573896 /* CIF_CSI_INTSTAT */
574897 #define CSI_FRAME0_START_ID0		(0x1 << 0)
....@@ -598,51 +921,73 @@
598921 #define CSI_LINE_ID3_INTST		(0x1 << 24)
599922 #define CSI_DMA_LVDS_ID2_FIFO_OVERFLOW	(0x1 << 25)
600923 #define CSI_DMA_LVDS_ID3_FIFO_OVERFLOW	(0x1 << 26)
924
+#define CSI_SIZE_ERR_ID0		(0x1 << 24)
925
+#define CSI_SIZE_ERR_ID1		(0x1 << 25)
926
+#define CSI_SIZE_ERR_ID2		(0x1 << 26)
927
+#define CSI_SIZE_ERR_ID3		(0x1 << 27)
601928 
602
-#define CSI_FRAME_START_ID0	(CSI_FRAME0_START_ID0 |\
603
-				 CSI_FRAME1_START_ID0)
604
-#define CSI_FRAME_START_ID1	(CSI_FRAME0_START_ID1 |\
605
-				 CSI_FRAME1_START_ID1)
606
-#define CSI_FRAME_START_ID2	(CSI_FRAME0_START_ID2 |\
607
-				 CSI_FRAME1_START_ID2)
608
-#define CSI_FRAME_START_ID3	(CSI_FRAME0_START_ID3 |\
609
-				 CSI_FRAME1_START_ID3)
610
-#define CSI_FRAME_END_ID0	(CSI_FRAME0_END_ID0 |\
611
-				 CSI_FRAME1_END_ID0)
612
-#define CSI_FRAME_END_ID1	(CSI_FRAME0_END_ID1 |\
613
-				 CSI_FRAME1_END_ID1)
614
-#define CSI_FRAME_END_ID2	(CSI_FRAME0_END_ID2 |\
615
-				 CSI_FRAME1_END_ID2)
616
-#define CSI_FRAME_END_ID3	(CSI_FRAME0_END_ID3 |\
617
-				 CSI_FRAME1_END_ID3)
618
-#define CSI_FIFO_OVERFLOW	(CSI_DMA_Y_FIFO_OVERFLOW |	\
619
-				 CSI_DMA_UV_FIFO_OVERFLOW |	\
620
-				 CSI_CONFIG_FIFO_OVERFLOW |	\
621
-				 CSI_RX_FIFO_OVERFLOW |	\
622
-				 CSI_DMA_LVDS_ID2_FIFO_OVERFLOW |	\
623
-				 CSI_DMA_LVDS_ID3_FIFO_OVERFLOW)
929
+#define CSI_FRAME_START_ID0		(CSI_FRAME0_START_ID0 |\
930
+					 CSI_FRAME1_START_ID0)
931
+#define CSI_FRAME_START_ID1		(CSI_FRAME0_START_ID1 |\
932
+					 CSI_FRAME1_START_ID1)
933
+#define CSI_FRAME_START_ID2		(CSI_FRAME0_START_ID2 |\
934
+					 CSI_FRAME1_START_ID2)
935
+#define CSI_FRAME_START_ID3		(CSI_FRAME0_START_ID3 |\
936
+					 CSI_FRAME1_START_ID3)
937
+#define CSI_FRAME_END_ID0		(CSI_FRAME0_END_ID0 |\
938
+					 CSI_FRAME1_END_ID0)
939
+#define CSI_FRAME_END_ID1		(CSI_FRAME0_END_ID1 |\
940
+					 CSI_FRAME1_END_ID1)
941
+#define CSI_FRAME_END_ID2		(CSI_FRAME0_END_ID2 |\
942
+					 CSI_FRAME1_END_ID2)
943
+#define CSI_FRAME_END_ID3		(CSI_FRAME0_END_ID3 |\
944
+					 CSI_FRAME1_END_ID3)
945
+#define CSI_FIFO_OVERFLOW		(CSI_DMA_Y_FIFO_OVERFLOW |\
946
+					 CSI_DMA_UV_FIFO_OVERFLOW |\
947
+					 CSI_CONFIG_FIFO_OVERFLOW |\
948
+					 CSI_RX_FIFO_OVERFLOW |\
949
+					 CSI_DMA_LVDS_ID2_FIFO_OVERFLOW |\
950
+					 CSI_DMA_LVDS_ID3_FIFO_OVERFLOW)
951
+
952
+/*mask for rk3588*/
953
+#define CSI_RX_FIFO_OVERFLOW_V1		(0x1 << 19)
954
+#define CSI_BANDWIDTH_LACK_V1		(0x1 << 18)
955
+#define CSI_ALL_ERROR_INTEN_V1		(0xf0f << 16)
956
+
957
+
958
+#define CSI_FIFO_OVERFLOW_V1		(CSI_DMA_Y_FIFO_OVERFLOW |\
959
+					 CSI_DMA_UV_FIFO_OVERFLOW |\
960
+					 CSI_RX_FIFO_OVERFLOW_V1)
961
+#define CSI_SIZE_ERR			(CSI_SIZE_ERR_ID0 |\
962
+					 CSI_SIZE_ERR_ID1 |\
963
+					 CSI_SIZE_ERR_ID2 |\
964
+					 CSI_SIZE_ERR_ID3)
965
+
624966 /* CIF_MIPI_LVDS_CTRL */
625
-#define CIF_MIPI_LVDS_SW_DMA_IDLE		(0x1 << 16)
626
-#define CIF_MIPI_LVDS_SW_PRESS_VALUE(val)	(((val) & 0x3) << 13)
627
-#define CIF_MIPI_LVDS_SW_PRESS_ENABLE		(0x1 << 12)
628
-#define CIF_MIPI_LVDS_SW_LVDS_WIDTH_8BITS	(0x0 << 9)
629
-#define CIF_MIPI_LVDS_SW_LVDS_WIDTH_10BITS	(0x1 << 9)
630
-#define CIF_MIPI_LVDS_SW_LVDS_WIDTH_12BITS	(0x2 << 9)
631
-#define CIF_MIPI_LVDS_SW_SEL_LVDS		(0x1 << 8)
632
-#define CIF_MIPI_LVDS_SW_HURRY_VALUE(val)	(((val) & 0x3) << 5)
633
-#define CIF_MIPI_LVDS_SW_HURRY_ENABLE		(0x1 << 4)
634
-#define CIF_MIPI_LVDS_SW_WATER_LINE_75		(0x0 << 1)
635
-#define CIF_MIPI_LVDS_SW_WATER_LINE_50		(0x1 << 1)
636
-#define CIF_MIPI_LVDS_SW_WATER_LINE_25		(0x2 << 1)
637
-#define CIF_MIPI_LVDS_SW_WATER_LINE_00		(0x3 << 1)
638
-#define CIF_MIPI_LVDS_SW_WATER_LINE_ENABLE	(0x1 << 0)
639
-#define CIF_MIPI_LVDS_SW_DMA_IDLE_RK1808	(0x1 << 24)
967
+#define CIF_MIPI_LVDS_SW_DMA_IDLE			(0x1 << 16)
968
+#define CIF_MIPI_LVDS_SW_PRESS_VALUE(val)		(((val) & 0x3) << 13)
969
+#define CIF_MIPI_LVDS_SW_PRESS_VALUE_RK3588(val)	(((val) & 0x7) << 13)
970
+#define CIF_MIPI_LVDS_SW_PRESS_ENABLE			(0x1 << 12)
971
+#define CIF_MIPI_LVDS_SW_LVDS_WIDTH_8BITS		(0x0 << 9)
972
+#define CIF_MIPI_LVDS_SW_LVDS_WIDTH_10BITS		(0x1 << 9)
973
+#define CIF_MIPI_LVDS_SW_LVDS_WIDTH_12BITS		(0x2 << 9)
974
+#define CIF_MIPI_LVDS_SW_SEL_LVDS			(0x1 << 8)
975
+#define CIF_MIPI_LVDS_SW_SEL_LVDS_RV1106		(0x1 << 3)
976
+#define CIF_MIPI_LVDS_SW_HURRY_VALUE(val)		(((val) & 0x3) << 5)
977
+#define CIF_MIPI_LVDS_SW_HURRY_VALUE_RK3588(val)	(((val) & 0x7) << 5)
978
+#define CIF_MIPI_LVDS_SW_HURRY_ENABLE			(0x1 << 4)
979
+#define CIF_MIPI_LVDS_SW_WATER_LINE_75			(0x0 << 1)
980
+#define CIF_MIPI_LVDS_SW_WATER_LINE_50			(0x1 << 1)
981
+#define CIF_MIPI_LVDS_SW_WATER_LINE_25			(0x2 << 1)
982
+#define CIF_MIPI_LVDS_SW_WATER_LINE_00			(0x3 << 1)
983
+#define CIF_MIPI_LVDS_SW_WATER_LINE_ENABLE		(0x1 << 0)
984
+#define CIF_MIPI_LVDS_SW_DMA_IDLE_RK1808		(0x1 << 24)
640985 #define CIF_MIPI_LVDS_SW_HURRY_VALUE_RK1808(val)	(((val) & 0x3) << 17)
641
-#define CIF_MIPI_LVDS_SW_HURRY_ENABLE_RK1808	(0x1 << 16)
642
-#define CIF_MIPI_LVDS_SW_WATER_LINE_75_RK1808	(0x0 << 0)
643
-#define CIF_MIPI_LVDS_SW_WATER_LINE_50_RK1808	(0x1 << 0)
644
-#define CIF_MIPI_LVDS_SW_WATER_LINE_25_RK1808	(0x2 << 0)
645
-#define CIF_MIPI_LVDS_SW_WATER_LINE_00_RK1808	(0x3 << 0)
986
+#define CIF_MIPI_LVDS_SW_HURRY_ENABLE_RK1808		(0x1 << 16)
987
+#define CIF_MIPI_LVDS_SW_WATER_LINE_75_RK1808		(0x0 << 0)
988
+#define CIF_MIPI_LVDS_SW_WATER_LINE_50_RK1808		(0x1 << 0)
989
+#define CIF_MIPI_LVDS_SW_WATER_LINE_25_RK1808		(0x2 << 0)
990
+#define CIF_MIPI_LVDS_SW_WATER_LINE_00_RK1808		(0x3 << 0)
646991 #define CIF_MIPI_LVDS_SW_WATER_LINE_ENABLE_RK1808	(0x1 << 4)
647992 
648993 /* CSI Host Registers Define */
....@@ -667,6 +1012,11 @@
6671012 #define SW_FRM_END_ID2(x)	(((x) & CSI_FRAME_END_ID2) >> 12)
6681013 #define SW_FRM_END_ID3(x)	(((x) & CSI_FRAME_END_ID3) >> 14)
6691014 
1015
+/*RV1106 SKIP FUNC*/
1016
+#define RKCIF_CAP_SHIFT		0x18
1017
+#define RKCIF_SKIP_SHIFT	0X15
1018
+#define RKCIF_SKIP_EN(x)	(0x1 << (8 + x))
1019
+
6701020 /* CIF LVDS SAV EAV Define */
6711021 #define SW_LVDS_EAV_ACT(code)	(((code) & 0xfff) << 16)
6721022 #define SW_LVDS_SAV_ACT(code)	(((code) & 0xfff) << 0)
....@@ -688,5 +1038,29 @@
6881038 #define RK3568_CIF_PCLK_SAMPLING_EDGE_FALLING	(0x10001000)
6891039 #define RK3568_CIF_PCLK_SINGLE_EDGE		(0x02000000)
6901040 #define RK3568_CIF_PCLK_DUAL_EDGE		(0x02000200)
1041
+#define CIF_GRF_SOC_CON2			(0x308)
1042
+#define RK3588_CIF_PCLK_SAMPLING_EDGE_RISING	(0x00100000)
1043
+#define RK3588_CIF_PCLK_SAMPLING_EDGE_FALLING	(0x00100010)
1044
+#define RK3588_CIF_PCLK_SINGLE_EDGE		(0x00200000)
1045
+#define RK3588_CIF_PCLK_DUAL_EDGE		(0x00200020)
1046
+#define RV1106_CIF_GRF_VI_CON			(0x50038)
1047
+#define RV1106_CIF_GRF_VENC_WRAPPER		(0x10008)
1048
+#define RV1106_CIF_PCLK_SINGLE_EDGE		(0x00040000)
1049
+#define RV1106_CIF_PCLK_DUAL_EDGE		(0x00040004)
1050
+#define RV1106_CIF_PCLK_EDGE_RISING_M0		(0x00020002)
1051
+#define RV1106_CIF_PCLK_EDGE_FALLING_M0		(0x00020000)
1052
+#define RV1106_CIF_PCLK_EDGE_RISING_M1		(0x00010001)
1053
+#define RV1106_CIF_PCLK_EDGE_FALLING_M1		(0x00010000)
1054
+#define RV1106_CIF_GRF_SEL_M0			(0x00010000)
1055
+#define RV1106_CIF_GRF_SEL_M1			(0x00010001)
1056
+
1057
+/*toisp*/
1058
+#define TOISP_FS_CH0(index)		(0x1 << (14 + index * 3))
1059
+#define TOISP_FS_CH1(index)		(0x1 << (15 + index * 3))
1060
+#define TOISP_FS_CH2(index)		(0x1 << (16 + index * 3))
1061
+
1062
+#define TOISP_END_CH0(index)		(0x1 << (20 + index * 3))
1063
+#define TOISP_END_CH1(index)		(0x1 << (21 + index * 3))
1064
+#define TOISP_END_CH2(index)		(0x1 << (22 + index * 3))
6911065 
6921066 #endif