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2023-12-11 1f93a7dfd1f8d5ff7a5c53246c7534fe2332d6f4

 kernel/drivers/clk/socfpga/clk-pll-a10.c
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@@ -1,17 +1,6 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (C) 2015 Altera Corporation. All rights reserved
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms and conditions of the GNU General Public License,
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- * version 2, as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope it will be useful, but WITHOUT
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- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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- * more details.
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- *
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- * You should have received a copy of the GNU General Public License along with
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- * this program.  If not, see <http://www.gnu.org/licenses/>.
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  */
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 #include <linux/slab.h>
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 #include <linux/clk-provider.h>
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@@ -69,7 +58,7 @@
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 		CLK_MGR_PLL_CLK_SRC_MASK;
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 }
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-static struct clk_ops clk_pll_ops = {
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+static const struct clk_ops clk_pll_ops = {
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 	.recalc_rate = clk_pll_recalc_rate,
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 	.get_parent = clk_pll_get_parent,
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 };
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@@ -82,7 +71,7 @@
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 	struct socfpga_pll *pll_clk;
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 	const char *clk_name = node->name;
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 	const char *parent_name[SOCFGPA_MAX_PARENTS];
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-	struct clk_init_data init = {};
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+	struct clk_init_data init;
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 	struct device_node *clkmgr_np;
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 	int rc;
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 	int i = 0;
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@@ -113,8 +102,6 @@
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 	pll_clk->hw.hw.init = &init;
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 	pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
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-	clk_pll_ops.enable = clk_gate_ops.enable;
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-	clk_pll_ops.disable = clk_gate_ops.disable;
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 	clk = clk_register(NULL, &pll_clk->hw.hw);
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 	if (WARN_ON(IS_ERR(clk))) {