add audio

hc

2023-12-11 1f93a7dfd1f8d5ff7a5c53246c7534fe2332d6f4

 kernel/arch/xtensa/kernel/hw_breakpoint.c
..
..
@@ -12,7 +12,7 @@
12
12
 #include <linux/log2.h>
13
13
 #include <linux/percpu.h>
14
14
 #include <linux/perf_event.h>
15
-#include <variant/core.h>
15
+#include <asm/core.h>
16
16
 
17
17
 /* Breakpoint currently in use for each IBREAKA. */
18
18
 static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[XCHAL_NUM_IBREAK]);
..
..
@@ -101,30 +101,30 @@
101
101
 	switch (sr) {
102
102
 #if XCHAL_NUM_IBREAK > 0
103
103
 	case SREG_IBREAKA + 0:
104
-		WSR(v, SREG_IBREAKA + 0);
104
+		xtensa_set_sr(v, SREG_IBREAKA + 0);
105
105
 		break;
106
106
 #endif
107
107
 #if XCHAL_NUM_IBREAK > 1
108
108
 	case SREG_IBREAKA + 1:
109
-		WSR(v, SREG_IBREAKA + 1);
109
+		xtensa_set_sr(v, SREG_IBREAKA + 1);
110
110
 		break;
111
111
 #endif
112
112
 
113
113
 #if XCHAL_NUM_DBREAK > 0
114
114
 	case SREG_DBREAKA + 0:
115
-		WSR(v, SREG_DBREAKA + 0);
115
+		xtensa_set_sr(v, SREG_DBREAKA + 0);
116
116
 		break;
117
117
 	case SREG_DBREAKC + 0:
118
-		WSR(v, SREG_DBREAKC + 0);
118
+		xtensa_set_sr(v, SREG_DBREAKC + 0);
119
119
 		break;
120
120
 #endif
121
121
 #if XCHAL_NUM_DBREAK > 1
122
122
 	case SREG_DBREAKA + 1:
123
-		WSR(v, SREG_DBREAKA + 1);
123
+		xtensa_set_sr(v, SREG_DBREAKA + 1);
124
124
 		break;
125
125
 
126
126
 	case SREG_DBREAKC + 1:
127
-		WSR(v, SREG_DBREAKC + 1);
127
+		xtensa_set_sr(v, SREG_DBREAKC + 1);
128
128
 		break;
129
129
 #endif
130
130
 	}
..
..
@@ -150,8 +150,8 @@
150
150
 	unsigned long ibreakenable;
151
151
 
152
152
 	xtensa_wsr(info->address, SREG_IBREAKA + reg);
153
-	RSR(ibreakenable, SREG_IBREAKENABLE);
154
-	WSR(ibreakenable | (1 << reg), SREG_IBREAKENABLE);
153
+	ibreakenable = xtensa_get_sr(SREG_IBREAKENABLE);
154
+	xtensa_set_sr(ibreakenable | (1 << reg), SREG_IBREAKENABLE);
155
155
 }
156
156
 
157
157
 static void set_dbreak_regs(int reg, struct perf_event *bp)
..
..
@@ -214,8 +214,9 @@
214
214
 		/* Breakpoint */
215
215
 		i = free_slot(this_cpu_ptr(bp_on_reg), XCHAL_NUM_IBREAK, bp);
216
216
 		if (i >= 0) {
217
-			RSR(ibreakenable, SREG_IBREAKENABLE);
218
-			WSR(ibreakenable & ~(1 << i), SREG_IBREAKENABLE);
217
+			ibreakenable = xtensa_get_sr(SREG_IBREAKENABLE);
218
+			xtensa_set_sr(ibreakenable & ~(1 << i),
219
+				      SREG_IBREAKENABLE);
219
220
 		}
220
221
 	} else {
221
222
 		/* Watchpoint */