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2023-12-11 1f93a7dfd1f8d5ff7a5c53246c7534fe2332d6f4

 kernel/arch/mips/mm/page.c
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@@ -20,7 +20,6 @@
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 #include <asm/inst.h>
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 #include <asm/io.h>
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 #include <asm/page.h>
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-#include <asm/pgtable.h>
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 #include <asm/prefetch.h>
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 #include <asm/bootinfo.h>
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 #include <asm/mipsregs.h>
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@@ -187,7 +186,7 @@
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 			}
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 			break;
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-		case CPU_LOONGSON3:
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+		case CPU_LOONGSON64:
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 			/* Loongson-3 only support the Pref_Load/Pref_Store. */
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 			pref_bias_clear_store = 128;
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 			pref_bias_copy_load = 128;
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@@ -251,14 +250,16 @@
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 		if (cpu_has_cache_cdex_s) {
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 			uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0);
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 		} else if (cpu_has_cache_cdex_p) {
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-			if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
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+			if (IS_ENABLED(CONFIG_WAR_R4600_V1_HIT_CACHEOP) &&
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+			    cpu_is_r4600_v1_x()) {
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 				uasm_i_nop(buf);
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 				uasm_i_nop(buf);
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 				uasm_i_nop(buf);
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 				uasm_i_nop(buf);
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 			}
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-			if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
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+			if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) &&
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+			    cpu_is_r4600_v2_x())
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 				uasm_i_lw(buf, ZERO, ZERO, AT);
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 			uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
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@@ -303,7 +304,7 @@
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 	else
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 		uasm_i_ori(&buf, A2, A0, off);
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-	if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
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+	if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) && cpu_is_r4600_v2_x())
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 		uasm_i_lui(&buf, AT, uasm_rel_hi(0xa0000000));
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 	off = cache_line_size ? min(8, pref_bias_clear_store / cache_line_size)
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@@ -403,14 +404,16 @@
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 		if (cpu_has_cache_cdex_s) {
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 			uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0);
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 		} else if (cpu_has_cache_cdex_p) {
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-			if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
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+			if (IS_ENABLED(CONFIG_WAR_R4600_V1_HIT_CACHEOP) &&
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+			    cpu_is_r4600_v1_x()) {
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 				uasm_i_nop(buf);
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 				uasm_i_nop(buf);
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 				uasm_i_nop(buf);
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 				uasm_i_nop(buf);
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 			}
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-			if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
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+			if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) &&
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+			    cpu_is_r4600_v2_x())
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 				uasm_i_lw(buf, ZERO, ZERO, AT);
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 			uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
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@@ -454,7 +457,7 @@
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 	else
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 		uasm_i_ori(&buf, A2, A0, off);
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-	if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
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+	if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) && cpu_is_r4600_v2_x())
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 		uasm_i_lui(&buf, AT, uasm_rel_hi(0xa0000000));
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 	off = cache_line_size ? min(8, pref_bias_copy_load / cache_line_size) *