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2023-12-11 1f93a7dfd1f8d5ff7a5c53246c7534fe2332d6f4

 kernel/arch/arm64/net/bpf_jit.h
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@@ -1,19 +1,8 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * BPF JIT compiler for ARM64
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  *
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  * Copyright (C) 2014-2016 Zi Shen Lim <zlim.lnx@gmail.com>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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  */
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 #ifndef _BPF_JIT_H
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 #define _BPF_JIT_H
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@@ -111,6 +100,14 @@
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 /* Rd = Rn OP imm12 */
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 #define A64_ADD_I(sf, Rd, Rn, imm12) A64_ADDSUB_IMM(sf, Rd, Rn, imm12, ADD)
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 #define A64_SUB_I(sf, Rd, Rn, imm12) A64_ADDSUB_IMM(sf, Rd, Rn, imm12, SUB)
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+#define A64_ADDS_I(sf, Rd, Rn, imm12) \
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+	A64_ADDSUB_IMM(sf, Rd, Rn, imm12, ADD_SETFLAGS)
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+#define A64_SUBS_I(sf, Rd, Rn, imm12) \
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+	A64_ADDSUB_IMM(sf, Rd, Rn, imm12, SUB_SETFLAGS)
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+/* Rn + imm12; set condition flags */
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+#define A64_CMN_I(sf, Rn, imm12) A64_ADDS_I(sf, A64_ZR, Rn, imm12)
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+/* Rn - imm12; set condition flags */
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+#define A64_CMP_I(sf, Rn, imm12) A64_SUBS_I(sf, A64_ZR, Rn, imm12)
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 /* Rd = Rn */
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 #define A64_MOV(sf, Rd, Rn) A64_ADD_I(sf, Rd, Rn, 0)
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@@ -182,6 +179,9 @@
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 /* Rd = Ra + Rn * Rm */
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 #define A64_MADD(sf, Rd, Ra, Rn, Rm) aarch64_insn_gen_data3(Rd, Ra, Rn, Rm, \
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 	A64_VARIANT(sf), AARCH64_INSN_DATA3_MADD)
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+/* Rd = Ra - Rn * Rm */
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+#define A64_MSUB(sf, Rd, Ra, Rn, Rm) aarch64_insn_gen_data3(Rd, Ra, Rn, Rm, \
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+	A64_VARIANT(sf), AARCH64_INSN_DATA3_MSUB)
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 /* Rd = Rn * Rm */
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 #define A64_MUL(sf, Rd, Rn, Rm) A64_MADD(sf, Rd, A64_ZR, Rn, Rm)
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@@ -197,4 +197,26 @@
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 /* Rn & Rm; set condition flags */
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 #define A64_TST(sf, Rn, Rm) A64_ANDS(sf, A64_ZR, Rn, Rm)
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+/* Logical (immediate) */
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+#define A64_LOGIC_IMM(sf, Rd, Rn, imm, type) ({ \
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+	u64 imm64 = (sf) ? (u64)imm : (u64)(u32)imm; \
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+	aarch64_insn_gen_logical_immediate(AARCH64_INSN_LOGIC_##type, \
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+		A64_VARIANT(sf), Rn, Rd, imm64); \
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+})
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+/* Rd = Rn OP imm */
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+#define A64_AND_I(sf, Rd, Rn, imm) A64_LOGIC_IMM(sf, Rd, Rn, imm, AND)
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+#define A64_ORR_I(sf, Rd, Rn, imm) A64_LOGIC_IMM(sf, Rd, Rn, imm, ORR)
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+#define A64_EOR_I(sf, Rd, Rn, imm) A64_LOGIC_IMM(sf, Rd, Rn, imm, EOR)
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+#define A64_ANDS_I(sf, Rd, Rn, imm) A64_LOGIC_IMM(sf, Rd, Rn, imm, AND_SETFLAGS)
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+/* Rn & imm; set condition flags */
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+#define A64_TST_I(sf, Rn, imm) A64_ANDS_I(sf, A64_ZR, Rn, imm)
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+
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+/* HINTs */
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+#define A64_HINT(x) aarch64_insn_gen_hint(x)
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+
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+/* BTI */
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+#define A64_BTI_C  A64_HINT(AARCH64_INSN_HINT_BTIC)
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+#define A64_BTI_J  A64_HINT(AARCH64_INSN_HINT_BTIJ)
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+#define A64_BTI_JC A64_HINT(AARCH64_INSN_HINT_BTIJC)
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+
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 #endif /* _BPF_JIT_H */