add audio

hc

2023-12-11 1f93a7dfd1f8d5ff7a5c53246c7534fe2332d6f4

 kernel/arch/arm64/boot/dts/sprd/whale2.dtsi
..
..
@@ -75,7 +75,9 @@
75
75
 					     "sprd,sc9836-uart";
76
76
 				reg = <0x0 0x100>;
77
77
 				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
78
-				clocks = <&ext_26m>;
78
+				clock-names = "enable", "uart", "source";
79
+				clocks = <&apapb_gate CLK_UART0_EB>,
80
+				       <&ap_clk CLK_UART0>, <&ext_26m>;
79
81
 				status = "disabled";
80
82
 			};
81
83
 
..
..
@@ -84,7 +86,9 @@
84
86
 					     "sprd,sc9836-uart";
85
87
 				reg = <0x100000 0x100>;
86
88
 				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
87
-				clocks = <&ext_26m>;
89
+				clock-names = "enable", "uart", "source";
90
+				clocks = <&apapb_gate CLK_UART1_EB>,
91
+				       <&ap_clk CLK_UART1>, <&ext_26m>;
88
92
 				status = "disabled";
89
93
 			};
90
94
 
..
..
@@ -93,7 +97,9 @@
93
97
 					     "sprd,sc9836-uart";
94
98
 				reg = <0x200000 0x100>;
95
99
 				interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
96
-				clocks = <&ext_26m>;
100
+				clock-names = "enable", "uart", "source";
101
+				clocks = <&apapb_gate CLK_UART2_EB>,
102
+				       <&ap_clk CLK_UART2>, <&ext_26m>;
97
103
 				status = "disabled";
98
104
 			};
99
105
 
..
..
@@ -102,7 +108,9 @@
102
108
 					     "sprd,sc9836-uart";
103
109
 				reg = <0x300000 0x100>;
104
110
 				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
105
-				clocks = <&ext_26m>;
111
+				clock-names = "enable", "uart", "source";
112
+				clocks = <&apapb_gate CLK_UART3_EB>,
113
+				       <&ap_clk CLK_UART3>, <&ext_26m>;
106
114
 				status = "disabled";
107
115
 			};
108
116
 		};
..
..
@@ -121,6 +129,34 @@
121
129
 				#dma-channels = <32>;
122
130
 				clock-names = "enable";
123
131
 				clocks = <&apahb_gate CLK_DMA_EB>;
132
+			};
133
+
134
+			sdio3: sdio@50430000 {
135
+				compatible  = "sprd,sdhci-r11";
136
+				reg = <0 0x50430000 0 0x1000>;
137
+				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
138
+
139
+				clock-names = "sdio", "enable", "2x_enable";
140
+				clocks = <&aon_prediv CLK_EMMC_2X>,
141
+				       <&apahb_gate CLK_EMMC_EB>,
142
+				       <&aon_gate CLK_EMMC_2X_EN>;
143
+				assigned-clocks = <&aon_prediv CLK_EMMC_2X>;
144
+				assigned-clock-parents = <&clk_l0_409m6>;
145
+
146
+				sprd,phy-delay-mmc-hs400 = <0x44 0x7f 0x2e 0x2e>;
147
+				sprd,phy-delay-mmc-hs200 = <0x0 0x8c 0x8c 0x8c>;
148
+				sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>;
149
+				sprd,phy-delay-mmc-hs400es = <0x3f 0x3f 0x2e 0x2e>;
150
+				vmmc-supply = <&vddemmccore>;
151
+				bus-width = <8>;
152
+				non-removable;
153
+				no-sdio;
154
+				no-sd;
155
+				cap-mmc-hw-reset;
156
+				mmc-hs400-enhanced-strobe;
157
+				mmc-hs400-1_8v;
158
+				mmc-hs200-1_8v;
159
+				mmc-ddr-1_8v;
124
160
 			};
125
161
 		};
126
162
 
..
..
@@ -264,4 +300,11 @@
264
300
 		clock-frequency = <100000000>;
265
301
 		clock-output-names = "ext-rco-100m";
266
302
 	};
303
+
304
+	clk_l0_409m6: clk_l0_409m6 {
305
+		compatible = "fixed-clock";
306
+		#clock-cells = <0>;
307
+		clock-frequency = <409600000>;
308
+		clock-output-names = "ext-409m6";
309
+	};
267
310
 };