forked from ~ljy/RK356X_SDK_RELEASE

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hc
2023-12-11 1f93a7dfd1f8d5ff7a5c53246c7534fe2332d6f4 
 kernel/arch/arm64/boot/dts/rockchip/rk3568.dtsi
....@@ -59,7 +59,8 @@
5959 		spi1 = &spi1;
6060 		spi2 = &spi2;
6161 		spi3 = &spi3;
62
-		spi4 = &sfc; // for U-Boot
62
+		lvds0 = &lvds;
63
+		lvds1 = &lvds1;
6364 	};
6465 
6566 	cpus {
....@@ -126,12 +127,17 @@
126127 		opp-shared;
127128 
128129 		mbist-vmin = <825000 900000 950000>;
129
-		nvmem-cells = <&cpu_leakage>, <&core_pvtm>, <&mbist_vmin>;
130
-		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
130
+		nvmem-cells = <&cpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&cpu_opp_info>,
131
+			      <&specification_serial_number>, <&remark_spec_serial_number>;
132
+		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info",
133
+				   "specification_serial_number", "remark_spec_serial_number";
134
+		rockchip,supported-hw;
135
+		rockchip,max-volt = <1150000>;
131136 		rockchip,pvtm-voltage-sel = <
132137 			0        84000   0
133
-			84001    91000   1
134
-			91001    100000  2
138
+			84001    87000   1
139
+			87001    91000   2
140
+			91001    100000  3
135141 		>;
136142 		rockchip,pvtm-freq = <408000>;
137143 		rockchip,pvtm-volt = <900000>;
....@@ -146,77 +152,104 @@
146152 		rockchip,low-temp = <0>;
147153 		rockchip,low-temp-adjust-volt = <
148154 			/* MHz    MHz    uV */
149
-			   0      1608   75000
155
+			   0      1992   75000
150156 		>;
151157 
158
+		/* RK3568 && RK3568M cpu OPPs */
152159 		opp-408000000 {
160
+			opp-supported-hw = <0xfb 0xffff>;
153161 			opp-hz = /bits/ 64 <408000000>;
154162 			opp-microvolt = <850000 850000 1150000>;
155
-			opp-microvolt-L0 = <850000 850000 1150000>;
156
-			opp-microvolt-L1 = <825000 825000 1150000>;
157
-			opp-microvolt-L2 = <825000 825000 1150000>;
158163 			clock-latency-ns = <40000>;
159164 		};
160165 		opp-600000000 {
166
+			opp-supported-hw = <0xfb 0xffff>;
161167 			opp-hz = /bits/ 64 <600000000>;
162
-			opp-microvolt = <850000 825000 1150000>;
163
-			opp-microvolt-L0 = <850000 850000 1150000>;
164
-			opp-microvolt-L1 = <825000 825000 1150000>;
165
-			opp-microvolt-L2 = <825000 825000 1150000>;
168
+			opp-microvolt = <850000 850000 1150000>;
166169 			clock-latency-ns = <40000>;
167170 		};
168171 		opp-816000000 {
172
+			opp-supported-hw = <0xfb 0xffff>;
169173 			opp-hz = /bits/ 64 <816000000>;
170174 			opp-microvolt = <850000 850000 1150000>;
171
-			opp-microvolt-L0 = <850000 850000 1150000>;
172
-			opp-microvolt-L1 = <825000 825000 1150000>;
173
-			opp-microvolt-L2 = <825000 825000 1150000>;
174175 			clock-latency-ns = <40000>;
175176 			opp-suspend;
176177 		};
177178 		opp-1104000000 {
179
+			opp-supported-hw = <0xfb 0xffff>;
178180 			opp-hz = /bits/ 64 <1104000000>;
179181 			opp-microvolt = <900000 900000 1150000>;
180182 			opp-microvolt-L0 = <900000 900000 1150000>;
181
-			opp-microvolt-L1 = <825000 825000 1150000>;
182
-			opp-microvolt-L2 = <825000 825000 1150000>;
183
+			opp-microvolt-L1 = <850000 850000 1150000>;
184
+			opp-microvolt-L2 = <850000 850000 1150000>;
185
+			opp-microvolt-L3 = <850000 850000 1150000>;
183186 			clock-latency-ns = <40000>;
184187 		};
185188 		opp-1416000000 {
189
+			opp-supported-hw = <0xfb 0xffff>;
186190 			opp-hz = /bits/ 64 <1416000000>;
187
-			opp-microvolt = <1000000 1000000 1150000>;
188
-			opp-microvolt-L0 = <1000000 1000000 1150000>;
189
-			opp-microvolt-L1 = <925000 925000 1150000>;
190
-			opp-microvolt-L2 = <925000 925000 1150000>;
191
+			opp-microvolt = <1025000 1025000 1150000>;
192
+			opp-microvolt-L0 = <1025000 1025000 1150000>;
193
+			opp-microvolt-L1 = <975000 975000 1150000>;
194
+			opp-microvolt-L2 = <950000 950000 1150000>;
195
+			opp-microvolt-L3 = <925000 925000 1150000>;
191196 			clock-latency-ns = <40000>;
192197 		};
193198 		opp-1608000000 {
199
+			opp-supported-hw = <0xf9 0xffff>;
194200 			opp-hz = /bits/ 64 <1608000000>;
195
-			opp-microvolt = <1075000 1075000 1150000>;
196
-			opp-microvolt-L0 = <1075000 1075000 1150000>;
197
-			opp-microvolt-L1 = <1000000 1000000 1150000>;
198
-			opp-microvolt-L2 = <1000000 1000000 1150000>;
201
+			opp-microvolt = <1100000 1100000 1150000>;
202
+			opp-microvolt-L0 = <1100000 1100000 1150000>;
203
+			opp-microvolt-L1 = <1050000 1050000 1150000>;
204
+			opp-microvolt-L2 = <1025000 1025000 1150000>;
205
+			opp-microvolt-L3 = <1000000 1000000 1150000>;
199206 			clock-latency-ns = <40000>;
200207 		};
201208 		opp-1800000000 {
209
+			opp-supported-hw = <0xf9 0xffff>;
202210 			opp-hz = /bits/ 64 <1800000000>;
203
-			opp-microvolt = <1125000 1125000 1150000>;
204
-			opp-microvolt-L0 = <1125000 1125000 1150000>;
205
-			opp-microvolt-L1 = <1050000 1050000 1150000>;
206
-			opp-microvolt-L2 = <1050000 1050000 1150000>;
207
-			clock-latency-ns = <40000>;
208
-		};
209
-		opp-1992000000 {
210
-			opp-hz = /bits/ 64 <1992000000>;
211211 			opp-microvolt = <1150000 1150000 1150000>;
212212 			opp-microvolt-L0 = <1150000 1150000 1150000>;
213213 			opp-microvolt-L1 = <1100000 1100000 1150000>;
214214 			opp-microvolt-L2 = <1075000 1075000 1150000>;
215
+			opp-microvolt-L3 = <1050000 1050000 1150000>;
216
+			clock-latency-ns = <40000>;
217
+		};
218
+		opp-1992000000 {
219
+			opp-supported-hw = <0xf9 0xffff>;
220
+			opp-hz = /bits/ 64 <1992000000>;
221
+			opp-microvolt = <1150000 1150000 1150000>;
222
+			opp-microvolt-L0 = <1150000 1150000 1150000>;
223
+			opp-microvolt-L1 = <1150000 1150000 1150000>;
224
+			opp-microvolt-L2 = <1125000 1125000 1150000>;
225
+			opp-microvolt-L3 = <1100000 1100000 1150000>;
226
+			clock-latency-ns = <40000>;
227
+		};
228
+
229
+		/* RK3568J cpu OPPs */
230
+		opp-j-1008000000 {
231
+			opp-supported-hw = <0x04 0xffff>;
232
+			opp-hz = /bits/ 64 <1008000000>;
233
+			opp-microvolt = <850000 850000 1150000>;
234
+			clock-latency-ns = <40000>;
235
+		};
236
+		opp-j-1416000000 {
237
+			opp-supported-hw = <0x04 0xffff>;
238
+			opp-hz = /bits/ 64 <1416000000>;
239
+			opp-microvolt = <900000 900000 1150000>;
240
+			clock-latency-ns = <40000>;
241
+		};
242
+
243
+		/* RK3568M cpu OPPs */
244
+		opp-m-1608000000 {
245
+			opp-supported-hw = <0x02 0xffff>;
246
+			opp-hz = /bits/ 64 <1608000000>;
247
+			opp-microvolt = <1000000 1000000 1150000>;
215248 			clock-latency-ns = <40000>;
216249 		};
217250 	};
218251 
219
-	arm-pmu {
252
+	arm_pmu: arm-pmu {
220253 		compatible = "arm,cortex-a55-pmu", "arm,armv8-pmuv3";
221254 		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
222255 			     <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
....@@ -253,7 +286,7 @@
253286 				logo,kernel = "logo_kernel.bmp";
254287 				logo,mode = "center";
255288 				charge_logo,mode = "center";
256
-				connect = <&vp0_out_dsi1>;
289
+				connect = <&vp1_out_dsi1>;
257290 			};
258291 			route_edp: route-edp {
259292 				status = "disabled";
....@@ -261,7 +294,7 @@
261294 				logo,kernel = "logo_kernel.bmp";
262295 				logo,mode = "center";
263296 				charge_logo,mode = "center";
264
-				connect = <&vp0_out_edp>;
297
+				connect = <&vp1_out_edp>;
265298 			};
266299 			route_hdmi: route-hdmi {
267300 				status = "disabled";
....@@ -269,7 +302,7 @@
269302 				logo,kernel = "logo_kernel.bmp";
270303 				logo,mode = "center";
271304 				charge_logo,mode = "center";
272
-				connect = <&vp1_out_hdmi>;
305
+				connect = <&vp0_out_hdmi>;
273306 			};
274307 			route_lvds: route-lvds {
275308 				status = "disabled";
....@@ -290,12 +323,15 @@
290323 		};
291324 	};
292325 
293
-	firmware {
294
-		optee: optee {
295
-			compatible = "linaro,optee-tz";
296
-			method = "smc";
297
-		};
326
+	edac: edac {
327
+		compatible = "rockchip,rk3568-edac";
328
+		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
329
+			     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
330
+		interrupt-names = "ce", "ue";
331
+		status = "disabled";
332
+	};
298333 
334
+	firmware {
299335 		scmi: scmi {
300336 			compatible = "arm,scmi-smc";
301337 			shmem = <&scmi_shmem>;
....@@ -307,7 +343,7 @@
307343 				reg = <0x14>;
308344 				#clock-cells = <1>;
309345 
310
-				rockchip,clk-init = <1416000000>;
346
+				rockchip,clk-init = <1104000000>;
311347 			};
312348 		};
313349 
....@@ -315,6 +351,12 @@
315351 			compatible = "arm,sdei-1.0";
316352 			method = "smc";
317353 		};
354
+	};
355
+
356
+	mipi_csi2: mipi-csi2 {
357
+		compatible = "rockchip,rk3568-mipi-csi2";
358
+		rockchip,hw = <&mipi_csi2_hw>;
359
+		status = "disabled";
318360 	};
319361 
320362 	mpp_srv: mpp-srv {
....@@ -582,12 +624,15 @@
582624 			resets = <&cru SRST_USB3OTG0>;
583625 			reset-names = "usb3-otg";
584626 			snps,dis_enblslpm_quirk;
585
-			snps,dis-u1u2-quirk;
627
+			snps,dis-u1-entry-quirk;
628
+			snps,dis-u2-entry-quirk;
586629 			snps,dis-u2-freeclk-exists-quirk;
587630 			snps,dis-del-phy-power-chg-quirk;
588631 			snps,dis-tx-ipgap-linecheck-quirk;
589632 			snps,dis_rxdet_inp3_quirk;
590633 			snps,xhci-trb-ent-quirk;
634
+			snps,parkmode-disable-hs-quirk;
635
+			snps,parkmode-disable-ss-quirk;
591636 			quirk-skip-phy-init;
592637 			status = "disabled";
593638 		};
....@@ -621,6 +666,8 @@
621666 			snps,dis-tx-ipgap-linecheck-quirk;
622667 			snps,dis_rxdet_inp3_quirk;
623668 			snps,xhci-trb-ent-quirk;
669
+			snps,parkmode-disable-hs-quirk;
670
+			snps,parkmode-disable-ss-quirk;
624671 			status = "disabled";
625672 		};
626673 	};
....@@ -761,6 +808,34 @@
761808 						reg = <2>;
762809 						remote-endpoint = <&vp2_out_lvds>;
763810 						status = "disabled";
811
+					};
812
+				};
813
+			};
814
+		};
815
+
816
+		lvds1: lvds1 {
817
+			compatible = "rockchip,rk3568-lvds";
818
+			phys = <&video_phy1>;
819
+			phy-names = "phy";
820
+			status = "disabled";
821
+
822
+			ports {
823
+				#address-cells = <1>;
824
+				#size-cells = <0>;
825
+
826
+				port@0 {
827
+					reg = <0>;
828
+					#address-cells = <1>;
829
+					#size-cells = <0>;
830
+
831
+					lvds1_in_vp1: endpoint@0 {
832
+						reg = <0>;
833
+						remote-endpoint = <&vp1_out_lvds1>;
834
+					};
835
+
836
+					lvds1_in_vp2: endpoint@1 {
837
+						reg = <1>;
838
+						remote-endpoint = <&vp2_out_lvds1>;
764839 					};
765840 				};
766841 			};
....@@ -938,7 +1013,7 @@
9381013 		dmas = <&dmac0 0>, <&dmac0 1>;
9391014 		pinctrl-names = "default";
9401015 		pinctrl-0 = <&uart0_xfer>;
941
-		status = "okay";
1016
+		status = "disabled";
9421017 	};
9431018 
9441019 	pwm0: pwm@fdd70000 {
....@@ -1109,77 +1184,97 @@
11091184 		compatible = "operating-points-v2";
11101185 
11111186 		mbist-vmin = <825000 900000 950000>;
1112
-		nvmem-cells = <&npu_leakage>, <&core_pvtm>, <&mbist_vmin>;
1113
-		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
1187
+		nvmem-cells = <&npu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&npu_opp_info>,
1188
+			      <&specification_serial_number>, <&remark_spec_serial_number>;
1189
+		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info",
1190
+				   "specification_serial_number", "remark_spec_serial_number";
1191
+		rockchip,supported-hw;
1192
+		rockchip,max-volt = <1000000>;
11141193 		rockchip,temp-hysteresis = <5000>;
11151194 		rockchip,low-temp = <0>;
11161195 		rockchip,low-temp-adjust-volt = <
11171196 			/* MHz    MHz    uV */
1118
-			   0      700    50000
1197
+			   0      1000    50000
11191198 		>;
11201199 		rockchip,pvtm-voltage-sel = <
11211200 			0        84000   0
1122
-			84001    91000   1
1123
-			91001    100000  2
1201
+			84001    87000   1
1202
+			87001    91000   2
1203
+			91001    100000  3
11241204 		>;
11251205 		rockchip,pvtm-ch = <0 5>;
11261206 
1207
+		/* RK3568 && RK3568M npu OPPs */
11271208 		opp-200000000 {
1209
+			opp-supported-hw = <0xfb 0xffff>;
11281210 			opp-hz = /bits/ 64 <200000000>;
11291211 			opp-microvolt = <850000 850000 1000000>;
1130
-			opp-microvolt-L0 = <850000 850000 1000000>;
1131
-			opp-microvolt-L1 = <825000 825000 1000000>;
1132
-			opp-microvolt-L2 = <825000 825000 1000000>;
11331212 		};
11341213 		opp-300000000 {
1214
+			opp-supported-hw = <0xfb 0xffff>;
11351215 			opp-hz = /bits/ 64 <297000000>;
11361216 			opp-microvolt = <850000 850000 1000000>;
1137
-			opp-microvolt-L0 = <850000 850000 1000000>;
1138
-			opp-microvolt-L1 = <825000 825000 1000000>;
1139
-			opp-microvolt-L2 = <825000 825000 1000000>;
11401217 		};
11411218 		opp-400000000 {
1219
+			opp-supported-hw = <0xfb 0xffff>;
11421220 			opp-hz = /bits/ 64 <400000000>;
11431221 			opp-microvolt = <850000 850000 1000000>;
1144
-			opp-microvolt-L0 = <850000 850000 1000000>;
1145
-			opp-microvolt-L1 = <825000 825000 1000000>;
1146
-			opp-microvolt-L2 = <825000 825000 1000000>;
11471222 		};
11481223 		opp-600000000 {
1224
+			opp-supported-hw = <0xfb 0xffff>;
11491225 			opp-hz = /bits/ 64 <600000000>;
1150
-			opp-microvolt = <875000 875000 1000000>;
1151
-			opp-microvolt-L0 = <875000 875000 1000000>;
1152
-			opp-microvolt-L1 = <825000 825000 1000000>;
1153
-			opp-microvolt-L2 = <825000 825000 1000000>;
1226
+			opp-microvolt = <850000 850000 1000000>;
11541227 		};
11551228 		opp-700000000 {
1229
+			opp-supported-hw = <0xfb 0xffff>;
11561230 			opp-hz = /bits/ 64 <700000000>;
1157
-			opp-microvolt = <900000 900000 1000000>;
1158
-			opp-microvolt-L0 = <900000 900000 1000000>;
1231
+			opp-microvolt = <875000 875000 1000000>;
1232
+			opp-microvolt-L0 = <875000 875000 1000000>;
11591233 			opp-microvolt-L1 = <850000 850000 1000000>;
11601234 			opp-microvolt-L2 = <850000 850000 1000000>;
1235
+			opp-microvolt-L3 = <850000 850000 1000000>;
11611236 		};
11621237 		opp-800000000 {
1238
+			opp-supported-hw = <0xfb 0xffff>;
11631239 			opp-hz = /bits/ 64 <800000000>;
11641240 			opp-microvolt = <925000 925000 1000000>;
11651241 			opp-microvolt-L0 = <925000 925000 1000000>;
1166
-			opp-microvolt-L1 = <875000 875000 1000000>;
1242
+			opp-microvolt-L1 = <900000 900000 1000000>;
11671243 			opp-microvolt-L2 = <875000 875000 1000000>;
1244
+			opp-microvolt-L3 = <875000 875000 1000000>;
11681245 		};
11691246 		opp-900000000 {
1247
+			opp-supported-hw = <0xf9 0xffff>;
11701248 			opp-hz = /bits/ 64 <900000000>;
11711249 			opp-microvolt = <975000 975000 1000000>;
11721250 			opp-microvolt-L0 = <975000 975000 1000000>;
1173
-			opp-microvolt-L1 = <925000 925000 1000000>;
1174
-			opp-microvolt-L2 = <900000 900000 1000000>;
1251
+			opp-microvolt-L1 = <950000 950000 1000000>;
1252
+			opp-microvolt-L2 = <925000 925000 1000000>;
1253
+			opp-microvolt-L3 = <900000 900000 1000000>;
11751254 		};
11761255 		opp-1000000000 {
1256
+			opp-supported-hw = <0xf9 0xffff>;
11771257 			opp-hz = /bits/ 64 <1000000000>;
11781258 			opp-microvolt = <1000000 1000000 1000000>;
11791259 			opp-microvolt-L0 = <1000000 1000000 1000000>;
1180
-			opp-microvolt-L1 = <950000 950000 1000000>;
1181
-			opp-microvolt-L2 = <925000 925000 1000000>;
1260
+			opp-microvolt-L1 = <975000 975000 1000000>;
1261
+			opp-microvolt-L2 = <950000 950000 1000000>;
1262
+			opp-microvolt-L3 = <925000 925000 1000000>;
11821263 			status = "disabled";
1264
+		};
1265
+
1266
+		/* RK3568J npu OPPs */
1267
+		opp-j-600000000 {
1268
+			opp-supported-hw = <0x04 0xffff>;
1269
+			opp-hz = /bits/ 64 <600000000>;
1270
+			opp-microvolt = <900000 900000 1000000>;
1271
+		};
1272
+
1273
+		/* RK3568M npu OPPs */
1274
+		opp-m-900000000 {
1275
+			opp-supported-hw = <0x02 0xffff>;
1276
+			opp-hz = /bits/ 64 <900000000>;
1277
+			opp-microvolt = <925000 925000 1000000>;
11831278 		};
11841279 	};
11851280 
....@@ -1209,8 +1304,8 @@
12091304 			opp-hz = /bits/ 64 <700000000>;
12101305 			opp-microvolt = <900000>;
12111306 			opp-microvolt-L0 = <900000>;
1212
-			opp-microvolt-L1 = <850000>;
1213
-			opp-microvolt-L2 = <850000>;
1307
+			opp-microvolt-L1 = <875000>;
1308
+			opp-microvolt-L2 = <875000>;
12141309 		};
12151310 		opp-900000000 {
12161311 			opp-hz = /bits/ 64 <900000000>;
....@@ -1271,57 +1366,84 @@
12711366 		compatible = "operating-points-v2";
12721367 
12731368 		mbist-vmin = <825000 900000 950000>;
1274
-		nvmem-cells = <&gpu_leakage>, <&core_pvtm>, <&mbist_vmin>;
1275
-		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
1369
+		nvmem-cells = <&gpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&gpu_opp_info>,
1370
+			      <&specification_serial_number>, <&remark_spec_serial_number>;
1371
+		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info",
1372
+				   "specification_serial_number", "remark_spec_serial_number";
1373
+		rockchip,supported-hw;
1374
+		rockchip,max-volt = <1000000>;
1375
+		rockchip,temp-hysteresis = <5000>;
1376
+		rockchip,low-temp = <0>;
1377
+		rockchip,low-temp-adjust-volt = <
1378
+			/* MHz    MHz    uV */
1379
+			   0      800    50000
1380
+		>;
12761381 		rockchip,pvtm-voltage-sel = <
12771382 			0        84000   0
1278
-			84001    91000   1
1279
-			91001    100000  2
1383
+			84001    87000   1
1384
+			87001    91000   2
1385
+			91001    100000  3
12801386 		>;
12811387 		rockchip,pvtm-ch = <0 5>;
12821388 
1389
+		/* RK3568 && RK3568M gpu OPPs */
12831390 		opp-200000000 {
1391
+			opp-supported-hw = <0xfb 0xffff>;
12841392 			opp-hz = /bits/ 64 <200000000>;
1285
-			opp-microvolt = <850000>;
1286
-			opp-microvolt-L0 = <850000>;
1287
-			opp-microvolt-L1 = <825000>;
1288
-			opp-microvolt-L2 = <825000>;
1393
+			opp-microvolt = <850000 850000 1000000>;
12891394 		};
12901395 		opp-300000000 {
1396
+			opp-supported-hw = <0xfb 0xffff>;
12911397 			opp-hz = /bits/ 64 <300000000>;
1292
-			opp-microvolt = <850000>;
1293
-			opp-microvolt-L0 = <850000>;
1294
-			opp-microvolt-L1 = <825000>;
1295
-			opp-microvolt-L2 = <825000>;
1398
+			opp-microvolt = <850000 850000 1000000>;
12961399 		};
12971400 		opp-400000000 {
1401
+			opp-supported-hw = <0xfb 0xffff>;
12981402 			opp-hz = /bits/ 64 <400000000>;
1299
-			opp-microvolt = <850000>;
1300
-			opp-microvolt-L0 = <850000>;
1301
-			opp-microvolt-L1 = <825000>;
1302
-			opp-microvolt-L2 = <825000>;
1403
+			opp-microvolt = <850000 850000 1000000>;
13031404 		};
13041405 		opp-600000000 {
1406
+			opp-supported-hw = <0xfb 0xffff>;
13051407 			opp-hz = /bits/ 64 <600000000>;
1306
-			opp-microvolt = <875000>;
1307
-			opp-microvolt-L0 = <875000>;
1308
-			opp-microvolt-L1 = <825000>;
1309
-			opp-microvolt-L2 = <825000>;
1408
+			opp-microvolt = <900000 900000 1000000>;
1409
+			opp-microvolt-L0 = <900000 900000 1000000>;
1410
+			opp-microvolt-L1 = <875000 875000 1000000>;
1411
+			opp-microvolt-L2 = <850000 850000 1000000>;
1412
+			opp-microvolt-L3 = <850000 850000 1000000>;
13101413 		};
13111414 		opp-700000000 {
1415
+			opp-supported-hw = <0xfb 0xffff>;
13121416 			opp-hz = /bits/ 64 <700000000>;
1313
-			opp-microvolt = <950000>;
1314
-			opp-microvolt-L0 = <950000>;
1315
-			opp-microvolt-L1 = <900000>;
1316
-			opp-microvolt-L2 = <850000>;
1417
+			opp-microvolt = <950000 950000 1000000>;
1418
+			opp-microvolt-L0 = <950000 950000 1000000>;
1419
+			opp-microvolt-L1 = <925000 925000 1000000>;
1420
+			opp-microvolt-L2 = <900000 900000 1000000>;
1421
+			opp-microvolt-L3 = <875000 875000 1000000>;
13171422 		};
13181423 		opp-800000000 {
1424
+			opp-supported-hw = <0xf9 0xffff>;
13191425 			opp-hz = /bits/ 64 <800000000>;
1320
-			opp-microvolt = <1000000>;
1321
-			opp-microvolt-L0 = <1000000>;
1322
-			opp-microvolt-L1 = <950000>;
1323
-			opp-microvolt-L2 = <900000>;
1426
+			opp-microvolt = <1000000 1000000 1000000>;
1427
+			opp-microvolt-L0 = <1000000 1000000 1000000>;
1428
+			opp-microvolt-L1 = <975000 975000 1000000>;
1429
+			opp-microvolt-L2 = <950000 950000 1000000>;
1430
+			opp-microvolt-L3 = <925000 925000 1000000>;
13241431 		};
1432
+
1433
+		/* RK3568J gpu OPPs */
1434
+		opp-j-600000000 {
1435
+			opp-supported-hw = <0x04 0xffff>;
1436
+			opp-hz = /bits/ 64 <600000000>;
1437
+			opp-microvolt = <900000 900000 1000000>;
1438
+		};
1439
+
1440
+		/* RK3568M gpu OPPs */
1441
+		opp-m-800000000 {
1442
+			opp-supported-hw = <0x02 0xffff>;
1443
+			opp-hz = /bits/ 64 <800000000>;
1444
+			opp-microvolt = <950000 950000 1000000>;
1445
+		};
1446
+
13251447 	};
13261448 
13271449 	pvtm@fde80000 {
....@@ -1544,8 +1666,8 @@
15441666 			opp-hz = /bits/ 64 <297000000>;
15451667 			opp-microvolt = <900000>;
15461668 			opp-microvolt-L0 = <900000>;
1547
-			opp-microvolt-L1 = <850000>;
1548
-			opp-microvolt-L2 = <850000>;
1669
+			opp-microvolt-L1 = <875000>;
1670
+			opp-microvolt-L2 = <875000>;
15491671 		};
15501672 		opp-400000000 {
15511673 			opp-hz = /bits/ 64 <400000000>;
....@@ -1629,7 +1751,7 @@
16291751 			opp-hz = /bits/ 64 <297000000>;
16301752 			opp-microvolt = <900000>;
16311753 			opp-microvolt-L0 = <900000>;
1632
-			opp-microvolt-L1 = <850000>;
1754
+			opp-microvolt-L1 = <875000>;
16331755 		};
16341756 		opp-400000000 {
16351757 			opp-hz = /bits/ 64 <400000000>;
....@@ -1649,8 +1771,8 @@
16491771 		status = "disabled";
16501772 	};
16511773 
1652
-	mipi_csi2: mipi-csi2@fdfb0000 {
1653
-		compatible = "rockchip,rk3568-mipi-csi2";
1774
+	mipi_csi2_hw: mipi-csi2-hw@fdfb0000 {
1775
+		compatible = "rockchip,rk3568-mipi-csi2-hw";
16541776 		reg = <0x0 0xfdfb0000 0x0 0x10000>;
16551777 		reg-names = "csihost_regs";
16561778 		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
....@@ -1739,7 +1861,7 @@
17391861 		rockchip,grf = <&grf>;
17401862 		power-domains = <&power RK3568_PD_VI>;
17411863 		iommus = <&rkisp_mmu>;
1742
-		rockchip,iq-feature = /bits/ 64 <0x3FBFFFE67FF>;
1864
+		rockchip,iq-feature = /bits/ 64 <0x1BFBFFFE67FF>;
17431865 		status = "disabled";
17441866 	};
17451867 
....@@ -1768,6 +1890,13 @@
17681890 		status = "disabled";
17691891 	};
17701892 
1893
+	gmac_uio1: uio@fe010000 {
1894
+		compatible = "rockchip,uio-gmac";
1895
+		reg = <0x0 0xfe010000 0x0 0x10000>;
1896
+		rockchip,ethernet = <&gmac1>;
1897
+		status = "disabled";
1898
+	};
1899
+
17711900 	gmac1: ethernet@fe010000 {
17721901 		compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
17731902 		reg = <0x0 0xfe010000 0x0 0x10000>;
....@@ -1779,12 +1908,12 @@
17791908 			 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
17801909 			 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
17811910 			 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>,
1782
-			 <&cru PCLK_XPCS>;
1911
+			 <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>;
17831912 		clock-names = "stmmaceth", "mac_clk_rx",
17841913 			      "mac_clk_tx", "clk_mac_refout",
17851914 			      "aclk_mac", "pclk_mac",
17861915 			      "clk_mac_speed", "ptp_ref",
1787
-			      "pclk_xpcs";
1916
+			      "pclk_xpcs", "clk_xpcs_eee";
17881917 		resets = <&cru SRST_A_GMAC1>;
17891918 		reset-names = "stmmaceth";
17901919 
....@@ -1890,6 +2019,11 @@
18902019 					reg = <4>;
18912020 					remote-endpoint = <&lvds_in_vp1>;
18922021 				};
2022
+
2023
+				vp1_out_lvds1: endpoint@5 {
2024
+					reg = <5>;
2025
+					remote-endpoint = <&lvds1_in_vp1>;
2026
+				};
18932027 			};
18942028 
18952029 			vp2: port@2 {
....@@ -1907,6 +2041,11 @@
19072041 					reg = <1>;
19082042 					remote-endpoint = <&rgb_in_vp2>;
19092043 				};
2044
+
2045
+				vp2_out_lvds1: endpoint@2 {
2046
+					reg = <2>;
2047
+					remote-endpoint = <&lvds1_in_vp2>;
2048
+				};
19102049 			};
19112050 		};
19122051 	};
....@@ -1919,6 +2058,7 @@
19192058 		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
19202059 		clock-names = "aclk", "iface";
19212060 		#iommu-cells = <0>;
2061
+		rockchip,disable-device-link-resume;
19222062 		status = "disabled";
19232063 	};
19242064 
....@@ -1926,12 +2066,12 @@
19262066 		compatible = "rockchip,rk3568-mipi-dsi";
19272067 		reg = <0x0 0xfe060000 0x0 0x10000>;
19282068 		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1929
-		clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>, <&video_phy0>;
1930
-		clock-names = "pclk", "hclk", "hs_clk";
2069
+		clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>;
2070
+		clock-names = "pclk", "hclk";
19312071 		resets = <&cru SRST_P_DSITX_0>;
19322072 		reset-names = "apb";
19332073 		phys = <&video_phy0>;
1934
-		phy-names = "mipi_dphy";
2074
+		phy-names = "dphy";
19352075 		power-domains = <&power RK3568_PD_VO>;
19362076 		rockchip,grf = <&grf>;
19372077 		#address-cells = <1>;
....@@ -1966,12 +2106,12 @@
19662106 		compatible = "rockchip,rk3568-mipi-dsi";
19672107 		reg = <0x0 0xfe070000 0x0 0x10000>;
19682108 		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
1969
-		clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>, <&video_phy1>;
1970
-		clock-names = "pclk", "hclk", "hs_clk";
2109
+		clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>;
2110
+		clock-names = "pclk", "hclk";
19712111 		resets = <&cru SRST_P_DSITX_1>;
19722112 		reset-names = "apb";
19732113 		phys = <&video_phy1>;
1974
-		phy-names = "mipi_dphy";
2114
+		phy-names = "dphy";
19752115 		power-domains = <&power RK3568_PD_VO>;
19762116 		rockchip,grf = <&grf>;
19772117 		#address-cells = <1>;
....@@ -2024,7 +2164,7 @@
20242164 			#address-cells = <1>;
20252165 			#size-cells = <0>;
20262166 
2027
-			hdmi_in: port {
2167
+			port@0 {
20282168 				reg = <0>;
20292169 				#address-cells = <1>;
20302170 				#size-cells = <0>;
....@@ -2034,6 +2174,7 @@
20342174 					remote-endpoint = <&vp0_out_hdmi>;
20352175 					status = "disabled";
20362176 				};
2177
+
20372178 				hdmi_in_vp1: endpoint@1 {
20382179 					reg = <1>;
20392180 					remote-endpoint = <&vp1_out_hdmi>;
....@@ -2324,8 +2465,12 @@
23242465 		compatible = "operating-points-v2";
23252466 
23262467 		mbist-vmin = <825000 900000 950000>;
2327
-		nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>;
2328
-		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
2468
+		nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>, <&dmc_opp_info>,
2469
+			      <&specification_serial_number>, <&remark_spec_serial_number>;
2470
+		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info",
2471
+				   "specification_serial_number", "remark_spec_serial_number";
2472
+		rockchip,supported-hw;
2473
+		rockchip,max-volt = <1000000>;
23292474 		rockchip,temp-hysteresis = <5000>;
23302475 		rockchip,low-temp = <0>;
23312476 		rockchip,low-temp-adjust-volt = <
....@@ -2342,17 +2487,21 @@
23422487 		>;
23432488 		rockchip,pvtm-ch = <0 5>;
23442489 
2490
+		/* RK3568 dmc OPPs */
23452491 		opp-1560000000 {
2492
+			opp-supported-hw = <0xf9 0xffff>;
23462493 			opp-hz = /bits/ 64 <1560000000>;
2347
-			opp-microvolt = <900000>;
2348
-			opp-microvolt-L0 = <900000>;
2349
-			opp-microvolt-L1 = <850000>;
2494
+			opp-microvolt = <900000 900000 1000000>;
2495
+			opp-microvolt-L0 = <900000 900000 1000000>;
2496
+			opp-microvolt-L1 = <875000 875000 1000000>;
23502497 		};
2351
-	};
23522498 
2353
-	dmcdbg: dmcdbg {
2354
-		compatible = "rockchip,rk3568-dmcdbg";
2355
-		status = "disabled";
2499
+		/* RK3568J/M dmc OPPs */
2500
+		opp-j-m-1560000000 {
2501
+			opp-supported-hw = <0x06 0xffff>;
2502
+			opp-hz = /bits/ 64 <1560000000>;
2503
+			opp-microvolt = <875000 875000 1000000>;
2504
+		};
23562505 	};
23572506 
23582507 	pcie2x1: pcie@fe260000 {
....@@ -2516,6 +2665,13 @@
25162665 		};
25172666 	};
25182667 
2668
+	gmac_uio0: uio@fe2a0000 {
2669
+		compatible = "rockchip,uio-gmac";
2670
+		reg = <0x0 0xfe2a0000 0x0 0x10000>;
2671
+		rockchip,ethernet = <&gmac0>;
2672
+		status = "disabled";
2673
+	};
2674
+
25192675 	gmac0: ethernet@fe2a0000 {
25202676 		compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
25212677 		reg = <0x0 0xfe2a0000 0x0 0x10000>;
....@@ -2527,12 +2683,12 @@
25272683 			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
25282684 			 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
25292685 			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
2530
-			 <&cru PCLK_XPCS>;
2686
+			 <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>;
25312687 		clock-names = "stmmaceth", "mac_clk_rx",
25322688 			      "mac_clk_tx", "clk_mac_refout",
25332689 			      "aclk_mac", "pclk_mac",
25342690 			      "clk_mac_speed", "ptp_ref",
2535
-			      "pclk_xpcs";
2691
+			      "pclk_xpcs", "clk_xpcs_eee";
25362692 		resets = <&cru SRST_A_GMAC0>;
25372693 		reset-names = "stmmaceth";
25382694 
....@@ -2597,7 +2753,7 @@
25972753 		status = "disabled";
25982754 	};
25992755 
2600
-	sfc: sfc@fe300000 {
2756
+	sfc: spi@fe300000 {
26012757 		compatible = "rockchip,sfc";
26022758 		reg = <0x0 0xfe300000 0x0 0x4000>;
26032759 		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
....@@ -2605,11 +2761,13 @@
26052761 		clock-names = "clk_sfc", "hclk_sfc";
26062762 		assigned-clocks = <&cru SCLK_SFC>;
26072763 		assigned-clock-rates = <100000000>;
2764
+		#address-cells = <1>;
2765
+		#size-cells = <0>;
26082766 		status = "disabled";
26092767 	};
26102768 
26112769 	sdhci: sdhci@fe310000 {
2612
-		compatible = "rockchip,dwcmshc-sdhci", "snps,dwcmshc-sdhci";
2770
+		compatible = "rockchip,rk3568-dwcmshc", "rockchip,dwcmshc-sdhci";
26132771 		reg = <0x0 0xfe310000 0x0 0x10000>;
26142772 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
26152773 		assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>,
....@@ -2619,6 +2777,10 @@
26192777 			 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
26202778 			 <&cru TCLK_EMMC>;
26212779 		clock-names = "core", "bus", "axi", "block", "timer";
2780
+		resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
2781
+			 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
2782
+			 <&cru SRST_T_EMMC>;
2783
+		reset-names = "core", "bus", "axi", "block", "timer";
26222784 		status = "disabled";
26232785 	};
26242786 
....@@ -2671,6 +2833,10 @@
26712833 		cpu_code: cpu-code@2 {
26722834 			reg = <0x02 0x2>;
26732835 		};
2836
+		specification_serial_number: specification-serial-number@7 {
2837
+			reg = <0x07 0x1>;
2838
+			bits = <0 5>;
2839
+		};
26742840 		otp_cpu_version: cpu-version@8 {
26752841 			reg = <0x08 0x1>;
26762842 			bits = <3 3>;
....@@ -2717,6 +2883,22 @@
27172883 		};
27182884 		tsadc_trim_base: tsadc-trim-base@32 {
27192885 			reg = <0x32 0x1>;
2886
+		};
2887
+		cpu_opp_info: cpu-opp-info@36 {
2888
+			reg = <0x36 0x6>;
2889
+		};
2890
+		gpu_opp_info: gpu-opp-info@3c {
2891
+			reg = <0x3c 0x6>;
2892
+		};
2893
+		npu_opp_info: npu-opp-info@42 {
2894
+			reg = <0x42 0x6>;
2895
+		};
2896
+		dmc_opp_info: dmc-opp-info@48 {
2897
+			reg = <0x48 0x6>;
2898
+		};
2899
+		remark_spec_serial_number: remark-spec-serial-number@56 {
2900
+			reg = <0x56 0x1>;
2901
+			bits = <0 5>;
27202902 		};
27212903 	};
27222904 
....@@ -2809,7 +2991,7 @@
28092991 	};
28102992 
28112993 	pdm: pdm@fe440000 {
2812
-		compatible = "rockchip,rk3568-pdm";
2994
+		compatible = "rockchip,rk3568-pdm", "rockchip,pdm";
28132995 		reg = <0x0 0xfe440000 0x0 0x1000>;
28142996 		clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
28152997 		clock-names = "pdm_clk", "pdm_hclk";
....@@ -3049,6 +3231,7 @@
30493231 		pinctrl-names = "default", "high_speed";
30503232 		pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
30513233 		pinctrl-1 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins_hs>;
3234
+		num-cs = <2>;
30523235 		status = "disabled";
30533236 	};
30543237 
....@@ -3065,6 +3248,7 @@
30653248 		pinctrl-names = "default", "high_speed";
30663249 		pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
30673250 		pinctrl-1 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins_hs>;
3251
+		num-cs = <2>;
30683252 		status = "disabled";
30693253 	};
30703254 
....@@ -3081,6 +3265,7 @@
30813265 		pinctrl-names = "default", "high_speed";
30823266 		pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
30833267 		pinctrl-1 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins_hs>;
3268
+		num-cs = <2>;
30843269 		status = "disabled";
30853270 	};
30863271 
....@@ -3097,6 +3282,7 @@
30973282 		pinctrl-names = "default", "high_speed";
30983283 		pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
30993284 		pinctrl-1 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins_hs>;
3285
+		num-cs = <2>;
31003286 		status = "disabled";
31013287 	};
31023288 
....@@ -3111,7 +3297,7 @@
31113297 		dmas = <&dmac0 2>, <&dmac0 3>;
31123298 		pinctrl-names = "default";
31133299 		pinctrl-0 = <&uart1m0_xfer>;
3114
-		status = "okay";
3300
+		status = "disabled";
31153301 	};
31163302 
31173303 	uart2: serial@fe660000 {
....@@ -3475,31 +3661,33 @@
34753661 		status = "disabled";
34763662 	};
34773663 
3478
-	video_phy0: video-phy@fe850000 {
3479
-		compatible = "rockchip,rk3568-video-phy";
3664
+	video_phy0: phy@fe850000 {
3665
+		compatible = "rockchip,rk3568-dsi-dphy", "rockchip,rk3568-video-phy";
34803666 		reg = <0x0 0xfe850000  0x0 0x10000>,
34813667 		      <0x0 0xfe060000 0x0 0x10000>;
3668
+		reg-names = "phy", "host";
34823669 		clocks = <&pmucru CLK_MIPIDSIPHY0_REF>,
34833670 			 <&cru PCLK_MIPIDSIPHY0>, <&cru PCLK_DSITX_0>;
3484
-		clock-names = "ref", "pclk_phy", "pclk_host";
3671
+		clock-names = "ref", "pclk", "pclk_host";
34853672 		#clock-cells = <0>;
34863673 		resets = <&cru SRST_P_MIPIDSIPHY0>;
3487
-		reset-names = "rst";
3674
+		reset-names = "apb";
34883675 		power-domains = <&power RK3568_PD_VO>;
34893676 		#phy-cells = <0>;
34903677 		status = "disabled";
34913678 	};
34923679 
3493
-	video_phy1: video-phy@fe860000 {
3494
-		compatible = "rockchip,rk3568-video-phy";
3680
+	video_phy1: phy@fe860000 {
3681
+		compatible = "rockchip,rk3568-dsi-dphy", "rockchip,rk3568-video-phy";
34953682 		reg = <0x0 0xfe860000  0x0 0x10000>,
34963683 		      <0x0 0xfe070000 0x0 0x10000>;
3684
+		reg-names = "phy", "host";
34973685 		clocks = <&pmucru CLK_MIPIDSIPHY1_REF>,
34983686 			 <&cru PCLK_MIPIDSIPHY1>, <&cru PCLK_DSITX_1>;
3499
-		clock-names = "ref", "pclk_phy", "pclk_host";
3687
+		clock-names = "ref", "pclk", "pclk_host";
35003688 		#clock-cells = <0>;
35013689 		resets = <&cru SRST_P_MIPIDSIPHY1>;
3502
-		reset-names = "rst";
3690
+		reset-names = "apb";
35033691 		power-domains = <&power RK3568_PD_VO>;
35043692 		#phy-cells = <0>;
35053693 		status = "disabled";
....@@ -3609,7 +3797,7 @@
36093797 		#size-cells = <2>;
36103798 		ranges;
36113799 
3612
-		gpio0: gpio@fdd60000 {
3800
+		gpio0: gpio0@fdd60000 {
36133801 			compatible = "rockchip,gpio-bank";
36143802 			reg = <0x0 0xfdd60000 0x0 0x100>;
36153803 			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
....@@ -3617,12 +3805,11 @@
36173805 
36183806 			gpio-controller;
36193807 			#gpio-cells = <2>;
3620
-			gpio-ranges = <&pinctrl 0 0 32>;
36213808 			interrupt-controller;
36223809 			#interrupt-cells = <2>;
36233810 		};
36243811 
3625
-		gpio1: gpio@fe740000 {
3812
+		gpio1: gpio1@fe740000 {
36263813 			compatible = "rockchip,gpio-bank";
36273814 			reg = <0x0 0xfe740000 0x0 0x100>;
36283815 			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
....@@ -3630,12 +3817,11 @@
36303817 
36313818 			gpio-controller;
36323819 			#gpio-cells = <2>;
3633
-			gpio-ranges = <&pinctrl 0 32 32>;
36343820 			interrupt-controller;
36353821 			#interrupt-cells = <2>;
36363822 		};
36373823 
3638
-		gpio2: gpio@fe750000 {
3824
+		gpio2: gpio2@fe750000 {
36393825 			compatible = "rockchip,gpio-bank";
36403826 			reg = <0x0 0xfe750000 0x0 0x100>;
36413827 			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
....@@ -3643,12 +3829,11 @@
36433829 
36443830 			gpio-controller;
36453831 			#gpio-cells = <2>;
3646
-			gpio-ranges = <&pinctrl 0 64 32>;
36473832 			interrupt-controller;
36483833 			#interrupt-cells = <2>;
36493834 		};
36503835 
3651
-		gpio3: gpio@fe760000 {
3836
+		gpio3: gpio3@fe760000 {
36523837 			compatible = "rockchip,gpio-bank";
36533838 			reg = <0x0 0xfe760000 0x0 0x100>;
36543839 			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
....@@ -3656,12 +3841,11 @@
36563841 
36573842 			gpio-controller;
36583843 			#gpio-cells = <2>;
3659
-			gpio-ranges = <&pinctrl 0 96 32>;
36603844 			interrupt-controller;
36613845 			#interrupt-cells = <2>;
36623846 		};
36633847 
3664
-		gpio4: gpio@fe770000 {
3848
+		gpio4: gpio4@fe770000 {
36653849 			compatible = "rockchip,gpio-bank";
36663850 			reg = <0x0 0xfe770000 0x0 0x100>;
36673851 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
....@@ -3669,7 +3853,6 @@
36693853 
36703854 			gpio-controller;
36713855 			#gpio-cells = <2>;
3672
-			gpio-ranges = <&pinctrl 0 128 32>;
36733856 			interrupt-controller;
36743857 			#interrupt-cells = <2>;
36753858 		};