forked from ~ljy/RK356X_SDK_RELEASE

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2023-12-11 1f93a7dfd1f8d5ff7a5c53246c7534fe2332d6f4 
 kernel/arch/arm64/boot/dts/rockchip/rk3568.dtsi
....@@ -22,7 +22,6 @@
2222 	#address-cells = <2>;
2323 	#size-cells = <2>;
2424 
25
-
2625 	aliases {
2726 		csi2dphy0 = &csi2_dphy0;
2827 		csi2dphy1 = &csi2_dphy1;
....@@ -60,7 +59,8 @@
6059 		spi1 = &spi1;
6160 		spi2 = &spi2;
6261 		spi3 = &spi3;
63
-		spi4 = &sfc; // for U-Boot
62
+		lvds0 = &lvds;
63
+		lvds1 = &lvds1;
6464 	};
6565 
6666 	cpus {
....@@ -127,12 +127,17 @@
127127 		opp-shared;
128128 
129129 		mbist-vmin = <825000 900000 950000>;
130
-		nvmem-cells = <&cpu_leakage>, <&core_pvtm>, <&mbist_vmin>;
131
-		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
130
+		nvmem-cells = <&cpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&cpu_opp_info>,
131
+			      <&specification_serial_number>, <&remark_spec_serial_number>;
132
+		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info",
133
+				   "specification_serial_number", "remark_spec_serial_number";
134
+		rockchip,supported-hw;
135
+		rockchip,max-volt = <1150000>;
132136 		rockchip,pvtm-voltage-sel = <
133137 			0        84000   0
134
-			84001    91000   1
135
-			91001    100000  2
138
+			84001    87000   1
139
+			87001    91000   2
140
+			91001    100000  3
136141 		>;
137142 		rockchip,pvtm-freq = <408000>;
138143 		rockchip,pvtm-volt = <900000>;
....@@ -147,77 +152,104 @@
147152 		rockchip,low-temp = <0>;
148153 		rockchip,low-temp-adjust-volt = <
149154 			/* MHz    MHz    uV */
150
-			   0      1608   75000
155
+			   0      1992   75000
151156 		>;
152157 
158
+		/* RK3568 && RK3568M cpu OPPs */
153159 		opp-408000000 {
160
+			opp-supported-hw = <0xfb 0xffff>;
154161 			opp-hz = /bits/ 64 <408000000>;
155162 			opp-microvolt = <850000 850000 1150000>;
156
-			opp-microvolt-L0 = <850000 850000 1150000>;
157
-			opp-microvolt-L1 = <825000 825000 1150000>;
158
-			opp-microvolt-L2 = <825000 825000 1150000>;
159163 			clock-latency-ns = <40000>;
160164 		};
161165 		opp-600000000 {
166
+			opp-supported-hw = <0xfb 0xffff>;
162167 			opp-hz = /bits/ 64 <600000000>;
163
-			opp-microvolt = <850000 825000 1150000>;
164
-			opp-microvolt-L0 = <850000 850000 1150000>;
165
-			opp-microvolt-L1 = <825000 825000 1150000>;
166
-			opp-microvolt-L2 = <825000 825000 1150000>;
168
+			opp-microvolt = <850000 850000 1150000>;
167169 			clock-latency-ns = <40000>;
168170 		};
169171 		opp-816000000 {
172
+			opp-supported-hw = <0xfb 0xffff>;
170173 			opp-hz = /bits/ 64 <816000000>;
171174 			opp-microvolt = <850000 850000 1150000>;
172
-			opp-microvolt-L0 = <850000 850000 1150000>;
173
-			opp-microvolt-L1 = <825000 825000 1150000>;
174
-			opp-microvolt-L2 = <825000 825000 1150000>;
175175 			clock-latency-ns = <40000>;
176176 			opp-suspend;
177177 		};
178178 		opp-1104000000 {
179
+			opp-supported-hw = <0xfb 0xffff>;
179180 			opp-hz = /bits/ 64 <1104000000>;
180181 			opp-microvolt = <900000 900000 1150000>;
181182 			opp-microvolt-L0 = <900000 900000 1150000>;
182
-			opp-microvolt-L1 = <825000 825000 1150000>;
183
-			opp-microvolt-L2 = <825000 825000 1150000>;
183
+			opp-microvolt-L1 = <850000 850000 1150000>;
184
+			opp-microvolt-L2 = <850000 850000 1150000>;
185
+			opp-microvolt-L3 = <850000 850000 1150000>;
184186 			clock-latency-ns = <40000>;
185187 		};
186188 		opp-1416000000 {
189
+			opp-supported-hw = <0xfb 0xffff>;
187190 			opp-hz = /bits/ 64 <1416000000>;
188
-			opp-microvolt = <1000000 1000000 1150000>;
189
-			opp-microvolt-L0 = <1000000 1000000 1150000>;
190
-			opp-microvolt-L1 = <925000 925000 1150000>;
191
-			opp-microvolt-L2 = <925000 925000 1150000>;
191
+			opp-microvolt = <1025000 1025000 1150000>;
192
+			opp-microvolt-L0 = <1025000 1025000 1150000>;
193
+			opp-microvolt-L1 = <975000 975000 1150000>;
194
+			opp-microvolt-L2 = <950000 950000 1150000>;
195
+			opp-microvolt-L3 = <925000 925000 1150000>;
192196 			clock-latency-ns = <40000>;
193197 		};
194198 		opp-1608000000 {
199
+			opp-supported-hw = <0xf9 0xffff>;
195200 			opp-hz = /bits/ 64 <1608000000>;
196
-			opp-microvolt = <1075000 1075000 1150000>;
197
-			opp-microvolt-L0 = <1075000 1075000 1150000>;
198
-			opp-microvolt-L1 = <1000000 1000000 1150000>;
199
-			opp-microvolt-L2 = <1000000 1000000 1150000>;
201
+			opp-microvolt = <1100000 1100000 1150000>;
202
+			opp-microvolt-L0 = <1100000 1100000 1150000>;
203
+			opp-microvolt-L1 = <1050000 1050000 1150000>;
204
+			opp-microvolt-L2 = <1025000 1025000 1150000>;
205
+			opp-microvolt-L3 = <1000000 1000000 1150000>;
200206 			clock-latency-ns = <40000>;
201207 		};
202208 		opp-1800000000 {
209
+			opp-supported-hw = <0xf9 0xffff>;
203210 			opp-hz = /bits/ 64 <1800000000>;
204
-			opp-microvolt = <1125000 1125000 1150000>;
205
-			opp-microvolt-L0 = <1125000 1125000 1150000>;
206
-			opp-microvolt-L1 = <1050000 1050000 1150000>;
207
-			opp-microvolt-L2 = <1050000 1050000 1150000>;
208
-			clock-latency-ns = <40000>;
209
-		};
210
-		opp-1992000000 {
211
-			opp-hz = /bits/ 64 <1992000000>;
212211 			opp-microvolt = <1150000 1150000 1150000>;
213212 			opp-microvolt-L0 = <1150000 1150000 1150000>;
214213 			opp-microvolt-L1 = <1100000 1100000 1150000>;
215214 			opp-microvolt-L2 = <1075000 1075000 1150000>;
215
+			opp-microvolt-L3 = <1050000 1050000 1150000>;
216
+			clock-latency-ns = <40000>;
217
+		};
218
+		opp-1992000000 {
219
+			opp-supported-hw = <0xf9 0xffff>;
220
+			opp-hz = /bits/ 64 <1992000000>;
221
+			opp-microvolt = <1150000 1150000 1150000>;
222
+			opp-microvolt-L0 = <1150000 1150000 1150000>;
223
+			opp-microvolt-L1 = <1150000 1150000 1150000>;
224
+			opp-microvolt-L2 = <1125000 1125000 1150000>;
225
+			opp-microvolt-L3 = <1100000 1100000 1150000>;
226
+			clock-latency-ns = <40000>;
227
+		};
228
+
229
+		/* RK3568J cpu OPPs */
230
+		opp-j-1008000000 {
231
+			opp-supported-hw = <0x04 0xffff>;
232
+			opp-hz = /bits/ 64 <1008000000>;
233
+			opp-microvolt = <850000 850000 1150000>;
234
+			clock-latency-ns = <40000>;
235
+		};
236
+		opp-j-1416000000 {
237
+			opp-supported-hw = <0x04 0xffff>;
238
+			opp-hz = /bits/ 64 <1416000000>;
239
+			opp-microvolt = <900000 900000 1150000>;
240
+			clock-latency-ns = <40000>;
241
+		};
242
+
243
+		/* RK3568M cpu OPPs */
244
+		opp-m-1608000000 {
245
+			opp-supported-hw = <0x02 0xffff>;
246
+			opp-hz = /bits/ 64 <1608000000>;
247
+			opp-microvolt = <1000000 1000000 1150000>;
216248 			clock-latency-ns = <40000>;
217249 		};
218250 	};
219251 
220
-	arm-pmu {
252
+	arm_pmu: arm-pmu {
221253 		compatible = "arm,cortex-a55-pmu", "arm,armv8-pmuv3";
222254 		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
223255 			     <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
....@@ -291,12 +323,15 @@
291323 		};
292324 	};
293325 
294
-	firmware {
295
-		optee: optee {
296
-			compatible = "linaro,optee-tz";
297
-			method = "smc";
298
-		};
326
+	edac: edac {
327
+		compatible = "rockchip,rk3568-edac";
328
+		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
329
+			     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
330
+		interrupt-names = "ce", "ue";
331
+		status = "disabled";
332
+	};
299333 
334
+	firmware {
300335 		scmi: scmi {
301336 			compatible = "arm,scmi-smc";
302337 			shmem = <&scmi_shmem>;
....@@ -308,7 +343,7 @@
308343 				reg = <0x14>;
309344 				#clock-cells = <1>;
310345 
311
-				rockchip,clk-init = <1416000000>;
346
+				rockchip,clk-init = <1104000000>;
312347 			};
313348 		};
314349 
....@@ -316,6 +351,12 @@
316351 			compatible = "arm,sdei-1.0";
317352 			method = "smc";
318353 		};
354
+	};
355
+
356
+	mipi_csi2: mipi-csi2 {
357
+		compatible = "rockchip,rk3568-mipi-csi2";
358
+		rockchip,hw = <&mipi_csi2_hw>;
359
+		status = "disabled";
319360 	};
320361 
321362 	mpp_srv: mpp-srv {
....@@ -583,12 +624,15 @@
583624 			resets = <&cru SRST_USB3OTG0>;
584625 			reset-names = "usb3-otg";
585626 			snps,dis_enblslpm_quirk;
586
-			snps,dis-u1u2-quirk;
627
+			snps,dis-u1-entry-quirk;
628
+			snps,dis-u2-entry-quirk;
587629 			snps,dis-u2-freeclk-exists-quirk;
588630 			snps,dis-del-phy-power-chg-quirk;
589631 			snps,dis-tx-ipgap-linecheck-quirk;
590632 			snps,dis_rxdet_inp3_quirk;
591633 			snps,xhci-trb-ent-quirk;
634
+			snps,parkmode-disable-hs-quirk;
635
+			snps,parkmode-disable-ss-quirk;
592636 			quirk-skip-phy-init;
593637 			status = "disabled";
594638 		};
....@@ -622,6 +666,8 @@
622666 			snps,dis-tx-ipgap-linecheck-quirk;
623667 			snps,dis_rxdet_inp3_quirk;
624668 			snps,xhci-trb-ent-quirk;
669
+			snps,parkmode-disable-hs-quirk;
670
+			snps,parkmode-disable-ss-quirk;
625671 			status = "disabled";
626672 		};
627673 	};
....@@ -762,6 +808,34 @@
762808 						reg = <2>;
763809 						remote-endpoint = <&vp2_out_lvds>;
764810 						status = "disabled";
811
+					};
812
+				};
813
+			};
814
+		};
815
+
816
+		lvds1: lvds1 {
817
+			compatible = "rockchip,rk3568-lvds";
818
+			phys = <&video_phy1>;
819
+			phy-names = "phy";
820
+			status = "disabled";
821
+
822
+			ports {
823
+				#address-cells = <1>;
824
+				#size-cells = <0>;
825
+
826
+				port@0 {
827
+					reg = <0>;
828
+					#address-cells = <1>;
829
+					#size-cells = <0>;
830
+
831
+					lvds1_in_vp1: endpoint@0 {
832
+						reg = <0>;
833
+						remote-endpoint = <&vp1_out_lvds1>;
834
+					};
835
+
836
+					lvds1_in_vp2: endpoint@1 {
837
+						reg = <1>;
838
+						remote-endpoint = <&vp2_out_lvds1>;
765839 					};
766840 				};
767841 			};
....@@ -939,7 +1013,7 @@
9391013 		dmas = <&dmac0 0>, <&dmac0 1>;
9401014 		pinctrl-names = "default";
9411015 		pinctrl-0 = <&uart0_xfer>;
942
-		status = "okay";
1016
+		status = "disabled";
9431017 	};
9441018 
9451019 	pwm0: pwm@fdd70000 {
....@@ -1110,77 +1184,97 @@
11101184 		compatible = "operating-points-v2";
11111185 
11121186 		mbist-vmin = <825000 900000 950000>;
1113
-		nvmem-cells = <&npu_leakage>, <&core_pvtm>, <&mbist_vmin>;
1114
-		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
1187
+		nvmem-cells = <&npu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&npu_opp_info>,
1188
+			      <&specification_serial_number>, <&remark_spec_serial_number>;
1189
+		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info",
1190
+				   "specification_serial_number", "remark_spec_serial_number";
1191
+		rockchip,supported-hw;
1192
+		rockchip,max-volt = <1000000>;
11151193 		rockchip,temp-hysteresis = <5000>;
11161194 		rockchip,low-temp = <0>;
11171195 		rockchip,low-temp-adjust-volt = <
11181196 			/* MHz    MHz    uV */
1119
-			   0      700    50000
1197
+			   0      1000    50000
11201198 		>;
11211199 		rockchip,pvtm-voltage-sel = <
11221200 			0        84000   0
1123
-			84001    91000   1
1124
-			91001    100000  2
1201
+			84001    87000   1
1202
+			87001    91000   2
1203
+			91001    100000  3
11251204 		>;
11261205 		rockchip,pvtm-ch = <0 5>;
11271206 
1207
+		/* RK3568 && RK3568M npu OPPs */
11281208 		opp-200000000 {
1209
+			opp-supported-hw = <0xfb 0xffff>;
11291210 			opp-hz = /bits/ 64 <200000000>;
11301211 			opp-microvolt = <850000 850000 1000000>;
1131
-			opp-microvolt-L0 = <850000 850000 1000000>;
1132
-			opp-microvolt-L1 = <825000 825000 1000000>;
1133
-			opp-microvolt-L2 = <825000 825000 1000000>;
11341212 		};
11351213 		opp-300000000 {
1214
+			opp-supported-hw = <0xfb 0xffff>;
11361215 			opp-hz = /bits/ 64 <297000000>;
11371216 			opp-microvolt = <850000 850000 1000000>;
1138
-			opp-microvolt-L0 = <850000 850000 1000000>;
1139
-			opp-microvolt-L1 = <825000 825000 1000000>;
1140
-			opp-microvolt-L2 = <825000 825000 1000000>;
11411217 		};
11421218 		opp-400000000 {
1219
+			opp-supported-hw = <0xfb 0xffff>;
11431220 			opp-hz = /bits/ 64 <400000000>;
11441221 			opp-microvolt = <850000 850000 1000000>;
1145
-			opp-microvolt-L0 = <850000 850000 1000000>;
1146
-			opp-microvolt-L1 = <825000 825000 1000000>;
1147
-			opp-microvolt-L2 = <825000 825000 1000000>;
11481222 		};
11491223 		opp-600000000 {
1224
+			opp-supported-hw = <0xfb 0xffff>;
11501225 			opp-hz = /bits/ 64 <600000000>;
1151
-			opp-microvolt = <875000 875000 1000000>;
1152
-			opp-microvolt-L0 = <875000 875000 1000000>;
1153
-			opp-microvolt-L1 = <825000 825000 1000000>;
1154
-			opp-microvolt-L2 = <825000 825000 1000000>;
1226
+			opp-microvolt = <850000 850000 1000000>;
11551227 		};
11561228 		opp-700000000 {
1229
+			opp-supported-hw = <0xfb 0xffff>;
11571230 			opp-hz = /bits/ 64 <700000000>;
1158
-			opp-microvolt = <900000 900000 1000000>;
1159
-			opp-microvolt-L0 = <900000 900000 1000000>;
1231
+			opp-microvolt = <875000 875000 1000000>;
1232
+			opp-microvolt-L0 = <875000 875000 1000000>;
11601233 			opp-microvolt-L1 = <850000 850000 1000000>;
11611234 			opp-microvolt-L2 = <850000 850000 1000000>;
1235
+			opp-microvolt-L3 = <850000 850000 1000000>;
11621236 		};
11631237 		opp-800000000 {
1238
+			opp-supported-hw = <0xfb 0xffff>;
11641239 			opp-hz = /bits/ 64 <800000000>;
11651240 			opp-microvolt = <925000 925000 1000000>;
11661241 			opp-microvolt-L0 = <925000 925000 1000000>;
1167
-			opp-microvolt-L1 = <875000 875000 1000000>;
1242
+			opp-microvolt-L1 = <900000 900000 1000000>;
11681243 			opp-microvolt-L2 = <875000 875000 1000000>;
1244
+			opp-microvolt-L3 = <875000 875000 1000000>;
11691245 		};
11701246 		opp-900000000 {
1247
+			opp-supported-hw = <0xf9 0xffff>;
11711248 			opp-hz = /bits/ 64 <900000000>;
11721249 			opp-microvolt = <975000 975000 1000000>;
11731250 			opp-microvolt-L0 = <975000 975000 1000000>;
1174
-			opp-microvolt-L1 = <925000 925000 1000000>;
1175
-			opp-microvolt-L2 = <900000 900000 1000000>;
1251
+			opp-microvolt-L1 = <950000 950000 1000000>;
1252
+			opp-microvolt-L2 = <925000 925000 1000000>;
1253
+			opp-microvolt-L3 = <900000 900000 1000000>;
11761254 		};
11771255 		opp-1000000000 {
1256
+			opp-supported-hw = <0xf9 0xffff>;
11781257 			opp-hz = /bits/ 64 <1000000000>;
11791258 			opp-microvolt = <1000000 1000000 1000000>;
11801259 			opp-microvolt-L0 = <1000000 1000000 1000000>;
1181
-			opp-microvolt-L1 = <950000 950000 1000000>;
1182
-			opp-microvolt-L2 = <925000 925000 1000000>;
1260
+			opp-microvolt-L1 = <975000 975000 1000000>;
1261
+			opp-microvolt-L2 = <950000 950000 1000000>;
1262
+			opp-microvolt-L3 = <925000 925000 1000000>;
11831263 			status = "disabled";
1264
+		};
1265
+
1266
+		/* RK3568J npu OPPs */
1267
+		opp-j-600000000 {
1268
+			opp-supported-hw = <0x04 0xffff>;
1269
+			opp-hz = /bits/ 64 <600000000>;
1270
+			opp-microvolt = <900000 900000 1000000>;
1271
+		};
1272
+
1273
+		/* RK3568M npu OPPs */
1274
+		opp-m-900000000 {
1275
+			opp-supported-hw = <0x02 0xffff>;
1276
+			opp-hz = /bits/ 64 <900000000>;
1277
+			opp-microvolt = <925000 925000 1000000>;
11841278 		};
11851279 	};
11861280 
....@@ -1210,8 +1304,8 @@
12101304 			opp-hz = /bits/ 64 <700000000>;
12111305 			opp-microvolt = <900000>;
12121306 			opp-microvolt-L0 = <900000>;
1213
-			opp-microvolt-L1 = <850000>;
1214
-			opp-microvolt-L2 = <850000>;
1307
+			opp-microvolt-L1 = <875000>;
1308
+			opp-microvolt-L2 = <875000>;
12151309 		};
12161310 		opp-900000000 {
12171311 			opp-hz = /bits/ 64 <900000000>;
....@@ -1272,57 +1366,84 @@
12721366 		compatible = "operating-points-v2";
12731367 
12741368 		mbist-vmin = <825000 900000 950000>;
1275
-		nvmem-cells = <&gpu_leakage>, <&core_pvtm>, <&mbist_vmin>;
1276
-		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
1369
+		nvmem-cells = <&gpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&gpu_opp_info>,
1370
+			      <&specification_serial_number>, <&remark_spec_serial_number>;
1371
+		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info",
1372
+				   "specification_serial_number", "remark_spec_serial_number";
1373
+		rockchip,supported-hw;
1374
+		rockchip,max-volt = <1000000>;
1375
+		rockchip,temp-hysteresis = <5000>;
1376
+		rockchip,low-temp = <0>;
1377
+		rockchip,low-temp-adjust-volt = <
1378
+			/* MHz    MHz    uV */
1379
+			   0      800    50000
1380
+		>;
12771381 		rockchip,pvtm-voltage-sel = <
12781382 			0        84000   0
1279
-			84001    91000   1
1280
-			91001    100000  2
1383
+			84001    87000   1
1384
+			87001    91000   2
1385
+			91001    100000  3
12811386 		>;
12821387 		rockchip,pvtm-ch = <0 5>;
12831388 
1389
+		/* RK3568 && RK3568M gpu OPPs */
12841390 		opp-200000000 {
1391
+			opp-supported-hw = <0xfb 0xffff>;
12851392 			opp-hz = /bits/ 64 <200000000>;
1286
-			opp-microvolt = <850000>;
1287
-			opp-microvolt-L0 = <850000>;
1288
-			opp-microvolt-L1 = <825000>;
1289
-			opp-microvolt-L2 = <825000>;
1393
+			opp-microvolt = <850000 850000 1000000>;
12901394 		};
12911395 		opp-300000000 {
1396
+			opp-supported-hw = <0xfb 0xffff>;
12921397 			opp-hz = /bits/ 64 <300000000>;
1293
-			opp-microvolt = <850000>;
1294
-			opp-microvolt-L0 = <850000>;
1295
-			opp-microvolt-L1 = <825000>;
1296
-			opp-microvolt-L2 = <825000>;
1398
+			opp-microvolt = <850000 850000 1000000>;
12971399 		};
12981400 		opp-400000000 {
1401
+			opp-supported-hw = <0xfb 0xffff>;
12991402 			opp-hz = /bits/ 64 <400000000>;
1300
-			opp-microvolt = <850000>;
1301
-			opp-microvolt-L0 = <850000>;
1302
-			opp-microvolt-L1 = <825000>;
1303
-			opp-microvolt-L2 = <825000>;
1403
+			opp-microvolt = <850000 850000 1000000>;
13041404 		};
13051405 		opp-600000000 {
1406
+			opp-supported-hw = <0xfb 0xffff>;
13061407 			opp-hz = /bits/ 64 <600000000>;
1307
-			opp-microvolt = <875000>;
1308
-			opp-microvolt-L0 = <875000>;
1309
-			opp-microvolt-L1 = <825000>;
1310
-			opp-microvolt-L2 = <825000>;
1408
+			opp-microvolt = <900000 900000 1000000>;
1409
+			opp-microvolt-L0 = <900000 900000 1000000>;
1410
+			opp-microvolt-L1 = <875000 875000 1000000>;
1411
+			opp-microvolt-L2 = <850000 850000 1000000>;
1412
+			opp-microvolt-L3 = <850000 850000 1000000>;
13111413 		};
13121414 		opp-700000000 {
1415
+			opp-supported-hw = <0xfb 0xffff>;
13131416 			opp-hz = /bits/ 64 <700000000>;
1314
-			opp-microvolt = <950000>;
1315
-			opp-microvolt-L0 = <950000>;
1316
-			opp-microvolt-L1 = <900000>;
1317
-			opp-microvolt-L2 = <850000>;
1417
+			opp-microvolt = <950000 950000 1000000>;
1418
+			opp-microvolt-L0 = <950000 950000 1000000>;
1419
+			opp-microvolt-L1 = <925000 925000 1000000>;
1420
+			opp-microvolt-L2 = <900000 900000 1000000>;
1421
+			opp-microvolt-L3 = <875000 875000 1000000>;
13181422 		};
13191423 		opp-800000000 {
1424
+			opp-supported-hw = <0xf9 0xffff>;
13201425 			opp-hz = /bits/ 64 <800000000>;
1321
-			opp-microvolt = <1000000>;
1322
-			opp-microvolt-L0 = <1000000>;
1323
-			opp-microvolt-L1 = <950000>;
1324
-			opp-microvolt-L2 = <900000>;
1426
+			opp-microvolt = <1000000 1000000 1000000>;
1427
+			opp-microvolt-L0 = <1000000 1000000 1000000>;
1428
+			opp-microvolt-L1 = <975000 975000 1000000>;
1429
+			opp-microvolt-L2 = <950000 950000 1000000>;
1430
+			opp-microvolt-L3 = <925000 925000 1000000>;
13251431 		};
1432
+
1433
+		/* RK3568J gpu OPPs */
1434
+		opp-j-600000000 {
1435
+			opp-supported-hw = <0x04 0xffff>;
1436
+			opp-hz = /bits/ 64 <600000000>;
1437
+			opp-microvolt = <900000 900000 1000000>;
1438
+		};
1439
+
1440
+		/* RK3568M gpu OPPs */
1441
+		opp-m-800000000 {
1442
+			opp-supported-hw = <0x02 0xffff>;
1443
+			opp-hz = /bits/ 64 <800000000>;
1444
+			opp-microvolt = <950000 950000 1000000>;
1445
+		};
1446
+
13261447 	};
13271448 
13281449 	pvtm@fde80000 {
....@@ -1545,8 +1666,8 @@
15451666 			opp-hz = /bits/ 64 <297000000>;
15461667 			opp-microvolt = <900000>;
15471668 			opp-microvolt-L0 = <900000>;
1548
-			opp-microvolt-L1 = <850000>;
1549
-			opp-microvolt-L2 = <850000>;
1669
+			opp-microvolt-L1 = <875000>;
1670
+			opp-microvolt-L2 = <875000>;
15501671 		};
15511672 		opp-400000000 {
15521673 			opp-hz = /bits/ 64 <400000000>;
....@@ -1630,7 +1751,7 @@
16301751 			opp-hz = /bits/ 64 <297000000>;
16311752 			opp-microvolt = <900000>;
16321753 			opp-microvolt-L0 = <900000>;
1633
-			opp-microvolt-L1 = <850000>;
1754
+			opp-microvolt-L1 = <875000>;
16341755 		};
16351756 		opp-400000000 {
16361757 			opp-hz = /bits/ 64 <400000000>;
....@@ -1650,8 +1771,8 @@
16501771 		status = "disabled";
16511772 	};
16521773 
1653
-	mipi_csi2: mipi-csi2@fdfb0000 {
1654
-		compatible = "rockchip,rk3568-mipi-csi2";
1774
+	mipi_csi2_hw: mipi-csi2-hw@fdfb0000 {
1775
+		compatible = "rockchip,rk3568-mipi-csi2-hw";
16551776 		reg = <0x0 0xfdfb0000 0x0 0x10000>;
16561777 		reg-names = "csihost_regs";
16571778 		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
....@@ -1740,7 +1861,7 @@
17401861 		rockchip,grf = <&grf>;
17411862 		power-domains = <&power RK3568_PD_VI>;
17421863 		iommus = <&rkisp_mmu>;
1743
-		rockchip,iq-feature = /bits/ 64 <0x3FBFFFE67FF>;
1864
+		rockchip,iq-feature = /bits/ 64 <0x1BFBFFFE67FF>;
17441865 		status = "disabled";
17451866 	};
17461867 
....@@ -1769,6 +1890,13 @@
17691890 		status = "disabled";
17701891 	};
17711892 
1893
+	gmac_uio1: uio@fe010000 {
1894
+		compatible = "rockchip,uio-gmac";
1895
+		reg = <0x0 0xfe010000 0x0 0x10000>;
1896
+		rockchip,ethernet = <&gmac1>;
1897
+		status = "disabled";
1898
+	};
1899
+
17721900 	gmac1: ethernet@fe010000 {
17731901 		compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
17741902 		reg = <0x0 0xfe010000 0x0 0x10000>;
....@@ -1780,12 +1908,12 @@
17801908 			 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
17811909 			 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
17821910 			 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>,
1783
-			 <&cru PCLK_XPCS>;
1911
+			 <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>;
17841912 		clock-names = "stmmaceth", "mac_clk_rx",
17851913 			      "mac_clk_tx", "clk_mac_refout",
17861914 			      "aclk_mac", "pclk_mac",
17871915 			      "clk_mac_speed", "ptp_ref",
1788
-			      "pclk_xpcs";
1916
+			      "pclk_xpcs", "clk_xpcs_eee";
17891917 		resets = <&cru SRST_A_GMAC1>;
17901918 		reset-names = "stmmaceth";
17911919 
....@@ -1891,6 +2019,11 @@
18912019 					reg = <4>;
18922020 					remote-endpoint = <&lvds_in_vp1>;
18932021 				};
2022
+
2023
+				vp1_out_lvds1: endpoint@5 {
2024
+					reg = <5>;
2025
+					remote-endpoint = <&lvds1_in_vp1>;
2026
+				};
18942027 			};
18952028 
18962029 			vp2: port@2 {
....@@ -1908,6 +2041,11 @@
19082041 					reg = <1>;
19092042 					remote-endpoint = <&rgb_in_vp2>;
19102043 				};
2044
+
2045
+				vp2_out_lvds1: endpoint@2 {
2046
+					reg = <2>;
2047
+					remote-endpoint = <&lvds1_in_vp2>;
2048
+				};
19112049 			};
19122050 		};
19132051 	};
....@@ -1920,6 +2058,7 @@
19202058 		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
19212059 		clock-names = "aclk", "iface";
19222060 		#iommu-cells = <0>;
2061
+		rockchip,disable-device-link-resume;
19232062 		status = "disabled";
19242063 	};
19252064 
....@@ -1927,12 +2066,12 @@
19272066 		compatible = "rockchip,rk3568-mipi-dsi";
19282067 		reg = <0x0 0xfe060000 0x0 0x10000>;
19292068 		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1930
-		clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>, <&video_phy0>;
1931
-		clock-names = "pclk", "hclk", "hs_clk";
2069
+		clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>;
2070
+		clock-names = "pclk", "hclk";
19322071 		resets = <&cru SRST_P_DSITX_0>;
19332072 		reset-names = "apb";
19342073 		phys = <&video_phy0>;
1935
-		phy-names = "mipi_dphy";
2074
+		phy-names = "dphy";
19362075 		power-domains = <&power RK3568_PD_VO>;
19372076 		rockchip,grf = <&grf>;
19382077 		#address-cells = <1>;
....@@ -1967,12 +2106,12 @@
19672106 		compatible = "rockchip,rk3568-mipi-dsi";
19682107 		reg = <0x0 0xfe070000 0x0 0x10000>;
19692108 		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
1970
-		clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>, <&video_phy1>;
1971
-		clock-names = "pclk", "hclk", "hs_clk";
2109
+		clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>;
2110
+		clock-names = "pclk", "hclk";
19722111 		resets = <&cru SRST_P_DSITX_1>;
19732112 		reset-names = "apb";
19742113 		phys = <&video_phy1>;
1975
-		phy-names = "mipi_dphy";
2114
+		phy-names = "dphy";
19762115 		power-domains = <&power RK3568_PD_VO>;
19772116 		rockchip,grf = <&grf>;
19782117 		#address-cells = <1>;
....@@ -2025,7 +2164,7 @@
20252164 			#address-cells = <1>;
20262165 			#size-cells = <0>;
20272166 
2028
-			hdmi_in: port {
2167
+			port@0 {
20292168 				reg = <0>;
20302169 				#address-cells = <1>;
20312170 				#size-cells = <0>;
....@@ -2035,6 +2174,7 @@
20352174 					remote-endpoint = <&vp0_out_hdmi>;
20362175 					status = "disabled";
20372176 				};
2177
+
20382178 				hdmi_in_vp1: endpoint@1 {
20392179 					reg = <1>;
20402180 					remote-endpoint = <&vp1_out_hdmi>;
....@@ -2325,8 +2465,12 @@
23252465 		compatible = "operating-points-v2";
23262466 
23272467 		mbist-vmin = <825000 900000 950000>;
2328
-		nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>;
2329
-		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
2468
+		nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>, <&dmc_opp_info>,
2469
+			      <&specification_serial_number>, <&remark_spec_serial_number>;
2470
+		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info",
2471
+				   "specification_serial_number", "remark_spec_serial_number";
2472
+		rockchip,supported-hw;
2473
+		rockchip,max-volt = <1000000>;
23302474 		rockchip,temp-hysteresis = <5000>;
23312475 		rockchip,low-temp = <0>;
23322476 		rockchip,low-temp-adjust-volt = <
....@@ -2343,17 +2487,21 @@
23432487 		>;
23442488 		rockchip,pvtm-ch = <0 5>;
23452489 
2490
+		/* RK3568 dmc OPPs */
23462491 		opp-1560000000 {
2492
+			opp-supported-hw = <0xf9 0xffff>;
23472493 			opp-hz = /bits/ 64 <1560000000>;
2348
-			opp-microvolt = <900000>;
2349
-			opp-microvolt-L0 = <900000>;
2350
-			opp-microvolt-L1 = <850000>;
2494
+			opp-microvolt = <900000 900000 1000000>;
2495
+			opp-microvolt-L0 = <900000 900000 1000000>;
2496
+			opp-microvolt-L1 = <875000 875000 1000000>;
23512497 		};
2352
-	};
23532498 
2354
-	dmcdbg: dmcdbg {
2355
-		compatible = "rockchip,rk3568-dmcdbg";
2356
-		status = "disabled";
2499
+		/* RK3568J/M dmc OPPs */
2500
+		opp-j-m-1560000000 {
2501
+			opp-supported-hw = <0x06 0xffff>;
2502
+			opp-hz = /bits/ 64 <1560000000>;
2503
+			opp-microvolt = <875000 875000 1000000>;
2504
+		};
23572505 	};
23582506 
23592507 	pcie2x1: pcie@fe260000 {
....@@ -2398,7 +2546,7 @@
23982546 		reg-names = "pcie-dbi", "pcie-apb";
23992547 		resets = <&cru SRST_PCIE20_POWERUP>;
24002548 		reset-names = "pipe";
2401
-		status = "okay";
2549
+		status = "disabled";
24022550 
24032551 		pcie2x1_intc: legacy-interrupt-controller {
24042552 			interrupt-controller;
....@@ -2517,6 +2665,13 @@
25172665 		};
25182666 	};
25192667 
2668
+	gmac_uio0: uio@fe2a0000 {
2669
+		compatible = "rockchip,uio-gmac";
2670
+		reg = <0x0 0xfe2a0000 0x0 0x10000>;
2671
+		rockchip,ethernet = <&gmac0>;
2672
+		status = "disabled";
2673
+	};
2674
+
25202675 	gmac0: ethernet@fe2a0000 {
25212676 		compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
25222677 		reg = <0x0 0xfe2a0000 0x0 0x10000>;
....@@ -2528,12 +2683,12 @@
25282683 			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
25292684 			 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
25302685 			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
2531
-			 <&cru PCLK_XPCS>;
2686
+			 <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>;
25322687 		clock-names = "stmmaceth", "mac_clk_rx",
25332688 			      "mac_clk_tx", "clk_mac_refout",
25342689 			      "aclk_mac", "pclk_mac",
25352690 			      "clk_mac_speed", "ptp_ref",
2536
-			      "pclk_xpcs";
2691
+			      "pclk_xpcs", "clk_xpcs_eee";
25372692 		resets = <&cru SRST_A_GMAC0>;
25382693 		reset-names = "stmmaceth";
25392694 
....@@ -2598,7 +2753,7 @@
25982753 		status = "disabled";
25992754 	};
26002755 
2601
-	sfc: sfc@fe300000 {
2756
+	sfc: spi@fe300000 {
26022757 		compatible = "rockchip,sfc";
26032758 		reg = <0x0 0xfe300000 0x0 0x4000>;
26042759 		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
....@@ -2606,11 +2761,13 @@
26062761 		clock-names = "clk_sfc", "hclk_sfc";
26072762 		assigned-clocks = <&cru SCLK_SFC>;
26082763 		assigned-clock-rates = <100000000>;
2764
+		#address-cells = <1>;
2765
+		#size-cells = <0>;
26092766 		status = "disabled";
26102767 	};
26112768 
26122769 	sdhci: sdhci@fe310000 {
2613
-		compatible = "rockchip,dwcmshc-sdhci", "snps,dwcmshc-sdhci";
2770
+		compatible = "rockchip,rk3568-dwcmshc", "rockchip,dwcmshc-sdhci";
26142771 		reg = <0x0 0xfe310000 0x0 0x10000>;
26152772 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
26162773 		assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>,
....@@ -2620,6 +2777,10 @@
26202777 			 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
26212778 			 <&cru TCLK_EMMC>;
26222779 		clock-names = "core", "bus", "axi", "block", "timer";
2780
+		resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
2781
+			 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
2782
+			 <&cru SRST_T_EMMC>;
2783
+		reset-names = "core", "bus", "axi", "block", "timer";
26232784 		status = "disabled";
26242785 	};
26252786 
....@@ -2672,6 +2833,10 @@
26722833 		cpu_code: cpu-code@2 {
26732834 			reg = <0x02 0x2>;
26742835 		};
2836
+		specification_serial_number: specification-serial-number@7 {
2837
+			reg = <0x07 0x1>;
2838
+			bits = <0 5>;
2839
+		};
26752840 		otp_cpu_version: cpu-version@8 {
26762841 			reg = <0x08 0x1>;
26772842 			bits = <3 3>;
....@@ -2718,6 +2883,22 @@
27182883 		};
27192884 		tsadc_trim_base: tsadc-trim-base@32 {
27202885 			reg = <0x32 0x1>;
2886
+		};
2887
+		cpu_opp_info: cpu-opp-info@36 {
2888
+			reg = <0x36 0x6>;
2889
+		};
2890
+		gpu_opp_info: gpu-opp-info@3c {
2891
+			reg = <0x3c 0x6>;
2892
+		};
2893
+		npu_opp_info: npu-opp-info@42 {
2894
+			reg = <0x42 0x6>;
2895
+		};
2896
+		dmc_opp_info: dmc-opp-info@48 {
2897
+			reg = <0x48 0x6>;
2898
+		};
2899
+		remark_spec_serial_number: remark-spec-serial-number@56 {
2900
+			reg = <0x56 0x1>;
2901
+			bits = <0 5>;
27212902 		};
27222903 	};
27232904 
....@@ -2810,7 +2991,7 @@
28102991 	};
28112992 
28122993 	pdm: pdm@fe440000 {
2813
-		compatible = "rockchip,rk3568-pdm";
2994
+		compatible = "rockchip,rk3568-pdm", "rockchip,pdm";
28142995 		reg = <0x0 0xfe440000 0x0 0x1000>;
28152996 		clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
28162997 		clock-names = "pdm_clk", "pdm_hclk";
....@@ -3050,6 +3231,7 @@
30503231 		pinctrl-names = "default", "high_speed";
30513232 		pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
30523233 		pinctrl-1 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins_hs>;
3234
+		num-cs = <2>;
30533235 		status = "disabled";
30543236 	};
30553237 
....@@ -3066,6 +3248,7 @@
30663248 		pinctrl-names = "default", "high_speed";
30673249 		pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
30683250 		pinctrl-1 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins_hs>;
3251
+		num-cs = <2>;
30693252 		status = "disabled";
30703253 	};
30713254 
....@@ -3082,6 +3265,7 @@
30823265 		pinctrl-names = "default", "high_speed";
30833266 		pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
30843267 		pinctrl-1 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins_hs>;
3268
+		num-cs = <2>;
30853269 		status = "disabled";
30863270 	};
30873271 
....@@ -3098,6 +3282,7 @@
30983282 		pinctrl-names = "default", "high_speed";
30993283 		pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
31003284 		pinctrl-1 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins_hs>;
3285
+		num-cs = <2>;
31013286 		status = "disabled";
31023287 	};
31033288 
....@@ -3112,7 +3297,7 @@
31123297 		dmas = <&dmac0 2>, <&dmac0 3>;
31133298 		pinctrl-names = "default";
31143299 		pinctrl-0 = <&uart1m0_xfer>;
3115
-		status = "okay";
3300
+		status = "disabled";
31163301 	};
31173302 
31183303 	uart2: serial@fe660000 {
....@@ -3476,31 +3661,33 @@
34763661 		status = "disabled";
34773662 	};
34783663 
3479
-	video_phy0: video-phy@fe850000 {
3480
-		compatible = "rockchip,rk3568-video-phy";
3664
+	video_phy0: phy@fe850000 {
3665
+		compatible = "rockchip,rk3568-dsi-dphy", "rockchip,rk3568-video-phy";
34813666 		reg = <0x0 0xfe850000  0x0 0x10000>,
34823667 		      <0x0 0xfe060000 0x0 0x10000>;
3668
+		reg-names = "phy", "host";
34833669 		clocks = <&pmucru CLK_MIPIDSIPHY0_REF>,
34843670 			 <&cru PCLK_MIPIDSIPHY0>, <&cru PCLK_DSITX_0>;
3485
-		clock-names = "ref", "pclk_phy", "pclk_host";
3671
+		clock-names = "ref", "pclk", "pclk_host";
34863672 		#clock-cells = <0>;
34873673 		resets = <&cru SRST_P_MIPIDSIPHY0>;
3488
-		reset-names = "rst";
3674
+		reset-names = "apb";
34893675 		power-domains = <&power RK3568_PD_VO>;
34903676 		#phy-cells = <0>;
34913677 		status = "disabled";
34923678 	};
34933679 
3494
-	video_phy1: video-phy@fe860000 {
3495
-		compatible = "rockchip,rk3568-video-phy";
3680
+	video_phy1: phy@fe860000 {
3681
+		compatible = "rockchip,rk3568-dsi-dphy", "rockchip,rk3568-video-phy";
34963682 		reg = <0x0 0xfe860000  0x0 0x10000>,
34973683 		      <0x0 0xfe070000 0x0 0x10000>;
3684
+		reg-names = "phy", "host";
34983685 		clocks = <&pmucru CLK_MIPIDSIPHY1_REF>,
34993686 			 <&cru PCLK_MIPIDSIPHY1>, <&cru PCLK_DSITX_1>;
3500
-		clock-names = "ref", "pclk_phy", "pclk_host";
3687
+		clock-names = "ref", "pclk", "pclk_host";
35013688 		#clock-cells = <0>;
35023689 		resets = <&cru SRST_P_MIPIDSIPHY1>;
3503
-		reset-names = "rst";
3690
+		reset-names = "apb";
35043691 		power-domains = <&power RK3568_PD_VO>;
35053692 		#phy-cells = <0>;
35063693 		status = "disabled";
....@@ -3610,7 +3797,7 @@
36103797 		#size-cells = <2>;
36113798 		ranges;
36123799 
3613
-		gpio0: gpio@fdd60000 {
3800
+		gpio0: gpio0@fdd60000 {
36143801 			compatible = "rockchip,gpio-bank";
36153802 			reg = <0x0 0xfdd60000 0x0 0x100>;
36163803 			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
....@@ -3618,12 +3805,11 @@
36183805 
36193806 			gpio-controller;
36203807 			#gpio-cells = <2>;
3621
-			gpio-ranges = <&pinctrl 0 0 32>;
36223808 			interrupt-controller;
36233809 			#interrupt-cells = <2>;
36243810 		};
36253811 
3626
-		gpio1: gpio@fe740000 {
3812
+		gpio1: gpio1@fe740000 {
36273813 			compatible = "rockchip,gpio-bank";
36283814 			reg = <0x0 0xfe740000 0x0 0x100>;
36293815 			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
....@@ -3631,12 +3817,11 @@
36313817 
36323818 			gpio-controller;
36333819 			#gpio-cells = <2>;
3634
-			gpio-ranges = <&pinctrl 0 32 32>;
36353820 			interrupt-controller;
36363821 			#interrupt-cells = <2>;
36373822 		};
36383823 
3639
-		gpio2: gpio@fe750000 {
3824
+		gpio2: gpio2@fe750000 {
36403825 			compatible = "rockchip,gpio-bank";
36413826 			reg = <0x0 0xfe750000 0x0 0x100>;
36423827 			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
....@@ -3644,12 +3829,11 @@
36443829 
36453830 			gpio-controller;
36463831 			#gpio-cells = <2>;
3647
-			gpio-ranges = <&pinctrl 0 64 32>;
36483832 			interrupt-controller;
36493833 			#interrupt-cells = <2>;
36503834 		};
36513835 
3652
-		gpio3: gpio@fe760000 {
3836
+		gpio3: gpio3@fe760000 {
36533837 			compatible = "rockchip,gpio-bank";
36543838 			reg = <0x0 0xfe760000 0x0 0x100>;
36553839 			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
....@@ -3657,12 +3841,11 @@
36573841 
36583842 			gpio-controller;
36593843 			#gpio-cells = <2>;
3660
-			gpio-ranges = <&pinctrl 0 96 32>;
36613844 			interrupt-controller;
36623845 			#interrupt-cells = <2>;
36633846 		};
36643847 
3665
-		gpio4: gpio@fe770000 {
3848
+		gpio4: gpio4@fe770000 {
36663849 			compatible = "rockchip,gpio-bank";
36673850 			reg = <0x0 0xfe770000 0x0 0x100>;
36683851 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
....@@ -3670,7 +3853,6 @@
36703853 
36713854 			gpio-controller;
36723855 			#gpio-cells = <2>;
3673
-			gpio-ranges = <&pinctrl 0 128 32>;
36743856 			interrupt-controller;
36753857 			#interrupt-cells = <2>;
36763858 		};