forked from ~ljy/RK356X_SDK_RELEASE

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2023-12-11 1f93a7dfd1f8d5ff7a5c53246c7534fe2332d6f4 
 kernel/arch/arm64/boot/dts/rockchip/rk3308-evb-ext-v10.dtsi
....@@ -45,143 +45,171 @@
4545 		default-brightness-level = <200>;
4646 	};
4747 
48
-	panel: panel {
49
-		compatible = "simple-panel";
50
-		bus-format = <MEDIA_BUS_FMT_RGB666_1X18>;
51
-		backlight = <&backlight>;
52
-		enable-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
53
-		enable-delay-ms = <20>;
54
-		reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
55
-		reset-delay-ms = <10>;
56
-		prepare-delay-ms = <20>;
57
-		unprepare-delay-ms = <20>;
58
-		disable-delay-ms = <20>;
59
-		/* spi-sdo-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; */
60
-		spi-sdi-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>;
61
-		spi-scl-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
62
-		spi-cs-gpios = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>;
63
-		width-mm = <217>;
64
-		height-mm = <136>;
65
-		status = "okay";
48
+	spi_gpio: spi-gpio {
49
+		compatible = "spi-gpio";
50
+		#address-cells = <0x1>;
51
+		#size-cells = <0x0>;
6652 		pinctrl-names = "default";
67
-		pinctrl-0 = <&spi_init_cmd>;
68
-		rockchip,cmd-type = "spi";
53
+		pinctrl-0 = <&spi_pins>;
54
+		spi-delay-us = <10>;
55
+		status = "okay";
6956 
70
-		/* type:0 is cmd, 1 is data */
71
-		panel-init-sequence = [
72
-			/* type delay num val1 val2 val3 */
73
-			  00   00  01  e0
74
-			  01   00  01  00
75
-			  01   00  01  07
76
-			  01   00  01  0f
77
-			  01   00  01  0d
78
-			  01   00  01  1b
79
-			  01   00  01  0a
80
-			  01   00  01  3c
81
-			  01   00  01  78
82
-			  01   00  01  4a
83
-			  01   00  01  07
84
-			  01   00  01  0e
85
-			  01   00  01  09
86
-			  01   00  01  1b
87
-			  01   00  01  1e
88
-			  01   00  01  0f
89
-			  00   00  01  e1
90
-			  01   00  01  00
91
-			  01   00  01  22
92
-			  01   00  01  24
93
-			  01   00  01  06
94
-			  01   00  01  12
95
-			  01   00  01  07
96
-			  01   00  01  36
97
-			  01   00  01  47
98
-			  01   00  01  47
99
-			  01   00  01  06
100
-			  01   00  01  0a
101
-			  01   00  01  07
102
-			  01   00  01  30
103
-			  01   00  01  37
104
-			  01   00  01  0f
57
+		sck-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
58
+		miso-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>;
59
+		mosi-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>;
60
+		cs-gpios = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>;
61
+		num-chipselects = <1>;
10562 
106
-			  00   00  01  c0
107
-			  01   00  01  10
108
-			  01   00  01  10
63
+		/*
64
+		 * 320x480 RGB/MCU screen K350C4516T
65
+		 */
66
+		panel: panel {
67
+			compatible = "simple-panel-spi";
68
+			reg = <0>;
69
+			bus-format = <MEDIA_BUS_FMT_RGB666_1X18>;
70
+			backlight = <&backlight>;
71
+			enable-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
72
+			enable-delay-ms = <20>;
73
+			reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
74
+			reset-delay-ms = <10>;
75
+			prepare-delay-ms = <20>;
76
+			unprepare-delay-ms = <20>;
77
+			disable-delay-ms = <20>;
78
+			init-delay-ms = <10>;
79
+			width-mm = <217>;
80
+			height-mm = <136>;
81
+			rockchip,cmd-type = "spi";
82
+			status = "okay";
10983 
110
-			  00   00  01  c1
111
-			  01   00  01  41
84
+			// type:0 is cmd, 1 is data
85
+			panel-init-sequence = [
86
+				/* type delay num val1 val2 val3 */
87
+				00   00  01  e0
88
+				01   00  01  00
89
+				01   00  01  07
90
+				01   00  01  0f
91
+				01   00  01  0d
92
+				01   00  01  1b
93
+				01   00  01  0a
94
+				01   00  01  3c
95
+				01   00  01  78
96
+				01   00  01  4a
97
+				01   00  01  07
98
+				01   00  01  0e
99
+				01   00  01  09
100
+				01   00  01  1b
101
+				01   00  01  1e
102
+				01   00  01  0f
103
+				00   00  01  e1
104
+				01   00  01  00
105
+				01   00  01  22
106
+				01   00  01  24
107
+				01   00  01  06
108
+				01   00  01  12
109
+				01   00  01  07
110
+				01   00  01  36
111
+				01   00  01  47
112
+				01   00  01  47
113
+				01   00  01  06
114
+				01   00  01  0a
115
+				01   00  01  07
116
+				01   00  01  30
117
+				01   00  01  37
118
+				01   00  01  0f
112119 
113
-			  00   00  01  c5
114
-			  01   00  01  00
115
-			  01   00  01  22
116
-			  01   00  01  80
120
+				00   00  01  c0
121
+				01   00  01  10
122
+				01   00  01  10
117123 
118
-			  00   00  01  36
119
-			  01   00  01  48
124
+				00   00  01  c1
125
+				01   00  01  41
120126 
121
-			  00   00  01  3a  /* interface mode control */
122
-			  01   00  01  66
127
+				00   00  01  c5
128
+				01   00  01  00
129
+				01   00  01  22
130
+				01   00  01  80
123131 
124
-			  00   00  01  b0  /* interface mode control */
125
-			  01   00  01  00
132
+				00   00  01  36
133
+				01   00  01  48
126134 
127
-			  00   00  01  b1  /* frame rate 70hz */
128
-			  01   00  01  b0
129
-			  01   00  01  11
130
-			  00   00  01  b4
131
-			  01   00  01  02
132
-			  00   00  01  B6  /* RGB/MCU Interface Control */
133
-			  01   00  01  32  /* 02 mcu, 32 rgb */
134
-			  01   00  01  02
135
+				00   00  01  3a
136
+				01   00  01  66 /*
137
+						 * interface pixel format:
138
+						 * 66 for RGB666(18bit)
139
+						 */
135140 
136
-			  00   00  01  b7
137
-			  01   00  01  c6
141
+				00   00  01  b0
142
+				01   00  01  00
138143 
139
-			  00   00  01  be
140
-			  01   00  01  00
141
-			  01   00  01  04
144
+				00   00  01  b1
145
+				01   00  01  a0 /*
146
+						 * frame rate control:
147
+						 * a0 (60hz) for RGB666(18bit)
148
+						 */
149
+				01   00  01  11
150
+				00   00  01  b4
151
+				01   00  01  02
152
+				00   00  01  B6
153
+				01   00  01  32 /*
154
+						 * display function control:
155
+						 * 32 for RGB
156
+						 * 02 for MCU
157
+						 */
158
+				01   00  01  02
142159 
143
-			  00   00  01  e9
144
-			  01   00  01  00
160
+				00   00  01  b7
161
+				01   00  01  c6
145162 
146
-			  00   00  01  f7
147
-			  01   00  01  a9
148
-			  01   00  01  51
149
-			  01   00  01  2c
150
-			  01   00  01  82
163
+				00   00  01  be
164
+				01   00  01  00
165
+				01   00  01  04
151166 
152
-			  00   78  01  11
153
-			  00   00  01  29
154
-		];
167
+				00   00  01  e9
168
+				01   00  01  00
155169 
156
-		panel-exit-sequence = [
157
-			/* type delay num val1 val2 val3 */
158
-			00   0a  01  28
159
-			00   78  01  10
160
-		];
170
+				00   00  01  f7
171
+				01   00  01  a9
172
+				01   00  01  51
173
+				01   00  01  2c
174
+				01   00  01  82
161175 
162
-		display-timings {
163
-			native-mode = <&kd050fwfba002_timing>;
176
+				00   78  01  11
177
+				00   00  01  29
178
+			];
164179 
165
-			kd050fwfba002_timing: timing0 {
166
-				clock-frequency = <12000000>;
167
-				hactive = <320>;
168
-				vactive = <480>;
169
-				hback-porch = <10>;
170
-				hfront-porch = <5>;
171
-				vback-porch = <10>;
172
-				vfront-porch = <5>;
173
-				hsync-len = <10>;
174
-				vsync-len = <10>;
175
-				hsync-active = <0>;
176
-				vsync-active = <0>;
177
-				de-active = <0>;
178
-				pixelclk-active = <0>;
180
+			panel-exit-sequence = [
181
+				//type delay num val1 val2 val3
182
+				00   0a  01  28
183
+				00   78  01  10
184
+			];
185
+
186
+			display-timings {
187
+				native-mode = <&kd050fwfba002_timing>;
188
+
189
+				kd050fwfba002_timing: timing0 {
190
+					/*
191
+					 * 10453500  for RGB666(18bit)
192
+					 */
193
+					clock-frequency = <10453500>;
194
+					hactive = <320>;
195
+					vactive = <480>;
196
+					hback-porch = <10>;
197
+					hfront-porch = <5>;
198
+					vback-porch = <10>;
199
+					vfront-porch = <5>;
200
+					hsync-len = <10>;
201
+					vsync-len = <10>;
202
+					hsync-active = <0>;
203
+					vsync-active = <0>;
204
+					de-active = <0>;
205
+					pixelclk-active = <1>;
206
+				};
179207 			};
180
-		};
181208 
182
-		port {
183
-			panel_in_rgb: endpoint {
184
-				remote-endpoint = <&rgb_out_panel>;
209
+			port {
210
+				panel_in_rgb: endpoint {
211
+					remote-endpoint = <&rgb_out_panel>;
212
+				};
185213 			};
186214 		};
187215 	};
....@@ -192,9 +220,11 @@
192220 };
193221 
194222 &pinctrl {
195
-	spi_panel {
196
-		spi_init_cmd: spi-init-cmd {
223
+	soft_spi {
224
+		spi_pins: spi-pins {
197225 			rockchip,pins =
226
+				/* spi sdo */
227
+				<3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>,
198228 				/* spi sdi */
199229 				<1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>,
200230 				/* spi scl */