forked from ~ljy/RK356X_SDK_RELEASE

blame | history | patch | commit | commitdiff
hc
2023-12-11 1f93a7dfd1f8d5ff7a5c53246c7534fe2332d6f4 
 kernel/arch/arm64/boot/dts/nvidia/tegra132.dtsi
....@@ -6,6 +6,7 @@
66 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
77 #include <dt-bindings/interrupt-controller/arm-gic.h>
88 #include <dt-bindings/thermal/tegra124-soctherm.h>
9
+#include <dt-bindings/soc/tegra-pmc.h>
910 
1011 / {
1112 	compatible = "nvidia,tegra132", "nvidia,tegra124";
....@@ -16,9 +17,9 @@
1617 	pcie@1003000 {
1718 		compatible = "nvidia,tegra124-pcie";
1819 		device_type = "pci";
19
-		reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
20
-		       0x0 0x01003800 0x0 0x00000800   /* AFI registers */
21
-		       0x0 0x02000000 0x0 0x10000000>; /* configuration space */
20
+		reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
21
+		      <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
22
+		      <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
2223 		reg-names = "pads", "afi", "cs";
2324 		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2425 			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
....@@ -32,11 +33,11 @@
3233 		#address-cells = <3>;
3334 		#size-cells = <2>;
3435 
35
-		ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */
36
-			  0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */
37
-			  0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
38
-			  0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
39
-			  0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
36
+		ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
37
+			 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
38
+			 <0x01000000 0 0x0        0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
39
+			 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
40
+			 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
4041 
4142 		clocks = <&tegra_car TEGRA124_CLK_PCIE>,
4243 			 <&tegra_car TEGRA124_CLK_AFI>,
....@@ -48,9 +49,6 @@
4849 			 <&tegra_car 74>;
4950 		reset-names = "pex", "afi", "pcie_x";
5051 		status = "disabled";
51
-
52
-		phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
53
-		phy-names = "pcie";
5452 
5553 		pci@1,0 {
5654 			device_type = "pci";
....@@ -82,10 +80,12 @@
8280 	};
8381 
8482 	host1x@50000000 {
85
-		compatible = "nvidia,tegra124-host1x", "simple-bus";
83
+		compatible = "nvidia,tegra132-host1x",
84
+			     "nvidia,tegra124-host1x";
8685 		reg = <0x0 0x50000000 0x0 0x00034000>;
8786 		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
8887 			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
88
+		interrupt-names = "syncpt", "host1x";
8989 		clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
9090 		clock-names = "host1x";
9191 		resets = <&tegra_car 28>;
....@@ -100,9 +100,8 @@
100100 			compatible = "nvidia,tegra124-dc";
101101 			reg = <0x0 0x54200000 0x0 0x00040000>;
102102 			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
103
-			clocks = <&tegra_car TEGRA124_CLK_DISP1>,
104
-				 <&tegra_car TEGRA124_CLK_PLL_P>;
105
-			clock-names = "dc", "parent";
103
+			clocks = <&tegra_car TEGRA124_CLK_DISP1>;
104
+			clock-names = "dc";
106105 			resets = <&tegra_car 27>;
107106 			reset-names = "dc";
108107 
....@@ -115,9 +114,8 @@
115114 			compatible = "nvidia,tegra124-dc";
116115 			reg = <0x0 0x54240000 0x0 0x00040000>;
117116 			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
118
-			clocks = <&tegra_car TEGRA124_CLK_DISP2>,
119
-				 <&tegra_car TEGRA124_CLK_PLL_P>;
120
-			clock-names = "dc", "parent";
117
+			clocks = <&tegra_car TEGRA124_CLK_DISP2>;
118
+			clock-names = "dc";
121119 			resets = <&tegra_car 26>;
122120 			reset-names = "dc";
123121 
....@@ -143,10 +141,11 @@
143141 			reg = <0x0 0x54540000 0x0 0x00040000>;
144142 			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
145143 			clocks = <&tegra_car TEGRA124_CLK_SOR0>,
144
+				 <&tegra_car TEGRA124_CLK_SOR0_OUT>,
146145 				 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
147146 				 <&tegra_car TEGRA124_CLK_PLL_DP>,
148147 				 <&tegra_car TEGRA124_CLK_CLK_M>;
149
-			clock-names = "sor", "parent", "dp", "safe";
148
+			clock-names = "sor", "out", "parent", "dp", "safe";
150149 			resets = <&tegra_car 182>;
151150 			reset-names = "sor";
152151 			status = "disabled";
....@@ -162,6 +161,11 @@
162161 			resets = <&tegra_car 181>;
163162 			reset-names = "dpaux";
164163 			status = "disabled";
164
+
165
+			i2c-bus {
166
+				#address-cells = <1>;
167
+				#size-cells = <0>;
168
+			};
165169 		};
166170 	};
167171 
....@@ -577,11 +581,12 @@
577581 		clock-names = "rtc";
578582 	};
579583 
580
-	pmc@7000e400 {
584
+	tegra_pmc: pmc@7000e400 {
581585 		compatible = "nvidia,tegra124-pmc";
582586 		reg = <0x0 0x7000e400 0x0 0x400>;
583587 		clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
584588 		clock-names = "pclk", "clk32k_in";
589
+		#clock-cells = <1>;
585590 	};
586591 
587592 	fuse@7000f800 {
....@@ -604,9 +609,11 @@
604609 		#iommu-cells = <1>;
605610 	};
606611 
607
-	emc: emc@7001b000 {
608
-		compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc";
612
+	emc: external-memory-controller@7001b000 {
613
+		compatible = "nvidia,tegra132-emc";
609614 		reg = <0x0 0x7001b000 0x0 0x1000>;
615
+		clocks = <&tegra_car TEGRA124_CLK_EMC>;
616
+		clock-names = "emc";
610617 
611618 		nvidia,memory-controller = <&mc>;
612619 	};
....@@ -625,8 +632,6 @@
625632 			 <&tegra_car 123>,
626633 			 <&tegra_car 129>;
627634 		reset-names = "sata", "sata-oob", "sata-cold";
628
-		phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
629
-		phy-names = "sata-phy";
630635 		status = "disabled";
631636 	};
632637 
....@@ -646,6 +651,41 @@
646651 		status = "disabled";
647652 	};
648653 
654
+	usb@70090000 {
655
+		compatible = "nvidia,tegra132-xusb", "nvidia,tegra124-xusb";
656
+		reg = <0x0 0x70090000 0x0 0x8000>,
657
+		      <0x0 0x70098000 0x0 0x1000>,
658
+		      <0x0 0x70099000 0x0 0x1000>;
659
+		reg-names = "hcd", "fpci", "ipfs";
660
+
661
+		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
662
+			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
663
+
664
+		clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
665
+			 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
666
+			 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
667
+			 <&tegra_car TEGRA124_CLK_XUSB_SS>,
668
+			 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
669
+			 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
670
+			 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
671
+			 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
672
+			 <&tegra_car TEGRA124_CLK_PLL_U_480M>,
673
+			 <&tegra_car TEGRA124_CLK_CLK_M>,
674
+			 <&tegra_car TEGRA124_CLK_PLL_E>;
675
+		clock-names = "xusb_host", "xusb_host_src",
676
+			      "xusb_falcon_src", "xusb_ss",
677
+			      "xusb_ss_src", "xusb_ss_div2",
678
+			      "xusb_hs_src", "xusb_fs_src",
679
+			      "pll_u_480m", "clk_m", "pll_e";
680
+		resets = <&tegra_car 89>, <&tegra_car 156>,
681
+			 <&tegra_car 143>;
682
+		reset-names = "xusb_host", "xusb_ss", "xusb_src";
683
+
684
+		nvidia,xusb-padctl = <&padctl>;
685
+
686
+		status = "disabled";
687
+	};
688
+
649689 	padctl: padctl@7009f000 {
650690 		compatible = "nvidia,tegra132-xusb-padctl",
651691 			     "nvidia,tegra124-xusb-padctl";
....@@ -653,14 +693,116 @@
653693 		resets = <&tegra_car 142>;
654694 		reset-names = "padctl";
655695 
656
-		#phy-cells = <1>;
696
+		pads {
697
+			usb2 {
698
+				status = "disabled";
657699 
658
-		phys {
659
-			pcie-0 {
700
+				lanes {
701
+					usb2-0 {
702
+						status = "disabled";
703
+						#phy-cells = <0>;
704
+					};
705
+
706
+					usb2-1 {
707
+						status = "disabled";
708
+						#phy-cells = <0>;
709
+					};
710
+
711
+					usb2-2 {
712
+						status = "disabled";
713
+						#phy-cells = <0>;
714
+					};
715
+				};
716
+			};
717
+
718
+			ulpi {
719
+				status = "disabled";
720
+
721
+				lanes {
722
+					ulpi-0 {
723
+						status = "disabled";
724
+						#phy-cells = <0>;
725
+					};
726
+				};
727
+			};
728
+
729
+			hsic {
730
+				status = "disabled";
731
+
732
+				lanes {
733
+					hsic-0 {
734
+						status = "disabled";
735
+						#phy-cells = <0>;
736
+					};
737
+
738
+					hsic-1 {
739
+						status = "disabled";
740
+						#phy-cells = <0>;
741
+					};
742
+				};
743
+			};
744
+
745
+			pcie {
746
+				status = "disabled";
747
+
748
+				lanes {
749
+					pcie-0 {
750
+						status = "disabled";
751
+						#phy-cells = <0>;
752
+					};
753
+
754
+					pcie-1 {
755
+						status = "disabled";
756
+						#phy-cells = <0>;
757
+					};
758
+
759
+					pcie-2 {
760
+						status = "disabled";
761
+						#phy-cells = <0>;
762
+					};
763
+
764
+					pcie-3 {
765
+						status = "disabled";
766
+						#phy-cells = <0>;
767
+					};
768
+
769
+					pcie-4 {
770
+						status = "disabled";
771
+						#phy-cells = <0>;
772
+					};
773
+				};
774
+			};
775
+
776
+			sata {
777
+				status = "disabled";
778
+
779
+				lanes {
780
+					sata-0 {
781
+						status = "disabled";
782
+						#phy-cells = <0>;
783
+					};
784
+				};
785
+			};
786
+		};
787
+
788
+		ports {
789
+			usb2-0 {
660790 				status = "disabled";
661791 			};
662792 
663
-			sata-0 {
793
+			usb2-1 {
794
+				status = "disabled";
795
+			};
796
+
797
+			usb2-2 {
798
+				status = "disabled";
799
+			};
800
+
801
+			hsic-0 {
802
+				status = "disabled";
803
+			};
804
+
805
+			hsic-1 {
664806 				status = "disabled";
665807 			};
666808 
....@@ -671,22 +813,10 @@
671813 			usb3-1 {
672814 				status = "disabled";
673815 			};
674
-
675
-			utmi-0 {
676
-				status = "disabled";
677
-			};
678
-
679
-			utmi-1 {
680
-				status = "disabled";
681
-			};
682
-
683
-			utmi-2 {
684
-				status = "disabled";
685
-			};
686816 		};
687817 	};
688818 
689
-	sdhci@700b0000 {
819
+	mmc@700b0000 {
690820 		compatible = "nvidia,tegra124-sdhci";
691821 		reg = <0x0 0x700b0000 0x0 0x200>;
692822 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
....@@ -697,7 +827,7 @@
697827 		status = "disabled";
698828 	};
699829 
700
-	sdhci@700b0200 {
830
+	mmc@700b0200 {
701831 		compatible = "nvidia,tegra124-sdhci";
702832 		reg = <0x0 0x700b0200 0x0 0x200>;
703833 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
....@@ -708,7 +838,7 @@
708838 		status = "disabled";
709839 	};
710840 
711
-	sdhci@700b0400 {
841
+	mmc@700b0400 {
712842 		compatible = "nvidia,tegra124-sdhci";
713843 		reg = <0x0 0x700b0400 0x0 0x200>;
714844 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
....@@ -719,7 +849,7 @@
719849 		status = "disabled";
720850 	};
721851 
722
-	sdhci@700b0600 {
852
+	mmc@700b0600 {
723853 		compatible = "nvidia,tegra124-sdhci";
724854 		reg = <0x0 0x700b0600 0x0 0x200>;
725855 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
....@@ -732,12 +862,12 @@
732862 
733863 	soctherm: thermal-sensor@700e2000 {
734864 		compatible = "nvidia,tegra132-soctherm";
735
-		reg = <0x0 0x700e2000 0x0 0x600 /* 0: SOC_THERM reg_base */
736
-			0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */
865
+		reg = <0x0 0x700e2000 0x0 0x600>, /* 0: SOC_THERM reg_base */
866
+		      <0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */
737867 		reg-names = "soctherm-reg", "ccroc-reg";
738868 		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
739869 		clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
740
-			<&tegra_car TEGRA124_CLK_SOC_THERM>;
870
+		         <&tegra_car TEGRA124_CLK_SOC_THERM>;
741871 		clock-names = "tsensor", "soctherm";
742872 		resets = <&tegra_car 78>;
743873 		reset-names = "soctherm";
....@@ -988,6 +1118,7 @@
9881118 		clock-names = "reg", "pll_u", "utmi-pads";
9891119 		resets = <&tegra_car 22>, <&tegra_car 22>;
9901120 		reset-names = "usb", "utmi-pads";
1121
+		#phy-cells = <0>;
9911122 		nvidia,hssync-start-delay = <0>;
9921123 		nvidia,idle-wait-delay = <17>;
9931124 		nvidia,elastic-limit = <16>;
....@@ -1026,6 +1157,7 @@
10261157 		clock-names = "reg", "pll_u", "utmi-pads";
10271158 		resets = <&tegra_car 58>, <&tegra_car 22>;
10281159 		reset-names = "usb", "utmi-pads";
1160
+		#phy-cells = <0>;
10291161 		nvidia,hssync-start-delay = <0>;
10301162 		nvidia,idle-wait-delay = <17>;
10311163 		nvidia,elastic-limit = <16>;
....@@ -1063,6 +1195,7 @@
10631195 		clock-names = "reg", "pll_u", "utmi-pads";
10641196 		resets = <&tegra_car 59>, <&tegra_car 22>;
10651197 		reset-names = "usb", "utmi-pads";
1198
+		#phy-cells = <0>;
10661199 		nvidia,hssync-start-delay = <0>;
10671200 		nvidia,idle-wait-delay = <17>;
10681201 		nvidia,elastic-limit = <16>;
....@@ -1082,13 +1215,13 @@
10821215 
10831216 		cpu@0 {
10841217 			device_type = "cpu";
1085
-			compatible = "nvidia,denver", "arm,armv8";
1218
+			compatible = "nvidia,tegra132-denver";
10861219 			reg = <0>;
10871220 		};
10881221 
10891222 		cpu@1 {
10901223 			device_type = "cpu";
1091
-			compatible = "nvidia,denver", "arm,armv8";
1224
+			compatible = "nvidia,tegra132-denver";
10921225 			reg = <1>;
10931226 		};
10941227 	};