forked from ~ljy/RK356X_SDK_RELEASE

blame | history | patch | commit | commitdiff
hc
2023-12-11 1f93a7dfd1f8d5ff7a5c53246c7534fe2332d6f4 
 kernel/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
....@@ -8,6 +8,8 @@
88 #include <dt-bindings/clock/mt2712-clk.h>
99 #include <dt-bindings/interrupt-controller/irq.h>
1010 #include <dt-bindings/interrupt-controller/arm-gic.h>
11
+#include <dt-bindings/memory/mt2712-larb-port.h>
12
+#include <dt-bindings/phy/phy.h>
1113 #include <dt-bindings/power/mt2712-power.h>
1214 #include "mt2712-pinfunc.h"
1315 
....@@ -276,7 +278,7 @@
276278 		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
277279 	};
278280 
279
-	scpsys: scpsys@10006000 {
281
+	scpsys: power-controller@10006000 {
280282 		compatible = "mediatek,mt2712-scpsys", "syscon";
281283 		#power-domain-cells = <1>;
282284 		reg = <0 0x10006000 0 0x1000>;
....@@ -298,13 +300,54 @@
298300 		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
299301 		clocks = <&baud_clk>, <&sys_clk>;
300302 		clock-names = "baud", "bus";
303
+		dmas = <&apdma 10
304
+			&apdma 11>;
305
+		dma-names = "tx", "rx";
301306 		status = "disabled";
307
+	};
308
+
309
+	rtc: rtc@10011000 {
310
+		compatible = "mediatek,mt2712-rtc";
311
+		reg = <0 0x10011000 0 0x1000>;
312
+		interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_LOW>;
313
+	};
314
+
315
+	spis1: spi@10013000 {
316
+		compatible = "mediatek,mt2712-spi-slave";
317
+		reg = <0 0x10013000 0 0x100>;
318
+		interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>;
319
+		clocks = <&infracfg CLK_INFRA_AO_SPI1>;
320
+		clock-names = "spi";
321
+		assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
322
+		assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
323
+		status = "disabled";
324
+	};
325
+
326
+	iommu0: iommu@10205000 {
327
+		compatible = "mediatek,mt2712-m4u";
328
+		reg = <0 0x10205000 0 0x1000>;
329
+		interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>;
330
+		clocks = <&infracfg CLK_INFRA_M4U>;
331
+		clock-names = "bclk";
332
+		mediatek,larbs = <&larb0 &larb1 &larb2
333
+				  &larb3 &larb6>;
334
+		#iommu-cells = <1>;
302335 	};
303336 
304337 	apmixedsys: syscon@10209000 {
305338 		compatible = "mediatek,mt2712-apmixedsys", "syscon";
306339 		reg = <0 0x10209000 0 0x1000>;
307340 		#clock-cells = <1>;
341
+	};
342
+
343
+	iommu1: iommu@1020a000 {
344
+		compatible = "mediatek,mt2712-m4u";
345
+		reg = <0 0x1020a000 0 0x1000>;
346
+		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
347
+		clocks = <&infracfg CLK_INFRA_M4U>;
348
+		clock-names = "bclk";
349
+		mediatek,larbs = <&larb4 &larb5 &larb7>;
350
+		#iommu-cells = <1>;
308351 	};
309352 
310353 	mcucfg: syscon@10220000 {
....@@ -335,6 +378,39 @@
335378 			 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;
336379 	};
337380 
381
+	apdma: dma-controller@11000400 {
382
+		compatible = "mediatek,mt2712-uart-dma",
383
+			     "mediatek,mt6577-uart-dma";
384
+		reg = <0 0x11000400 0 0x80>,
385
+		      <0 0x11000480 0 0x80>,
386
+		      <0 0x11000500 0 0x80>,
387
+		      <0 0x11000580 0 0x80>,
388
+		      <0 0x11000600 0 0x80>,
389
+		      <0 0x11000680 0 0x80>,
390
+		      <0 0x11000700 0 0x80>,
391
+		      <0 0x11000780 0 0x80>,
392
+		      <0 0x11000800 0 0x80>,
393
+		      <0 0x11000880 0 0x80>,
394
+		      <0 0x11000900 0 0x80>,
395
+		      <0 0x11000980 0 0x80>;
396
+		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
397
+			     <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
398
+			     <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
399
+			     <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
400
+			     <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
401
+			     <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
402
+			     <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
403
+			     <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,
404
+			     <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,
405
+			     <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,
406
+			     <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,
407
+			     <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
408
+		dma-requests = <12>;
409
+		clocks = <&pericfg CLK_PERI_AP_DMA>;
410
+		clock-names = "apdma";
411
+		#dma-cells = <1>;
412
+	};
413
+
338414 	auxadc: adc@11001000 {
339415 		compatible = "mediatek,mt2712-auxadc";
340416 		reg = <0 0x11001000 0 0x1000>;
....@@ -351,6 +427,9 @@
351427 		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
352428 		clocks = <&baud_clk>, <&sys_clk>;
353429 		clock-names = "baud", "bus";
430
+		dmas = <&apdma 0
431
+			&apdma 1>;
432
+		dma-names = "tx", "rx";
354433 		status = "disabled";
355434 	};
356435 
....@@ -361,6 +440,9 @@
361440 		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
362441 		clocks = <&baud_clk>, <&sys_clk>;
363442 		clock-names = "baud", "bus";
443
+		dmas = <&apdma 2
444
+			&apdma 3>;
445
+		dma-names = "tx", "rx";
364446 		status = "disabled";
365447 	};
366448 
....@@ -371,6 +453,9 @@
371453 		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
372454 		clocks = <&baud_clk>, <&sys_clk>;
373455 		clock-names = "baud", "bus";
456
+		dmas = <&apdma 4
457
+			&apdma 5>;
458
+		dma-names = "tx", "rx";
374459 		status = "disabled";
375460 	};
376461 
....@@ -381,6 +466,213 @@
381466 		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
382467 		clocks = <&baud_clk>, <&sys_clk>;
383468 		clock-names = "baud", "bus";
469
+		dmas = <&apdma 6
470
+			&apdma 7>;
471
+		dma-names = "tx", "rx";
472
+		status = "disabled";
473
+	};
474
+
475
+	pwm: pwm@11006000 {
476
+		compatible = "mediatek,mt2712-pwm";
477
+		reg = <0 0x11006000 0 0x1000>;
478
+		#pwm-cells = <2>;
479
+		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
480
+		clocks = <&topckgen CLK_TOP_PWM_SEL>,
481
+			 <&pericfg CLK_PERI_PWM>,
482
+			 <&pericfg CLK_PERI_PWM0>,
483
+			 <&pericfg CLK_PERI_PWM1>,
484
+			 <&pericfg CLK_PERI_PWM2>,
485
+			 <&pericfg CLK_PERI_PWM3>,
486
+			 <&pericfg CLK_PERI_PWM4>,
487
+			 <&pericfg CLK_PERI_PWM5>,
488
+			 <&pericfg CLK_PERI_PWM6>,
489
+			 <&pericfg CLK_PERI_PWM7>;
490
+		clock-names = "top",
491
+			      "main",
492
+			      "pwm1",
493
+			      "pwm2",
494
+			      "pwm3",
495
+			      "pwm4",
496
+			      "pwm5",
497
+			      "pwm6",
498
+			      "pwm7",
499
+			      "pwm8";
500
+		status = "disabled";
501
+	};
502
+
503
+	i2c0: i2c@11007000 {
504
+		compatible = "mediatek,mt2712-i2c";
505
+		reg = <0 0x11007000 0 0x90>,
506
+		      <0 0x11000180 0 0x80>;
507
+		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
508
+		clock-div = <4>;
509
+		clocks = <&pericfg CLK_PERI_I2C0>,
510
+			 <&pericfg CLK_PERI_AP_DMA>;
511
+		clock-names = "main",
512
+			      "dma";
513
+		#address-cells = <1>;
514
+		#size-cells = <0>;
515
+		status = "disabled";
516
+	};
517
+
518
+	i2c1: i2c@11008000 {
519
+		compatible = "mediatek,mt2712-i2c";
520
+		reg = <0 0x11008000 0 0x90>,
521
+		      <0 0x11000200 0 0x80>;
522
+		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
523
+		clock-div = <4>;
524
+		clocks = <&pericfg CLK_PERI_I2C1>,
525
+			 <&pericfg CLK_PERI_AP_DMA>;
526
+		clock-names = "main",
527
+			      "dma";
528
+		#address-cells = <1>;
529
+		#size-cells = <0>;
530
+		status = "disabled";
531
+	};
532
+
533
+	i2c2: i2c@11009000 {
534
+		compatible = "mediatek,mt2712-i2c";
535
+		reg = <0 0x11009000 0 0x90>,
536
+		      <0 0x11000280 0 0x80>;
537
+		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
538
+		clock-div = <4>;
539
+		clocks = <&pericfg CLK_PERI_I2C2>,
540
+			 <&pericfg CLK_PERI_AP_DMA>;
541
+		clock-names = "main",
542
+			      "dma";
543
+		#address-cells = <1>;
544
+		#size-cells = <0>;
545
+		status = "disabled";
546
+	};
547
+
548
+	spi0: spi@1100a000 {
549
+		compatible = "mediatek,mt2712-spi";
550
+		#address-cells = <1>;
551
+		#size-cells = <0>;
552
+		reg = <0 0x1100a000 0 0x100>;
553
+		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
554
+		clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
555
+			 <&topckgen CLK_TOP_SPI_SEL>,
556
+			 <&pericfg CLK_PERI_SPI0>;
557
+		clock-names = "parent-clk", "sel-clk", "spi-clk";
558
+		status = "disabled";
559
+	};
560
+
561
+	nandc: nfi@1100e000 {
562
+		compatible = "mediatek,mt2712-nfc";
563
+		reg = <0 0x1100e000 0 0x1000>;
564
+		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
565
+		clocks = <&topckgen CLK_TOP_NFI2X_EN>, <&pericfg CLK_PERI_NFI>;
566
+		clock-names = "nfi_clk", "pad_clk";
567
+		ecc-engine = <&bch>;
568
+		#address-cells = <1>;
569
+		#size-cells = <0>;
570
+		status = "disabled";
571
+	};
572
+
573
+	bch: ecc@1100f000 {
574
+		compatible = "mediatek,mt2712-ecc";
575
+		reg = <0 0x1100f000 0 0x1000>;
576
+		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
577
+		clocks = <&topckgen CLK_TOP_NFI1X_CK_EN>;
578
+		clock-names = "nfiecc_clk";
579
+		status = "disabled";
580
+	};
581
+
582
+	i2c3: i2c@11010000 {
583
+		compatible = "mediatek,mt2712-i2c";
584
+		reg = <0 0x11010000 0 0x90>,
585
+		      <0 0x11000300 0 0x80>;
586
+		interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
587
+		clock-div = <4>;
588
+		clocks = <&pericfg CLK_PERI_I2C3>,
589
+			 <&pericfg CLK_PERI_AP_DMA>;
590
+		clock-names = "main",
591
+			      "dma";
592
+		#address-cells = <1>;
593
+		#size-cells = <0>;
594
+		status = "disabled";
595
+	};
596
+
597
+	i2c4: i2c@11011000 {
598
+		compatible = "mediatek,mt2712-i2c";
599
+		reg = <0 0x11011000 0 0x90>,
600
+		      <0 0x11000380 0 0x80>;
601
+		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
602
+		clock-div = <4>;
603
+		clocks = <&pericfg CLK_PERI_I2C4>,
604
+			 <&pericfg CLK_PERI_AP_DMA>;
605
+		clock-names = "main",
606
+			      "dma";
607
+		#address-cells = <1>;
608
+		#size-cells = <0>;
609
+		status = "disabled";
610
+	};
611
+
612
+	i2c5: i2c@11013000 {
613
+		compatible = "mediatek,mt2712-i2c";
614
+		reg = <0 0x11013000 0 0x90>,
615
+		      <0 0x11000100 0 0x80>;
616
+		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
617
+		clock-div = <4>;
618
+		clocks = <&pericfg CLK_PERI_I2C5>,
619
+			 <&pericfg CLK_PERI_AP_DMA>;
620
+		clock-names = "main",
621
+			      "dma";
622
+		#address-cells = <1>;
623
+		#size-cells = <0>;
624
+		status = "disabled";
625
+	};
626
+
627
+	spi2: spi@11015000 {
628
+		compatible = "mediatek,mt2712-spi";
629
+		#address-cells = <1>;
630
+		#size-cells = <0>;
631
+		reg = <0 0x11015000 0 0x100>;
632
+		interrupts = <GIC_SPI 284 IRQ_TYPE_LEVEL_LOW>;
633
+		clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
634
+			 <&topckgen CLK_TOP_SPI_SEL>,
635
+			 <&pericfg CLK_PERI_SPI2>;
636
+		clock-names = "parent-clk", "sel-clk", "spi-clk";
637
+		status = "disabled";
638
+	};
639
+
640
+	spi3: spi@11016000 {
641
+		compatible = "mediatek,mt2712-spi";
642
+		#address-cells = <1>;
643
+		#size-cells = <0>;
644
+		reg = <0 0x11016000 0 0x100>;
645
+		interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_LOW>;
646
+		clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
647
+			 <&topckgen CLK_TOP_SPI_SEL>,
648
+			 <&pericfg CLK_PERI_SPI3>;
649
+		clock-names = "parent-clk", "sel-clk", "spi-clk";
650
+		status = "disabled";
651
+	};
652
+
653
+	spi4: spi@10012000 {
654
+		compatible = "mediatek,mt2712-spi";
655
+		#address-cells = <1>;
656
+		#size-cells = <0>;
657
+		reg = <0 0x10012000 0 0x100>;
658
+		interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_LOW>;
659
+		clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
660
+			 <&topckgen CLK_TOP_SPI_SEL>,
661
+			 <&infracfg CLK_INFRA_AO_SPI0>;
662
+		clock-names = "parent-clk", "sel-clk", "spi-clk";
663
+		status = "disabled";
664
+	};
665
+
666
+	spi5: spi@11018000 {
667
+		compatible = "mediatek,mt2712-spi";
668
+		#address-cells = <1>;
669
+		#size-cells = <0>;
670
+		reg = <0 0x11018000 0 0x100>;
671
+		interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_LOW>;
672
+		clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
673
+			 <&topckgen CLK_TOP_SPI_SEL>,
674
+			 <&pericfg CLK_PERI_SPI5>;
675
+		clock-names = "parent-clk", "sel-clk", "spi-clk";
384676 		status = "disabled";
385677 	};
386678 
....@@ -391,7 +683,297 @@
391683 		interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
392684 		clocks = <&baud_clk>, <&sys_clk>;
393685 		clock-names = "baud", "bus";
686
+		dmas = <&apdma 8
687
+			&apdma 9>;
688
+		dma-names = "tx", "rx";
394689 		status = "disabled";
690
+	};
691
+
692
+	stmmac_axi_setup: stmmac-axi-config {
693
+		snps,wr_osr_lmt = <0x7>;
694
+		snps,rd_osr_lmt = <0x7>;
695
+		snps,blen = <0 0 0 0 16 8 4>;
696
+	};
697
+
698
+	mtl_rx_setup: rx-queues-config {
699
+		snps,rx-queues-to-use = <1>;
700
+		snps,rx-sched-sp;
701
+		queue0 {
702
+			snps,dcb-algorithm;
703
+			snps,map-to-dma-channel = <0x0>;
704
+			snps,priority = <0x0>;
705
+		};
706
+	};
707
+
708
+	mtl_tx_setup: tx-queues-config {
709
+		snps,tx-queues-to-use = <3>;
710
+		snps,tx-sched-wrr;
711
+		queue0 {
712
+			snps,weight = <0x10>;
713
+			snps,dcb-algorithm;
714
+			snps,priority = <0x0>;
715
+		};
716
+		queue1 {
717
+			snps,weight = <0x11>;
718
+			snps,dcb-algorithm;
719
+			snps,priority = <0x1>;
720
+		};
721
+		queue2 {
722
+			snps,weight = <0x12>;
723
+			snps,dcb-algorithm;
724
+			snps,priority = <0x2>;
725
+		};
726
+	};
727
+
728
+	eth: ethernet@1101c000 {
729
+		compatible = "mediatek,mt2712-gmac";
730
+		reg = <0 0x1101c000 0 0x1300>;
731
+		interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
732
+		interrupt-names = "macirq";
733
+		mac-address = [00 55 7b b5 7d f7];
734
+		clock-names = "axi",
735
+			      "apb",
736
+			      "mac_main",
737
+			      "ptp_ref";
738
+		clocks = <&pericfg CLK_PERI_GMAC>,
739
+			 <&pericfg CLK_PERI_GMAC_PCLK>,
740
+			 <&topckgen CLK_TOP_ETHER_125M_SEL>,
741
+			 <&topckgen CLK_TOP_ETHER_50M_SEL>;
742
+		assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
743
+				  <&topckgen CLK_TOP_ETHER_50M_SEL>;
744
+		assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
745
+					 <&topckgen CLK_TOP_APLL1_D3>;
746
+		power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
747
+		mediatek,pericfg = <&pericfg>;
748
+		snps,axi-config = <&stmmac_axi_setup>;
749
+		snps,mtl-rx-config = <&mtl_rx_setup>;
750
+		snps,mtl-tx-config = <&mtl_tx_setup>;
751
+		snps,txpbl = <1>;
752
+		snps,rxpbl = <1>;
753
+		clk_csr = <0>;
754
+		status = "disabled";
755
+	};
756
+
757
+	mmc0: mmc@11230000 {
758
+		compatible = "mediatek,mt2712-mmc";
759
+		reg = <0 0x11230000 0 0x1000>;
760
+		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
761
+		clocks = <&pericfg CLK_PERI_MSDC30_0>,
762
+			 <&pericfg CLK_PERI_MSDC50_0_HCLK_EN>,
763
+			 <&pericfg CLK_PERI_MSDC30_0_QTR_EN>,
764
+			 <&pericfg CLK_PERI_MSDC50_0_EN>;
765
+		clock-names = "source", "hclk", "bus_clk", "source_cg";
766
+		status = "disabled";
767
+	};
768
+
769
+	mmc1: mmc@11240000 {
770
+		compatible = "mediatek,mt2712-mmc";
771
+		reg = <0 0x11240000 0 0x1000>;
772
+		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
773
+		clocks = <&pericfg CLK_PERI_MSDC30_1>,
774
+			 <&topckgen CLK_TOP_AXI_SEL>,
775
+			 <&pericfg CLK_PERI_MSDC30_1_EN>;
776
+		clock-names = "source", "hclk", "source_cg";
777
+		status = "disabled";
778
+	};
779
+
780
+	mmc2: mmc@11250000 {
781
+		compatible = "mediatek,mt2712-mmc";
782
+		reg = <0 0x11250000 0 0x1000>;
783
+		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
784
+		clocks = <&pericfg CLK_PERI_MSDC30_2>,
785
+			 <&topckgen CLK_TOP_AXI_SEL>,
786
+			 <&pericfg CLK_PERI_MSDC30_2_EN>;
787
+		clock-names = "source", "hclk", "source_cg";
788
+		status = "disabled";
789
+	};
790
+
791
+	ssusb: usb@11271000 {
792
+		compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
793
+		reg = <0 0x11271000 0 0x3000>,
794
+		      <0 0x11280700 0 0x0100>;
795
+		reg-names = "mac", "ippc";
796
+		interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
797
+		phys = <&u2port0 PHY_TYPE_USB2>,
798
+		       <&u2port1 PHY_TYPE_USB2>;
799
+		power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>;
800
+		clocks = <&topckgen CLK_TOP_USB30_SEL>;
801
+		clock-names = "sys_ck";
802
+		mediatek,syscon-wakeup = <&pericfg 0x510 2>;
803
+		#address-cells = <2>;
804
+		#size-cells = <2>;
805
+		ranges;
806
+		status = "disabled";
807
+
808
+		usb_host0: xhci@11270000 {
809
+			compatible = "mediatek,mt2712-xhci",
810
+				     "mediatek,mtk-xhci";
811
+			reg = <0 0x11270000 0 0x1000>;
812
+			reg-names = "mac";
813
+			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_LOW>;
814
+			power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>;
815
+			clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
816
+			clock-names = "sys_ck", "ref_ck";
817
+			status = "disabled";
818
+		};
819
+	};
820
+
821
+	u3phy0: usb-phy@11290000 {
822
+		compatible = "mediatek,mt2712-tphy",
823
+			     "mediatek,generic-tphy-v2";
824
+		#address-cells = <1>;
825
+		#size-cells = <1>;
826
+		ranges = <0 0 0x11290000 0x9000>;
827
+		status = "okay";
828
+
829
+		u2port0: usb-phy@0 {
830
+			reg = <0x0 0x700>;
831
+			clocks = <&clk26m>;
832
+			clock-names = "ref";
833
+			#phy-cells = <1>;
834
+			status = "okay";
835
+		};
836
+
837
+		u2port1: usb-phy@8000 {
838
+			reg = <0x8000 0x700>;
839
+			clocks = <&clk26m>;
840
+			clock-names = "ref";
841
+			#phy-cells = <1>;
842
+			status = "okay";
843
+		};
844
+
845
+		u3port0: usb-phy@8700 {
846
+			reg = <0x8700 0x900>;
847
+			clocks = <&clk26m>;
848
+			clock-names = "ref";
849
+			#phy-cells = <1>;
850
+			status = "okay";
851
+		};
852
+	};
853
+
854
+	ssusb1: usb@112c1000 {
855
+		compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
856
+		reg = <0 0x112c1000 0 0x3000>,
857
+		      <0 0x112d0700 0 0x0100>;
858
+		reg-names = "mac", "ippc";
859
+		interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_LOW>;
860
+		phys = <&u2port2 PHY_TYPE_USB2>,
861
+		       <&u2port3 PHY_TYPE_USB2>,
862
+		       <&u3port1 PHY_TYPE_USB3>;
863
+		power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>;
864
+		clocks = <&topckgen CLK_TOP_USB30_SEL>;
865
+		clock-names = "sys_ck";
866
+		mediatek,syscon-wakeup = <&pericfg 0x514 2>;
867
+		#address-cells = <2>;
868
+		#size-cells = <2>;
869
+		ranges;
870
+		status = "disabled";
871
+
872
+		usb_host1: xhci@112c0000 {
873
+			compatible = "mediatek,mt2712-xhci",
874
+				     "mediatek,mtk-xhci";
875
+			reg = <0 0x112c0000 0 0x1000>;
876
+			reg-names = "mac";
877
+			interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>;
878
+			power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>;
879
+			clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
880
+			clock-names = "sys_ck", "ref_ck";
881
+			status = "disabled";
882
+		};
883
+	};
884
+
885
+	u3phy1: usb-phy@112e0000 {
886
+		compatible = "mediatek,mt2712-tphy",
887
+			     "mediatek,generic-tphy-v2";
888
+		#address-cells = <1>;
889
+		#size-cells = <1>;
890
+		ranges = <0 0 0x112e0000 0x9000>;
891
+		status = "okay";
892
+
893
+		u2port2: usb-phy@0 {
894
+			reg = <0x0 0x700>;
895
+			clocks = <&clk26m>;
896
+			clock-names = "ref";
897
+			#phy-cells = <1>;
898
+			status = "okay";
899
+		};
900
+
901
+		u2port3: usb-phy@8000 {
902
+			reg = <0x8000 0x700>;
903
+			clocks = <&clk26m>;
904
+			clock-names = "ref";
905
+			#phy-cells = <1>;
906
+			status = "okay";
907
+		};
908
+
909
+		u3port1: usb-phy@8700 {
910
+			reg = <0x8700 0x900>;
911
+			clocks = <&clk26m>;
912
+			clock-names = "ref";
913
+			#phy-cells = <1>;
914
+			status = "okay";
915
+		};
916
+	};
917
+
918
+	pcie: pcie@11700000 {
919
+		compatible = "mediatek,mt2712-pcie";
920
+		device_type = "pci";
921
+		reg = <0 0x11700000 0 0x1000>,
922
+		      <0 0x112ff000 0 0x1000>;
923
+		reg-names = "port0", "port1";
924
+		#address-cells = <3>;
925
+		#size-cells = <2>;
926
+		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
927
+			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
928
+		clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
929
+			 <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
930
+			 <&pericfg CLK_PERI_PCIE0>,
931
+			 <&pericfg CLK_PERI_PCIE1>;
932
+		clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
933
+		phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>;
934
+		phy-names = "pcie-phy0", "pcie-phy1";
935
+		bus-range = <0x00 0xff>;
936
+		ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x10000000>;
937
+
938
+		pcie0: pcie@0,0 {
939
+			device_type = "pci";
940
+			status = "disabled";
941
+			reg = <0x0000 0 0 0 0>;
942
+			#address-cells = <3>;
943
+			#size-cells = <2>;
944
+			#interrupt-cells = <1>;
945
+			ranges;
946
+			interrupt-map-mask = <0 0 0 7>;
947
+			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
948
+					<0 0 0 2 &pcie_intc0 1>,
949
+					<0 0 0 3 &pcie_intc0 2>,
950
+					<0 0 0 4 &pcie_intc0 3>;
951
+			pcie_intc0: interrupt-controller {
952
+				interrupt-controller;
953
+				#address-cells = <0>;
954
+				#interrupt-cells = <1>;
955
+			};
956
+		};
957
+
958
+		pcie1: pcie@1,0 {
959
+			device_type = "pci";
960
+			status = "disabled";
961
+			reg = <0x0800 0 0 0 0>;
962
+			#address-cells = <3>;
963
+			#size-cells = <2>;
964
+			#interrupt-cells = <1>;
965
+			ranges;
966
+			interrupt-map-mask = <0 0 0 7>;
967
+			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
968
+					<0 0 0 2 &pcie_intc1 1>,
969
+					<0 0 0 3 &pcie_intc1 2>,
970
+					<0 0 0 4 &pcie_intc1 3>;
971
+			pcie_intc1: interrupt-controller {
972
+				interrupt-controller;
973
+				#address-cells = <0>;
974
+				#interrupt-cells = <1>;
975
+			};
976
+		};
395977 	};
396978 
397979 	mfgcfg: syscon@13000000 {
....@@ -406,10 +988,83 @@
406988 		#clock-cells = <1>;
407989 	};
408990 
991
+	larb0: larb@14021000 {
992
+		compatible = "mediatek,mt2712-smi-larb";
993
+		reg = <0 0x14021000 0 0x1000>;
994
+		mediatek,smi = <&smi_common0>;
995
+		mediatek,larb-id = <0>;
996
+		power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
997
+		clocks = <&mmsys CLK_MM_SMI_LARB0>,
998
+			 <&mmsys CLK_MM_SMI_LARB0>;
999
+		clock-names = "apb", "smi";
1000
+	};
1001
+
1002
+	smi_common0: smi@14022000 {
1003
+		compatible = "mediatek,mt2712-smi-common";
1004
+		reg = <0 0x14022000 0 0x1000>;
1005
+		power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1006
+		clocks = <&mmsys CLK_MM_SMI_COMMON>,
1007
+			 <&mmsys CLK_MM_SMI_COMMON>;
1008
+		clock-names = "apb", "smi";
1009
+	};
1010
+
1011
+	larb4: larb@14027000 {
1012
+		compatible = "mediatek,mt2712-smi-larb";
1013
+		reg = <0 0x14027000 0 0x1000>;
1014
+		mediatek,smi = <&smi_common1>;
1015
+		mediatek,larb-id = <4>;
1016
+		power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1017
+		clocks = <&mmsys CLK_MM_SMI_LARB4>,
1018
+			 <&mmsys CLK_MM_SMI_LARB4>;
1019
+		clock-names = "apb", "smi";
1020
+	};
1021
+
1022
+	larb5: larb@14030000 {
1023
+		compatible = "mediatek,mt2712-smi-larb";
1024
+		reg = <0 0x14030000 0 0x1000>;
1025
+		mediatek,smi = <&smi_common1>;
1026
+		mediatek,larb-id = <5>;
1027
+		power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1028
+		clocks = <&mmsys CLK_MM_SMI_LARB5>,
1029
+			 <&mmsys CLK_MM_SMI_LARB5>;
1030
+		clock-names = "apb", "smi";
1031
+	};
1032
+
1033
+	smi_common1: smi@14031000 {
1034
+		compatible = "mediatek,mt2712-smi-common";
1035
+		reg = <0 0x14031000 0 0x1000>;
1036
+		power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1037
+		clocks = <&mmsys CLK_MM_SMI_COMMON1>,
1038
+			 <&mmsys CLK_MM_SMI_COMMON1>;
1039
+		clock-names = "apb", "smi";
1040
+	};
1041
+
1042
+	larb7: larb@14032000 {
1043
+		compatible = "mediatek,mt2712-smi-larb";
1044
+		reg = <0 0x14032000 0 0x1000>;
1045
+		mediatek,smi = <&smi_common1>;
1046
+		mediatek,larb-id = <7>;
1047
+		power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1048
+		clocks = <&mmsys CLK_MM_SMI_LARB7>,
1049
+			 <&mmsys CLK_MM_SMI_LARB7>;
1050
+		clock-names = "apb", "smi";
1051
+	};
1052
+
4091053 	imgsys: syscon@15000000 {
4101054 		compatible = "mediatek,mt2712-imgsys", "syscon";
4111055 		reg = <0 0x15000000 0 0x1000>;
4121056 		#clock-cells = <1>;
1057
+	};
1058
+
1059
+	larb2: larb@15001000 {
1060
+		compatible = "mediatek,mt2712-smi-larb";
1061
+		reg = <0 0x15001000 0 0x1000>;
1062
+		mediatek,smi = <&smi_common0>;
1063
+		mediatek,larb-id = <2>;
1064
+		power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>;
1065
+		clocks = <&imgsys CLK_IMG_SMI_LARB2>,
1066
+			 <&imgsys CLK_IMG_SMI_LARB2>;
1067
+		clock-names = "apb", "smi";
4131068 	};
4141069 
4151070 	bdpsys: syscon@15010000 {
....@@ -424,12 +1079,45 @@
4241079 		#clock-cells = <1>;
4251080 	};
4261081 
1082
+	larb1: larb@16010000 {
1083
+		compatible = "mediatek,mt2712-smi-larb";
1084
+		reg = <0 0x16010000 0 0x1000>;
1085
+		mediatek,smi = <&smi_common0>;
1086
+		mediatek,larb-id = <1>;
1087
+		power-domains = <&scpsys MT2712_POWER_DOMAIN_VDEC>;
1088
+		clocks = <&vdecsys CLK_VDEC_CKEN>,
1089
+			 <&vdecsys CLK_VDEC_LARB1_CKEN>;
1090
+		clock-names = "apb", "smi";
1091
+	};
1092
+
4271093 	vencsys: syscon@18000000 {
4281094 		compatible = "mediatek,mt2712-vencsys", "syscon";
4291095 		reg = <0 0x18000000 0 0x1000>;
4301096 		#clock-cells = <1>;
4311097 	};
4321098 
1099
+	larb3: larb@18001000 {
1100
+		compatible = "mediatek,mt2712-smi-larb";
1101
+		reg = <0 0x18001000 0 0x1000>;
1102
+		mediatek,smi = <&smi_common0>;
1103
+		mediatek,larb-id = <3>;
1104
+		power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>;
1105
+		clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>,
1106
+			 <&vencsys CLK_VENC_VENC>;
1107
+		clock-names = "apb", "smi";
1108
+	};
1109
+
1110
+	larb6: larb@18002000 {
1111
+		compatible = "mediatek,mt2712-smi-larb";
1112
+		reg = <0 0x18002000 0 0x1000>;
1113
+		mediatek,smi = <&smi_common0>;
1114
+		mediatek,larb-id = <6>;
1115
+		power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>;
1116
+		clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>,
1117
+			 <&vencsys CLK_VENC_VENC>;
1118
+		clock-names = "apb", "smi";
1119
+	};
1120
+
4331121 	jpgdecsys: syscon@19000000 {
4341122 		compatible = "mediatek,mt2712-jpgdecsys", "syscon";
4351123 		reg = <0 0x19000000 0 0x1000>;