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2023-12-11 1f93a7dfd1f8d5ff7a5c53246c7534fe2332d6f4

 kernel/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
..
..
@@ -2,7 +2,7 @@
2
2
 /*
3
3
  * Device Tree Include file for NXP Layerscape-1088A family SoC.
4
4
  *
5
- * Copyright 2017 NXP
5
+ * Copyright 2017-2020 NXP
6
6
  *
7
7
  * Harninder Rai <harninder.rai@nxp.com>
8
8
  *
..
..
@@ -18,6 +18,7 @@
18
18
 
19
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 	aliases {
20
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 		crypto = &crypto;
21
+		rtc1 = &ftm_alarm0;
21
22
 	};
22
23
 
23
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 	cpus {
..
..
@@ -129,19 +130,19 @@
129
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 	};
130
131
 
131
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 	thermal-zones {
132
-		cpu_thermal: cpu-thermal {
133
+		core-cluster {
133
134
 			polling-delay-passive = <1000>;
134
135
 			polling-delay = <5000>;
135
136
 			thermal-sensors = <&tmu 0>;
136
137
 
137
138
 			trips {
138
-				cpu_alert: cpu-alert {
139
+				core_cluster_alert: core-cluster-alert {
139
140
 					temperature = <85000>;
140
141
 					hysteresis = <2000>;
141
142
 					type = "passive";
142
143
 				};
143
144
 
144
-				cpu_crit: cpu-crit {
145
+				core-cluster-crit {
145
146
 					temperature = <95000>;
146
147
 					hysteresis = <2000>;
147
148
 					type = "critical";
..
..
@@ -150,17 +151,30 @@
150
151
 
151
152
 			cooling-maps {
152
153
 				map0 {
153
-					trip = <&cpu_alert>;
154
+					trip = <&core_cluster_alert>;
154
155
 					cooling-device =
155
-						<&cpu0 THERMAL_NO_LIMIT
156
-						THERMAL_NO_LIMIT>;
156
+						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
157
+						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
158
+						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
159
+						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
160
+						<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
161
+						<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
162
+						<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
163
+						<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
157
164
 				};
165
+			};
166
+		};
158
167
 
159
-				map1 {
160
-					trip = <&cpu_alert>;
161
-					cooling-device =
162
-						<&cpu4 THERMAL_NO_LIMIT
163
-						THERMAL_NO_LIMIT>;
168
+		soc {
169
+			polling-delay-passive = <1000>;
170
+			polling-delay = <5000>;
171
+			thermal-sensors = <&tmu 1>;
172
+
173
+			trips {
174
+				soc-crit {
175
+					temperature = <95000>;
176
+					hysteresis = <2000>;
177
+					type = "critical";
164
178
 				};
165
179
 			};
166
180
 		};
..
..
@@ -172,77 +186,6 @@
172
186
 			     <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
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187
 			     <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
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188
 			     <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
175
-	};
176
-
177
-	fsl_mc: fsl-mc@80c000000 {
178
-		compatible = "fsl,qoriq-mc";
179
-		reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */
180
-		      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
181
-		msi-parent = <&its>;
182
-		#address-cells = <3>;
183
-		#size-cells = <1>;
184
-
185
-		/*
186
-		 * Region type 0x0 - MC portals
187
-		 * Region type 0x1 - QBMAN portals
188
-		 */
189
-		ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
190
-			  0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
191
-
192
-		dpmacs {
193
-			#address-cells = <1>;
194
-			#size-cells = <0>;
195
-
196
-			dpmac1: dpmac@1 {
197
-				compatible = "fsl,qoriq-mc-dpmac";
198
-				reg = <1>;
199
-			};
200
-
201
-			dpmac2: dpmac@2 {
202
-				compatible = "fsl,qoriq-mc-dpmac";
203
-				reg = <2>;
204
-			};
205
-
206
-			dpmac3: dpmac@3 {
207
-				compatible = "fsl,qoriq-mc-dpmac";
208
-				reg = <3>;
209
-			};
210
-
211
-			dpmac4: dpmac@4 {
212
-				compatible = "fsl,qoriq-mc-dpmac";
213
-				reg = <4>;
214
-			};
215
-
216
-			dpmac5: dpmac@5 {
217
-				compatible = "fsl,qoriq-mc-dpmac";
218
-				reg = <5>;
219
-			};
220
-
221
-			dpmac6: dpmac@6 {
222
-				compatible = "fsl,qoriq-mc-dpmac";
223
-				reg = <6>;
224
-			};
225
-
226
-			dpmac7: dpmac@7 {
227
-				compatible = "fsl,qoriq-mc-dpmac";
228
-				reg = <7>;
229
-			};
230
-
231
-			dpmac8: dpmac@8 {
232
-				compatible = "fsl,qoriq-mc-dpmac";
233
-				reg = <8>;
234
-			};
235
-
236
-			dpmac9: dpmac@9 {
237
-				compatible = "fsl,qoriq-mc-dpmac";
238
-				reg = <9>;
239
-			};
240
-
241
-			dpmac10: dpmac@a {
242
-				compatible = "fsl,qoriq-mc-dpmac";
243
-				reg = <0xa>;
244
-			};
245
-		};
246
189
 	};
247
190
 
248
191
 	psci {
..
..
@@ -262,6 +205,7 @@
262
205
 		#address-cells = <2>;
263
206
 		#size-cells = <2>;
264
207
 		ranges;
208
+		dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
265
209
 
266
210
 		clockgen: clocking@1300000 {
267
211
 			compatible = "fsl,ls1088a-clockgen";
..
..
@@ -280,47 +224,64 @@
280
224
 			compatible = "fsl,qoriq-tmu";
281
225
 			reg = <0x0 0x1f80000 0x0 0x10000>;
282
226
 			interrupts = <0 23 0x4>;
283
-			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
227
+			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
284
228
 			fsl,tmu-calibration =
285
229
 				/* Calibration data group 1 */
286
-				<0x00000000 0x00000026
287
-				0x00000001 0x0000002d
288
-				0x00000002 0x00000032
289
-				0x00000003 0x00000039
290
-				0x00000004 0x0000003f
291
-				0x00000005 0x00000046
292
-				0x00000006 0x0000004d
293
-				0x00000007 0x00000054
294
-				0x00000008 0x0000005a
295
-				0x00000009 0x00000061
296
-				0x0000000a 0x0000006a
297
-				0x0000000b 0x00000071
230
+				<0x00000000 0x00000023
231
+				0x00000001 0x0000002a
232
+				0x00000002 0x00000030
233
+				0x00000003 0x00000037
234
+				0x00000004 0x0000003d
235
+				0x00000005 0x00000044
236
+				0x00000006 0x0000004a
237
+				0x00000007 0x00000051
238
+				0x00000008 0x00000057
239
+				0x00000009 0x0000005e
240
+				0x0000000a 0x00000064
241
+				0x0000000b 0x0000006b
298
242
 				/* Calibration data group 2 */
299
-				0x00010000 0x00000025
300
-				0x00010001 0x0000002c
301
-				0x00010002 0x00000035
302
-				0x00010003 0x0000003d
303
-				0x00010004 0x00000045
304
-				0x00010005 0x0000004e
305
-				0x00010006 0x00000057
306
-				0x00010007 0x00000061
307
-				0x00010008 0x0000006b
308
-				0x00010009 0x00000076
243
+				0x00010000 0x00000022
244
+				0x00010001 0x0000002a
245
+				0x00010002 0x00000032
246
+				0x00010003 0x0000003a
247
+				0x00010004 0x00000042
248
+				0x00010005 0x0000004a
249
+				0x00010006 0x00000052
250
+				0x00010007 0x0000005a
251
+				0x00010008 0x00000062
252
+				0x00010009 0x0000006a
309
253
 				/* Calibration data group 3 */
310
-				0x00020000 0x00000029
311
-				0x00020001 0x00000033
312
-				0x00020002 0x0000003d
313
-				0x00020003 0x00000049
314
-				0x00020004 0x00000056
315
-				0x00020005 0x00000061
316
-				0x00020006 0x0000006d
254
+				0x00020000 0x00000021
255
+				0x00020001 0x0000002b
256
+				0x00020002 0x00000035
257
+				0x00020003 0x00000040
258
+				0x00020004 0x0000004a
259
+				0x00020005 0x00000054
260
+				0x00020006 0x0000005e
317
261
 				/* Calibration data group 4 */
318
-				0x00030000 0x00000021
319
-				0x00030001 0x0000002a
320
-				0x00030002 0x0000003c
321
-				0x00030003 0x0000004e>;
262
+				0x00030000 0x00000010
263
+				0x00030001 0x0000001c
264
+				0x00030002 0x00000027
265
+				0x00030003 0x00000032
266
+				0x00030004 0x0000003e
267
+				0x00030005 0x00000049
268
+				0x00030006 0x00000054
269
+				0x00030007 0x00000060>;
322
270
 			little-endian;
323
271
 			#thermal-sensor-cells = <1>;
272
+		};
273
+
274
+		dspi: spi@2100000 {
275
+			compatible = "fsl,ls1088a-dspi",
276
+				     "fsl,ls1021a-v1.0-dspi";
277
+			#address-cells = <1>;
278
+			#size-cells = <0>;
279
+			reg = <0x0 0x2100000 0x0 0x10000>;
280
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
281
+			clock-names = "dspi";
282
+			clocks = <&clockgen 4 1>;
283
+			spi-num-chipselects = <6>;
284
+			status = "disabled";
324
285
 		};
325
286
 
326
287
 		duart0: serial@21c0500 {
..
..
@@ -340,9 +301,10 @@
340
301
 		};
341
302
 
342
303
 		gpio0: gpio@2300000 {
343
-			compatible = "fsl,qoriq-gpio";
304
+			compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
344
305
 			reg = <0x0 0x2300000 0x0 0x10000>;
345
306
 			interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
307
+			little-endian;
346
308
 			gpio-controller;
347
309
 			#gpio-cells = <2>;
348
310
 			interrupt-controller;
..
..
@@ -350,9 +312,10 @@
350
312
 		};
351
313
 
352
314
 		gpio1: gpio@2310000 {
353
-			compatible = "fsl,qoriq-gpio";
315
+			compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
354
316
 			reg = <0x0 0x2310000 0x0 0x10000>;
355
317
 			interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
318
+			little-endian;
356
319
 			gpio-controller;
357
320
 			#gpio-cells = <2>;
358
321
 			interrupt-controller;
..
..
@@ -360,9 +323,10 @@
360
323
 		};
361
324
 
362
325
 		gpio2: gpio@2320000 {
363
-			compatible = "fsl,qoriq-gpio";
326
+			compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
364
327
 			reg = <0x0 0x2320000 0x0 0x10000>;
365
328
 			interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
329
+			little-endian;
366
330
 			gpio-controller;
367
331
 			#gpio-cells = <2>;
368
332
 			interrupt-controller;
..
..
@@ -370,9 +334,10 @@
370
334
 		};
371
335
 
372
336
 		gpio3: gpio@2330000 {
373
-			compatible = "fsl,qoriq-gpio";
337
+			compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
374
338
 			reg = <0x0 0x2330000 0x0 0x10000>;
375
339
 			interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
340
+			little-endian;
376
341
 			gpio-controller;
377
342
 			#gpio-cells = <2>;
378
343
 			interrupt-controller;
..
..
@@ -395,7 +360,7 @@
395
360
 			#size-cells = <0>;
396
361
 			reg = <0x0 0x2000000 0x0 0x10000>;
397
362
 			interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
398
-			clocks = <&clockgen 4 3>;
363
+			clocks = <&clockgen 4 7>;
399
364
 			status = "disabled";
400
365
 		};
401
366
 
..
..
@@ -405,7 +370,7 @@
405
370
 			#size-cells = <0>;
406
371
 			reg = <0x0 0x2010000 0x0 0x10000>;
407
372
 			interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
408
-			clocks = <&clockgen 4 3>;
373
+			clocks = <&clockgen 4 7>;
409
374
 			status = "disabled";
410
375
 		};
411
376
 
..
..
@@ -415,7 +380,7 @@
415
380
 			#size-cells = <0>;
416
381
 			reg = <0x0 0x2020000 0x0 0x10000>;
417
382
 			interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
418
-			clocks = <&clockgen 4 3>;
383
+			clocks = <&clockgen 4 7>;
419
384
 			status = "disabled";
420
385
 		};
421
386
 
..
..
@@ -425,7 +390,20 @@
425
390
 			#size-cells = <0>;
426
391
 			reg = <0x0 0x2030000 0x0 0x10000>;
427
392
 			interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
428
-			clocks = <&clockgen 4 3>;
393
+			clocks = <&clockgen 4 7>;
394
+			status = "disabled";
395
+		};
396
+
397
+		qspi: spi@20c0000 {
398
+			compatible = "fsl,ls2080a-qspi";
399
+			#address-cells = <1>;
400
+			#size-cells = <0>;
401
+			reg = <0x0 0x20c0000 0x0 0x10000>,
402
+			      <0x0 0x20000000 0x0 0x10000000>;
403
+			reg-names = "QuadSPI", "QuadSPI-memory";
404
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
405
+			clock-names = "qspi_en", "qspi";
406
+			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
429
407
 			status = "disabled";
430
408
 		};
431
409
 
..
..
@@ -434,6 +412,7 @@
434
412
 			reg = <0x0 0x2140000 0x0 0x10000>;
435
413
 			interrupts = <0 28 0x4>; /* Level high type */
436
414
 			clock-frequency = <0>;
415
+			clocks = <&clockgen 2 1>;
437
416
 			voltage-ranges = <1800 1800 3300 3300>;
438
417
 			sdhci,auto-cmd12;
439
418
 			little-endian;
..
..
@@ -448,6 +427,7 @@
448
427
 			dr_mode = "host";
449
428
 			snps,quirk-frame-length-adjustment = <0x20>;
450
429
 			snps,dis_rxdet_inp3_quirk;
430
+			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
451
431
 			status = "disabled";
452
432
 		};
453
433
 
..
..
@@ -511,8 +491,8 @@
511
491
 			};
512
492
 		};
513
493
 
514
-		pcie@3400000 {
515
-			compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
494
+		pcie1: pcie@3400000 {
495
+			compatible = "fsl,ls1088a-pcie";
516
496
 			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
517
497
 			       0x20 0x00000000 0x0 0x00002000>; /* configuration space */
518
498
 			reg-names = "regs", "config";
..
..
@@ -522,7 +502,7 @@
522
502
 			#size-cells = <2>;
523
503
 			device_type = "pci";
524
504
 			dma-coherent;
525
-			num-lanes = <4>;
505
+			num-viewport = <256>;
526
506
 			bus-range = <0x0 0xff>;
527
507
 			ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000   /* downstream I/O */
528
508
 				  0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
..
..
@@ -533,10 +513,12 @@
533
513
 					<0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
534
514
 					<0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
535
515
 					<0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
516
+			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
517
+			status = "disabled";
536
518
 		};
537
519
 
538
-		pcie@3500000 {
539
-			compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
520
+		pcie2: pcie@3500000 {
521
+			compatible = "fsl,ls1088a-pcie";
540
522
 			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
541
523
 			       0x28 0x00000000 0x0 0x00002000>; /* configuration space */
542
524
 			reg-names = "regs", "config";
..
..
@@ -546,7 +528,7 @@
546
528
 			#size-cells = <2>;
547
529
 			device_type = "pci";
548
530
 			dma-coherent;
549
-			num-lanes = <4>;
531
+			num-viewport = <6>;
550
532
 			bus-range = <0x0 0xff>;
551
533
 			ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000   /* downstream I/O */
552
534
 				  0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
..
..
@@ -557,10 +539,12 @@
557
539
 					<0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
558
540
 					<0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
559
541
 					<0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
542
+			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
543
+			status = "disabled";
560
544
 		};
561
545
 
562
-		pcie@3600000 {
563
-			compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
546
+		pcie3: pcie@3600000 {
547
+			compatible = "fsl,ls1088a-pcie";
564
548
 			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
565
549
 			       0x30 0x00000000 0x0 0x00002000>; /* configuration space */
566
550
 			reg-names = "regs", "config";
..
..
@@ -570,7 +554,7 @@
570
554
 			#size-cells = <2>;
571
555
 			device_type = "pci";
572
556
 			dma-coherent;
573
-			num-lanes = <8>;
557
+			num-viewport = <6>;
574
558
 			bus-range = <0x0 0xff>;
575
559
 			ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000   /* downstream I/O */
576
560
 				  0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
..
..
@@ -581,62 +565,254 @@
581
565
 					<0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
582
566
 					<0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
583
567
 					<0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
568
+			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
569
+			status = "disabled";
570
+		};
571
+
572
+		smmu: iommu@5000000 {
573
+			compatible = "arm,mmu-500";
574
+			reg = <0 0x5000000 0 0x800000>;
575
+			#iommu-cells = <1>;
576
+			stream-match-mask = <0x7C00>;
577
+			#global-interrupts = <12>;
578
+				     // global secure fault
579
+			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
580
+				     // combined secure
581
+				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
582
+				     // global non-secure fault
583
+				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
584
+				     // combined non-secure
585
+				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
586
+				     // performance counter interrupts 0-7
587
+				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
588
+				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
589
+				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
590
+				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
591
+				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
592
+				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
593
+				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
594
+				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
595
+				     // per context interrupt, 64 interrupts
596
+				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
597
+				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
598
+				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
599
+				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
600
+				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
601
+				     <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
602
+				     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
603
+				     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
604
+				     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
605
+				     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
606
+				     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
607
+				     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
608
+				     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
609
+				     <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
610
+				     <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
611
+				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
612
+				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
613
+				     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
614
+				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
615
+				     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
616
+				     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
617
+				     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
618
+				     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
619
+				     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
620
+				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
621
+				     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
622
+				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
623
+				     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
624
+				     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
625
+				     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
626
+				     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
627
+				     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
628
+				     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
629
+				     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
630
+				     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
631
+				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
632
+				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
633
+				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
634
+				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
635
+				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
636
+				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
637
+				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
638
+				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
639
+				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
640
+				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
641
+				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
642
+				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
643
+				     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
644
+				     <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
645
+				     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
646
+				     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
647
+				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
648
+				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
649
+				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
650
+				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
651
+				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
652
+				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
653
+				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
654
+				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
655
+				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
656
+				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
657
+				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
658
+				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
659
+				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
660
+		};
661
+
662
+		console@8340020 {
663
+			compatible = "fsl,dpaa2-console";
664
+			reg = <0x00000000 0x08340020 0 0x2>;
665
+		};
666
+
667
+		ptp-timer@8b95000 {
668
+			compatible = "fsl,dpaa2-ptp";
669
+			reg = <0x0 0x8b95000 0x0 0x100>;
670
+			clocks = <&clockgen 4 0>;
671
+			little-endian;
672
+			fsl,extts-fifo;
584
673
 		};
585
674
 
586
675
 		cluster1_core0_watchdog: wdt@c000000 {
587
676
 			compatible = "arm,sp805", "arm,primecell";
588
677
 			reg = <0x0 0xc000000 0x0 0x1000>;
589
-			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
590
-			clock-names = "apb_pclk", "wdog_clk";
678
+			clocks = <&clockgen 4 15>, <&clockgen 4 15>;
679
+			clock-names = "wdog_clk", "apb_pclk";
591
680
 		};
592
681
 
593
682
 		cluster1_core1_watchdog: wdt@c010000 {
594
683
 			compatible = "arm,sp805", "arm,primecell";
595
684
 			reg = <0x0 0xc010000 0x0 0x1000>;
596
-			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
597
-			clock-names = "apb_pclk", "wdog_clk";
685
+			clocks = <&clockgen 4 15>, <&clockgen 4 15>;
686
+			clock-names = "wdog_clk", "apb_pclk";
598
687
 		};
599
688
 
600
689
 		cluster1_core2_watchdog: wdt@c020000 {
601
690
 			compatible = "arm,sp805", "arm,primecell";
602
691
 			reg = <0x0 0xc020000 0x0 0x1000>;
603
-			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
604
-			clock-names = "apb_pclk", "wdog_clk";
692
+			clocks = <&clockgen 4 15>, <&clockgen 4 15>;
693
+			clock-names = "wdog_clk", "apb_pclk";
605
694
 		};
606
695
 
607
696
 		cluster1_core3_watchdog: wdt@c030000 {
608
697
 			compatible = "arm,sp805", "arm,primecell";
609
698
 			reg = <0x0 0xc030000 0x0 0x1000>;
610
-			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
611
-			clock-names = "apb_pclk", "wdog_clk";
699
+			clocks = <&clockgen 4 15>, <&clockgen 4 15>;
700
+			clock-names = "wdog_clk", "apb_pclk";
612
701
 		};
613
702
 
614
703
 		cluster2_core0_watchdog: wdt@c100000 {
615
704
 			compatible = "arm,sp805", "arm,primecell";
616
705
 			reg = <0x0 0xc100000 0x0 0x1000>;
617
-			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
618
-			clock-names = "apb_pclk", "wdog_clk";
706
+			clocks = <&clockgen 4 15>, <&clockgen 4 15>;
707
+			clock-names = "wdog_clk", "apb_pclk";
619
708
 		};
620
709
 
621
710
 		cluster2_core1_watchdog: wdt@c110000 {
622
711
 			compatible = "arm,sp805", "arm,primecell";
623
712
 			reg = <0x0 0xc110000 0x0 0x1000>;
624
-			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
625
-			clock-names = "apb_pclk", "wdog_clk";
713
+			clocks = <&clockgen 4 15>, <&clockgen 4 15>;
714
+			clock-names = "wdog_clk", "apb_pclk";
626
715
 		};
627
716
 
628
717
 		cluster2_core2_watchdog: wdt@c120000 {
629
718
 			compatible = "arm,sp805", "arm,primecell";
630
719
 			reg = <0x0 0xc120000 0x0 0x1000>;
631
-			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
632
-			clock-names = "apb_pclk", "wdog_clk";
720
+			clocks = <&clockgen 4 15>, <&clockgen 4 15>;
721
+			clock-names = "wdog_clk", "apb_pclk";
633
722
 		};
634
723
 
635
724
 		cluster2_core3_watchdog: wdt@c130000 {
636
725
 			compatible = "arm,sp805", "arm,primecell";
637
726
 			reg = <0x0 0xc130000 0x0 0x1000>;
638
-			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
639
-			clock-names = "apb_pclk", "wdog_clk";
727
+			clocks = <&clockgen 4 15>, <&clockgen 4 15>;
728
+			clock-names = "wdog_clk", "apb_pclk";
729
+		};
730
+
731
+		fsl_mc: fsl-mc@80c000000 {
732
+			compatible = "fsl,qoriq-mc";
733
+			reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */
734
+			      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
735
+			msi-parent = <&its>;
736
+			iommu-map = <0 &smmu 0 0>;	/* This is fixed-up by u-boot */
737
+			dma-coherent;
738
+			#address-cells = <3>;
739
+			#size-cells = <1>;
740
+
741
+			/*
742
+			 * Region type 0x0 - MC portals
743
+			 * Region type 0x1 - QBMAN portals
744
+			 */
745
+			ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
746
+				  0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
747
+
748
+			dpmacs {
749
+				#address-cells = <1>;
750
+				#size-cells = <0>;
751
+
752
+				dpmac1: dpmac@1 {
753
+					compatible = "fsl,qoriq-mc-dpmac";
754
+					reg = <1>;
755
+				};
756
+
757
+				dpmac2: dpmac@2 {
758
+					compatible = "fsl,qoriq-mc-dpmac";
759
+					reg = <2>;
760
+				};
761
+
762
+				dpmac3: dpmac@3 {
763
+					compatible = "fsl,qoriq-mc-dpmac";
764
+					reg = <3>;
765
+				};
766
+
767
+				dpmac4: dpmac@4 {
768
+					compatible = "fsl,qoriq-mc-dpmac";
769
+					reg = <4>;
770
+				};
771
+
772
+				dpmac5: dpmac@5 {
773
+					compatible = "fsl,qoriq-mc-dpmac";
774
+					reg = <5>;
775
+				};
776
+
777
+				dpmac6: dpmac@6 {
778
+					compatible = "fsl,qoriq-mc-dpmac";
779
+					reg = <6>;
780
+				};
781
+
782
+				dpmac7: dpmac@7 {
783
+					compatible = "fsl,qoriq-mc-dpmac";
784
+					reg = <7>;
785
+				};
786
+
787
+				dpmac8: dpmac@8 {
788
+					compatible = "fsl,qoriq-mc-dpmac";
789
+					reg = <8>;
790
+				};
791
+
792
+				dpmac9: dpmac@9 {
793
+					compatible = "fsl,qoriq-mc-dpmac";
794
+					reg = <9>;
795
+				};
796
+
797
+				dpmac10: dpmac@a {
798
+					compatible = "fsl,qoriq-mc-dpmac";
799
+					reg = <0xa>;
800
+				};
801
+			};
802
+		};
803
+
804
+		rcpm: power-controller@1e34040 {
805
+			compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+";
806
+			reg = <0x0 0x1e34040 0x0 0x18>;
807
+			#fsl,rcpm-wakeup-cells = <6>;
808
+			little-endian;
809
+		};
810
+
811
+		ftm_alarm0: timer@2800000 {
812
+			compatible = "fsl,ls1088a-ftm-alarm";
813
+			reg = <0x0 0x2800000 0x0 0x10000>;
814
+			fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
815
+			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
640
816
 		};
641
817
 	};
642
818
 
..
..
@@ -646,5 +822,4 @@
646
822
 			method = "smc";
647
823
 		};
648
824
 	};
649
-
650
825
 };