.. | .. |
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47 | 47 | |
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48 | 48 | A57_0: cpu@0 { |
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49 | 49 | device_type = "cpu"; |
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50 | | - compatible = "arm,cortex-a57", "arm,armv8"; |
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| 50 | + compatible = "arm,cortex-a57"; |
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51 | 51 | reg = <0 0>; |
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52 | 52 | enable-method = "psci"; |
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53 | 53 | next-level-cache = <&CLUSTER0_L2>; |
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.. | .. |
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55 | 55 | |
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56 | 56 | A57_1: cpu@1 { |
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57 | 57 | device_type = "cpu"; |
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58 | | - compatible = "arm,cortex-a57", "arm,armv8"; |
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| 58 | + compatible = "arm,cortex-a57"; |
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59 | 59 | reg = <0 1>; |
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60 | 60 | enable-method = "psci"; |
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61 | 61 | next-level-cache = <&CLUSTER0_L2>; |
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.. | .. |
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63 | 63 | |
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64 | 64 | A57_2: cpu@2 { |
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65 | 65 | device_type = "cpu"; |
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66 | | - compatible = "arm,cortex-a57", "arm,armv8"; |
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| 66 | + compatible = "arm,cortex-a57"; |
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67 | 67 | reg = <0 2>; |
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68 | 68 | enable-method = "psci"; |
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69 | 69 | next-level-cache = <&CLUSTER0_L2>; |
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.. | .. |
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71 | 71 | |
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72 | 72 | A57_3: cpu@3 { |
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73 | 73 | device_type = "cpu"; |
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74 | | - compatible = "arm,cortex-a57", "arm,armv8"; |
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| 74 | + compatible = "arm,cortex-a57"; |
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75 | 75 | reg = <0 3>; |
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76 | 76 | enable-method = "psci"; |
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77 | 77 | next-level-cache = <&CLUSTER0_L2>; |
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.. | .. |
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576 | 576 | reg = <0x66090000 0x1000>; |
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577 | 577 | interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>; |
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578 | 578 | clocks = <&iprocslow>, <&iprocslow>; |
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579 | | - clock-names = "wdogclk", "apb_pclk"; |
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| 579 | + clock-names = "wdog_clk", "apb_pclk"; |
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580 | 580 | }; |
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581 | 581 | |
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582 | 582 | gpio_g: gpio@660a0000 { |
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.. | .. |
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687 | 687 | }; |
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688 | 688 | }; |
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689 | 689 | |
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690 | | - sata: ahci@663f2000 { |
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| 690 | + sata: sata@663f2000 { |
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691 | 691 | compatible = "brcm,iproc-ahci", "generic-ahci"; |
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692 | 692 | reg = <0x663f2000 0x1000>; |
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693 | 693 | dma-coherent; |
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