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2023-12-11 1f93a7dfd1f8d5ff7a5c53246c7534fe2332d6f4

 kernel/arch/arm/mm/proc-arm1026.S
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+/* SPDX-License-Identifier: GPL-2.0-or-later */
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 /*
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  *  linux/arch/arm/mm/proc-arm1026.S: MMU functions for ARM1026EJ-S
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  *
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@@ -5,22 +6,16 @@
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  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
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  *  hacked for non-paged-MM by Hyok S. Choi, 2003.
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  *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; either version 2 of the License, or
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- * (at your option) any later version.
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- *
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- *
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  * These are the low level assembler for performing cache and TLB
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  * functions on the ARM1026EJ-S.
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  */
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 #include <linux/linkage.h>
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 #include <linux/init.h>
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+#include <linux/pgtable.h>
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 #include <asm/assembler.h>
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 #include <asm/asm-offsets.h>
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 #include <asm/hwcap.h>
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 #include <asm/pgtable-hwdef.h>
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-#include <asm/pgtable.h>
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 #include <asm/ptrace.h>
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 #include "proc-macros.S"
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 	mov	ip, #0
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 __flush_whole_cache:
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 #ifndef CONFIG_CPU_DCACHE_DISABLE
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-1:	mrc	p15, 0, r15, c7, c14, 3		@ test, clean, invalidate
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+1:	mrc	p15, 0, APSR_nzcv, c7, c14, 3		@ test, clean, invalidate
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 	bne	1b
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 #endif
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 	tst	r2, #VM_EXEC
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@@ -368,7 +363,7 @@
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 #ifdef CONFIG_MMU
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 	mov	r1, #0
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 #ifndef CONFIG_CPU_DCACHE_DISABLE
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-1:	mrc	p15, 0, r15, c7, c14, 3		@ test, clean, invalidate
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+1:	mrc	p15, 0, APSR_nzcv, c7, c14, 3		@ test, clean, invalidate
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 	bne	1b
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 #endif
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 #ifndef CONFIG_CPU_ICACHE_DISABLE
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@@ -442,7 +437,7 @@
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 	string	cpu_arm1026_name, "ARM1026EJ-S"
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 	.align
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-	.section ".proc.info.init", #alloc
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+	.section ".proc.info.init", "a"
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 	.type	__arm1026_proc_info,#object
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 __arm1026_proc_info: