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2023-12-11 1f93a7dfd1f8d5ff7a5c53246c7534fe2332d6f4

 kernel/arch/arm/mm/cache-v7m.S
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@@ -1,3 +1,4 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  *  linux/arch/arm/mm/cache-v7m.S
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  *
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  *
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  *  Copyright (C) 2001 Deep Blue Solutions Ltd.
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  *  Copyright (C) 2005 ARM Ltd.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  *
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  *  This is the "shell" of the ARMv7M processor support.
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  */
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@@ -186,13 +183,13 @@
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 	and	r1, r1, #7			@ mask of the bits for current cache only
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 	cmp	r1, #2				@ see what cache we have at this level
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 	blt	skip				@ skip if no cache, or just i-cache
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-#ifdef CONFIG_PREEMPT
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+#ifdef CONFIG_PREEMPTION
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 	save_and_disable_irqs_notrace r9	@ make cssr&csidr read atomic
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 #endif
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 	write_csselr r10, r1			@ set current cache level
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 	isb					@ isb to sych the new cssr&csidr
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 	read_ccsidr r1				@ read the new csidr
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-#ifdef CONFIG_PREEMPT
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+#ifdef CONFIG_PREEMPTION
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 	restore_irqs_notrace r9
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 #endif
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 	and	r2, r1, #7			@ extract the length of the cache lines