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2023-12-11 1f93a7dfd1f8d5ff7a5c53246c7534fe2332d6f4

 kernel/arch/arm/mach-mmp/time.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * linux/arch/arm/mach-mmp/time.c
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  *
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@@ -12,16 +13,13 @@
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  * The timers module actually includes three timers, each timer with up to
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  * three match comparators. Timer #0 is used here in free-running mode as
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  * the clock source, and match comparator #1 used as clock event device.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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 #include <linux/init.h>
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 #include <linux/kernel.h>
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 #include <linux/interrupt.h>
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 #include <linux/clockchips.h>
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+#include <linux/clk.h>
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 #include <linux/io.h>
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 #include <linux/irq.h>
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@@ -35,14 +33,7 @@
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 #include "regs-timers.h"
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 #include "regs-apbc.h"
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 #include "irqs.h"
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-#include "cputype.h"
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-#include "clock.h"
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-
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-#ifdef CONFIG_CPU_MMP2
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-#define MMP_CLOCK_FREQ		6500000
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-#else
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-#define MMP_CLOCK_FREQ		3250000
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-#endif
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+#include <linux/soc/mmp/cputype.h>
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37
 
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 #define TIMERS_VIRT_BASE	TIMERS1_VIRT_BASE
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@@ -163,7 +154,8 @@
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 	__raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */
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156
 
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-	ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
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+	ccr &= (cpu_is_mmp2() || cpu_is_mmp3()) ?
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+		(TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
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 		(TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
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 	__raw_writel(ccr, mmp_timer_base + TMR_CCR);
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@@ -182,58 +174,50 @@
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 	__raw_writel(0x2, mmp_timer_base + TMR_CER);
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 }
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-static struct irqaction timer_irq = {
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-	.name		= "timer",
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-	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
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-	.handler	= timer_interrupt,
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-	.dev_id		= &ckevt,
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-};
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-
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-void __init timer_init(int irq)
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+void __init mmp_timer_init(int irq, unsigned long rate)
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 {
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 	timer_config();
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-	sched_clock_register(mmp_read_sched_clock, 32, MMP_CLOCK_FREQ);
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+	sched_clock_register(mmp_read_sched_clock, 32, rate);
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 	ckevt.cpumask = cpumask_of(0);
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184
 
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-	setup_irq(irq, &timer_irq);
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+	if (request_irq(irq, timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
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+			"timer", &ckevt))
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+		pr_err("Failed to request irq %d (timer)\n", irq);
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-	clocksource_register_hz(&cksrc, MMP_CLOCK_FREQ);
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-	clockevents_config_and_register(&ckevt, MMP_CLOCK_FREQ,
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-					MIN_DELTA, MAX_DELTA);
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+	clocksource_register_hz(&cksrc, rate);
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+	clockevents_config_and_register(&ckevt, rate, MIN_DELTA, MAX_DELTA);
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 }
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192
 
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-#ifdef CONFIG_OF
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-static const struct of_device_id mmp_timer_dt_ids[] = {
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-	{ .compatible = "mrvl,mmp-timer", },
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-	{}
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-};
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-
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-void __init mmp_dt_init_timer(void)
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+static int __init mmp_dt_init_timer(struct device_node *np)
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 {
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-	struct device_node *np;
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+	struct clk *clk;
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 	int irq, ret;
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+	unsigned long rate;
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-	np = of_find_matching_node(NULL, mmp_timer_dt_ids);
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-	if (!np) {
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-		ret = -ENODEV;
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-		goto out;
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+	clk = of_clk_get(np, 0);
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+	if (!IS_ERR(clk)) {
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+		ret = clk_prepare_enable(clk);
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+		if (ret)
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+			return ret;
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+		rate = clk_get_rate(clk);
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+	} else if (cpu_is_pj4()) {
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+		rate = 6500000;
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+	} else {
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+		rate = 3250000;
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 	}
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 	irq = irq_of_parse_and_map(np, 0);
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-	if (!irq) {
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-		ret = -EINVAL;
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-		goto out;
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-	}
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+	if (!irq)
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+		return -EINVAL;
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+
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 	mmp_timer_base = of_iomap(np, 0);
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-	if (!mmp_timer_base) {
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-		ret = -ENOMEM;
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-		goto out;
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-	}
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-	timer_init(irq);
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-	return;
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-out:
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-	pr_err("Failed to get timer from device tree with error:%d\n", ret);
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+	if (!mmp_timer_base)
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+		return -ENOMEM;
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+
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+	mmp_timer_init(irq, rate);
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+	return 0;
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 }
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-#endif
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+
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+TIMER_OF_DECLARE(mmp_timer, "mrvl,mmp-timer", mmp_dt_init_timer);