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2023-12-11 1f93a7dfd1f8d5ff7a5c53246c7534fe2332d6f4

 kernel/arch/arm/boot/dts/at91sam9n12.dtsi
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@@ -1,13 +1,11 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
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  *
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  *  Copyright (C) 2012 Atmel,
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  *                2012 Hong Xu <hong.xu@atmel.com>
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- *
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- * Licensed under GPLv2 or later.
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  */
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8
 
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-#include "skeleton.dtsi"
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 #include <dt-bindings/dma/at91.h>
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10
 #include <dt-bindings/pinctrl/at91.h>
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11
 #include <dt-bindings/interrupt-controller/irq.h>
..
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@@ -15,6 +13,8 @@
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 #include <dt-bindings/clock/at91.h>
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14
 
17
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 / {
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+	#address-cells = <1>;
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+	#size-cells = <1>;
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18
 	model = "Atmel AT91SAM9N12 SoC";
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19
 	compatible = "atmel,at91sam9n12";
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20
 	interrupt-parent = <&aic>;
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@@ -37,16 +37,18 @@
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37
 		pwm0 = &pwm0;
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38
 	};
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 	cpus {
40
-		#address-cells = <0>;
40
+		#address-cells = <1>;
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41
 		#size-cells = <0>;
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42
 
43
-		cpu {
43
+		cpu@0 {
44
44
 			compatible = "arm,arm926ej-s";
45
45
 			device_type = "cpu";
46
+			reg = <0>;
46
47
 		};
47
48
 	};
48
49
 
49
-	memory {
50
+	memory@20000000 {
51
+		device_type = "memory";
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52
 		reg = <0x20000000 0x10000000>;
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53
 	};
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54
 
..
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@@ -67,6 +69,9 @@
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 	sram: sram@300000 {
68
70
 		compatible = "mmio-sram";
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71
 		reg = <0x00300000 0x8000>;
72
+		#address-cells = <1>;
73
+		#size-cells = <1>;
74
+		ranges = <0 0x00300000 0x8000>;
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75
 	};
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76
 
72
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 	ahb {
..
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@@ -103,7 +108,7 @@
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 			ramc0: ramc@ffffe800 {
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 				compatible = "atmel,at91sam9g45-ddramc";
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 				reg = <0xffffe800 0x200>;
106
-				clocks = <&ddrck>;
111
+				clocks = <&pmc PMC_TYPE_SYSTEM 2>;
107
112
 				clock-names = "ddrck";
108
113
 			};
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114
 
..
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@@ -115,278 +120,10 @@
115
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 			pmc: pmc@fffffc00 {
116
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 				compatible = "atmel,at91sam9n12-pmc", "syscon";
117
122
 				reg = <0xfffffc00 0x200>;
123
+				#clock-cells = <2>;
124
+				clocks = <&clk32k>, <&main_xtal>;
125
+				clock-names = "slow_clk", "main_xtal";
118
126
 				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
119
-				interrupt-controller;
120
-				#address-cells = <1>;
121
-				#size-cells = <0>;
122
-				#interrupt-cells = <1>;
123
-
124
-				main_rc_osc: main_rc_osc {
125
-					compatible = "atmel,at91sam9x5-clk-main-rc-osc";
126
-					#clock-cells = <0>;
127
-					interrupts-extended = <&pmc AT91_PMC_MOSCRCS>;
128
-					clock-frequency = <12000000>;
129
-					clock-accuracy = <50000000>;
130
-				};
131
-
132
-				main_osc: main_osc {
133
-					compatible = "atmel,at91rm9200-clk-main-osc";
134
-					#clock-cells = <0>;
135
-					interrupts-extended = <&pmc AT91_PMC_MOSCS>;
136
-					clocks = <&main_xtal>;
137
-				};
138
-
139
-				main: mainck {
140
-					compatible = "atmel,at91sam9x5-clk-main";
141
-					#clock-cells = <0>;
142
-					interrupts-extended = <&pmc AT91_PMC_MOSCSELS>;
143
-					clocks = <&main_rc_osc>, <&main_osc>;
144
-				};
145
-
146
-				plla: pllack {
147
-					compatible = "atmel,at91rm9200-clk-pll";
148
-					#clock-cells = <0>;
149
-					interrupts-extended = <&pmc AT91_PMC_LOCKA>;
150
-					clocks = <&main>;
151
-					reg = <0>;
152
-					atmel,clk-input-range = <2000000 32000000>;
153
-					#atmel,pll-clk-output-range-cells = <4>;
154
-					atmel,pll-clk-output-ranges = <745000000 800000000 0 0>,
155
-								      <695000000 750000000 1 0>,
156
-								      <645000000 700000000 2 0>,
157
-								      <595000000 650000000 3 0>,
158
-								      <545000000 600000000 0 1>,
159
-								      <495000000 555000000 1 1>,
160
-								      <445000000 500000000 2 1>,
161
-								      <400000000 450000000 3 1>;
162
-				};
163
-
164
-				plladiv: plladivck {
165
-					compatible = "atmel,at91sam9x5-clk-plldiv";
166
-					#clock-cells = <0>;
167
-					clocks = <&plla>;
168
-				};
169
-
170
-				pllb: pllbck {
171
-					compatible = "atmel,at91rm9200-clk-pll";
172
-					#clock-cells = <0>;
173
-					interrupts-extended = <&pmc AT91_PMC_LOCKB>;
174
-					clocks = <&main>;
175
-					reg = <1>;
176
-					atmel,clk-input-range = <2000000 32000000>;
177
-					#atmel,pll-clk-output-range-cells = <3>;
178
-					atmel,pll-clk-output-ranges = <30000000 100000000 0>;
179
-				};
180
-
181
-				mck: masterck {
182
-					compatible = "atmel,at91sam9x5-clk-master";
183
-					#clock-cells = <0>;
184
-					interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
185
-					clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>;
186
-					atmel,clk-output-range = <0 133333333>;
187
-					atmel,clk-divisors = <1 2 4 3>;
188
-					atmel,master-clk-have-div3-pres;
189
-				};
190
-
191
-				usb: usbck {
192
-					compatible = "atmel,at91sam9n12-clk-usb";
193
-					#clock-cells = <0>;
194
-					clocks = <&pllb>;
195
-				};
196
-
197
-				prog: progck {
198
-					compatible = "atmel,at91sam9x5-clk-programmable";
199
-					#address-cells = <1>;
200
-					#size-cells = <0>;
201
-					interrupt-parent = <&pmc>;
202
-					clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>, <&mck>;
203
-
204
-					prog0: prog0 {
205
-						#clock-cells = <0>;
206
-						reg = <0>;
207
-						interrupts = <AT91_PMC_PCKRDY(0)>;
208
-					};
209
-
210
-					prog1: prog1 {
211
-						#clock-cells = <0>;
212
-						reg = <1>;
213
-						interrupts = <AT91_PMC_PCKRDY(1)>;
214
-					};
215
-				};
216
-
217
-				systemck {
218
-					compatible = "atmel,at91rm9200-clk-system";
219
-					#address-cells = <1>;
220
-					#size-cells = <0>;
221
-
222
-					ddrck: ddrck {
223
-						#clock-cells = <0>;
224
-						reg = <2>;
225
-						clocks = <&mck>;
226
-					};
227
-
228
-					lcdck: lcdck {
229
-						#clock-cells = <0>;
230
-						reg = <3>;
231
-						clocks = <&mck>;
232
-					};
233
-
234
-					uhpck: uhpck {
235
-						#clock-cells = <0>;
236
-						reg = <6>;
237
-						clocks = <&usb>;
238
-					};
239
-
240
-					udpck: udpck {
241
-						#clock-cells = <0>;
242
-						reg = <7>;
243
-						clocks = <&usb>;
244
-					};
245
-
246
-					pck0: pck0 {
247
-						#clock-cells = <0>;
248
-						reg = <8>;
249
-						clocks = <&prog0>;
250
-					};
251
-
252
-					pck1: pck1 {
253
-						#clock-cells = <0>;
254
-						reg = <9>;
255
-						clocks = <&prog1>;
256
-					};
257
-				};
258
-
259
-				periphck {
260
-					compatible = "atmel,at91sam9x5-clk-peripheral";
261
-					#address-cells = <1>;
262
-					#size-cells = <0>;
263
-					clocks = <&mck>;
264
-
265
-					pioAB_clk: pioAB_clk {
266
-						#clock-cells = <0>;
267
-						reg = <2>;
268
-					};
269
-
270
-					pioCD_clk: pioCD_clk {
271
-						#clock-cells = <0>;
272
-						reg = <3>;
273
-					};
274
-
275
-					fuse_clk: fuse_clk {
276
-						#clock-cells = <0>;
277
-						reg = <4>;
278
-					};
279
-
280
-					usart0_clk: usart0_clk {
281
-						#clock-cells = <0>;
282
-						reg = <5>;
283
-					};
284
-
285
-					usart1_clk: usart1_clk {
286
-						#clock-cells = <0>;
287
-						reg = <6>;
288
-					};
289
-
290
-					usart2_clk: usart2_clk {
291
-						#clock-cells = <0>;
292
-						reg = <7>;
293
-					};
294
-
295
-					usart3_clk: usart3_clk {
296
-						#clock-cells = <0>;
297
-						reg = <8>;
298
-					};
299
-
300
-					twi0_clk: twi0_clk {
301
-						reg = <9>;
302
-						#clock-cells = <0>;
303
-					};
304
-
305
-					twi1_clk: twi1_clk {
306
-						#clock-cells = <0>;
307
-						reg = <10>;
308
-					};
309
-
310
-					mci0_clk: mci0_clk {
311
-						#clock-cells = <0>;
312
-						reg = <12>;
313
-					};
314
-
315
-					spi0_clk: spi0_clk {
316
-						#clock-cells = <0>;
317
-						reg = <13>;
318
-					};
319
-
320
-					spi1_clk: spi1_clk {
321
-						#clock-cells = <0>;
322
-						reg = <14>;
323
-					};
324
-
325
-					uart0_clk: uart0_clk {
326
-						#clock-cells = <0>;
327
-						reg = <15>;
328
-					};
329
-
330
-					uart1_clk: uart1_clk {
331
-						#clock-cells = <0>;
332
-						reg = <16>;
333
-					};
334
-
335
-					tcb_clk: tcb_clk {
336
-						#clock-cells = <0>;
337
-						reg = <17>;
338
-					};
339
-
340
-					pwm_clk: pwm_clk {
341
-						#clock-cells = <0>;
342
-						reg = <18>;
343
-					};
344
-
345
-					adc_clk: adc_clk {
346
-						#clock-cells = <0>;
347
-						reg = <19>;
348
-					};
349
-
350
-					dma0_clk: dma0_clk {
351
-						#clock-cells = <0>;
352
-						reg = <20>;
353
-					};
354
-
355
-					uhphs_clk: uhphs_clk {
356
-						#clock-cells = <0>;
357
-						reg = <22>;
358
-					};
359
-
360
-					udphs_clk: udphs_clk {
361
-						#clock-cells = <0>;
362
-						reg = <23>;
363
-					};
364
-
365
-					lcdc_clk: lcdc_clk {
366
-						#clock-cells = <0>;
367
-						reg = <25>;
368
-					};
369
-
370
-					sha_clk: sha_clk {
371
-						#clock-cells = <0>;
372
-						reg = <27>;
373
-					};
374
-
375
-					ssc0_clk: ssc0_clk {
376
-						#clock-cells = <0>;
377
-						reg = <28>;
378
-					};
379
-
380
-					aes_clk: aes_clk {
381
-						#clock-cells = <0>;
382
-						reg = <29>;
383
-					};
384
-
385
-					trng_clk: trng_clk {
386
-						#clock-cells = <0>;
387
-						reg = <30>;
388
-					};
389
-				};
390
127
 			};
391
128
 
392
129
 			rstc@fffffe00 {
..
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@@ -399,7 +136,7 @@
399
136
 				compatible = "atmel,at91sam9260-pit";
400
137
 				reg = <0xfffffe30 0xf>;
401
138
 				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
402
-				clocks = <&mck>;
139
+				clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
403
140
 			};
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 			shdwc@fffffe10 {
..
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@@ -438,7 +175,7 @@
438
175
 				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
439
176
 				dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
440
177
 				dma-names = "rxtx";
441
-				clocks = <&mci0_clk>;
178
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
442
179
 				clock-names = "mci_clk";
443
180
 				#address-cells = <1>;
444
181
 				#size-cells = <0>;
..
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@@ -451,7 +188,7 @@
451
188
 				#size-cells = <0>;
452
189
 				reg = <0xf8008000 0x100>;
453
190
 				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
454
-				clocks = <&tcb_clk>, <&clk32k>;
191
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>;
455
192
 				clock-names = "t0_clk", "slow_clk";
456
193
 			};
457
194
 
..
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@@ -461,7 +198,7 @@
461
198
 				#size-cells = <0>;
462
199
 				reg = <0xf800c000 0x100>;
463
200
 				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
464
-				clocks = <&tcb_clk>, <&clk32k>;
201
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>;
465
202
 				clock-names = "t0_clk", "slow_clk";
466
203
 			};
467
204
 
..
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@@ -469,7 +206,7 @@
469
206
 				compatible = "atmel,at91sam9n12-hlcdc";
470
207
 				reg = <0xf8038000 0x2000>;
471
208
 				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
472
-				clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
209
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
473
210
 				clock-names = "periph_clk", "sys_clk", "slow_clk";
474
211
 				status = "disabled";
475
212
 
..
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@@ -498,7 +235,7 @@
498
235
 				reg = <0xffffec00 0x200>;
499
236
 				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
500
237
 				#dma-cells = <2>;
501
-				clocks = <&dma0_clk>;
238
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
502
239
 				clock-names = "dma_clk";
503
240
 			};
504
241
 
..
..
@@ -816,7 +553,7 @@
816
553
 					gpio-controller;
817
554
 					interrupt-controller;
818
555
 					#interrupt-cells = <2>;
819
-					clocks = <&pioAB_clk>;
556
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
820
557
 				};
821
558
 
822
559
 				pioB: gpio@fffff600 {
..
..
@@ -827,7 +564,7 @@
827
564
 					gpio-controller;
828
565
 					interrupt-controller;
829
566
 					#interrupt-cells = <2>;
830
-					clocks = <&pioAB_clk>;
567
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
831
568
 				};
832
569
 
833
570
 				pioC: gpio@fffff800 {
..
..
@@ -838,7 +575,7 @@
838
575
 					gpio-controller;
839
576
 					interrupt-controller;
840
577
 					#interrupt-cells = <2>;
841
-					clocks = <&pioCD_clk>;
578
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
842
579
 				};
843
580
 
844
581
 				pioD: gpio@fffffa00 {
..
..
@@ -849,7 +586,7 @@
849
586
 					gpio-controller;
850
587
 					interrupt-controller;
851
588
 					#interrupt-cells = <2>;
852
-					clocks = <&pioCD_clk>;
589
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
853
590
 				};
854
591
 			};
855
592
 
..
..
@@ -859,7 +596,7 @@
859
596
 				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
860
597
 				pinctrl-names = "default";
861
598
 				pinctrl-0 = <&pinctrl_dbgu>;
862
-				clocks = <&mck>;
599
+				clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
863
600
 				clock-names = "usart";
864
601
 				status = "disabled";
865
602
 			};
..
..
@@ -873,7 +610,7 @@
873
610
 				dma-names = "tx", "rx";
874
611
 				pinctrl-names = "default";
875
612
 				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
876
-				clocks = <&ssc0_clk>;
613
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
877
614
 				clock-names = "pclk";
878
615
 				status = "disabled";
879
616
 			};
..
..
@@ -884,7 +621,7 @@
884
621
 				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
885
622
 				pinctrl-names = "default";
886
623
 				pinctrl-0 = <&pinctrl_usart0>;
887
-				clocks = <&usart0_clk>;
624
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
888
625
 				clock-names = "usart";
889
626
 				status = "disabled";
890
627
 			};
..
..
@@ -895,7 +632,7 @@
895
632
 				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
896
633
 				pinctrl-names = "default";
897
634
 				pinctrl-0 = <&pinctrl_usart1>;
898
-				clocks = <&usart1_clk>;
635
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
899
636
 				clock-names = "usart";
900
637
 				status = "disabled";
901
638
 			};
..
..
@@ -906,7 +643,7 @@
906
643
 				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
907
644
 				pinctrl-names = "default";
908
645
 				pinctrl-0 = <&pinctrl_usart2>;
909
-				clocks = <&usart2_clk>;
646
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
910
647
 				clock-names = "usart";
911
648
 				status = "disabled";
912
649
 			};
..
..
@@ -917,7 +654,7 @@
917
654
 				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
918
655
 				pinctrl-names = "default";
919
656
 				pinctrl-0 = <&pinctrl_usart3>;
920
-				clocks = <&usart3_clk>;
657
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
921
658
 				clock-names = "usart";
922
659
 				status = "disabled";
923
660
 			};
..
..
@@ -933,7 +670,7 @@
933
670
 				#size-cells = <0>;
934
671
 				pinctrl-names = "default";
935
672
 				pinctrl-0 = <&pinctrl_i2c0>;
936
-				clocks = <&twi0_clk>;
673
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
937
674
 				status = "disabled";
938
675
 			};
939
676
 
..
..
@@ -948,7 +685,7 @@
948
685
 				#size-cells = <0>;
949
686
 				pinctrl-names = "default";
950
687
 				pinctrl-0 = <&pinctrl_i2c1>;
951
-				clocks = <&twi1_clk>;
688
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
952
689
 				status = "disabled";
953
690
 			};
954
691
 
..
..
@@ -963,7 +700,7 @@
963
700
 				dma-names = "tx", "rx";
964
701
 				pinctrl-names = "default";
965
702
 				pinctrl-0 = <&pinctrl_spi0>;
966
-				clocks = <&spi0_clk>;
703
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
967
704
 				clock-names = "spi_clk";
968
705
 				status = "disabled";
969
706
 			};
..
..
@@ -979,7 +716,7 @@
979
716
 				dma-names = "tx", "rx";
980
717
 				pinctrl-names = "default";
981
718
 				pinctrl-0 = <&pinctrl_spi1>;
982
-				clocks = <&spi1_clk>;
719
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
983
720
 				clock-names = "spi_clk";
984
721
 				status = "disabled";
985
722
 			};
..
..
@@ -1008,7 +745,7 @@
1008
745
 				reg = <0xf8034000 0x300>;
1009
746
 				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
1010
747
 				#pwm-cells = <3>;
1011
-				clocks = <&pwm_clk>;
748
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
1012
749
 				status = "disabled";
1013
750
 			};
1014
751
 
..
..
@@ -1016,7 +753,7 @@
1016
753
 				compatible = "atmel,at91sam9260-udc";
1017
754
 				reg = <0xf803c000 0x4000>;
1018
755
 				interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
1019
-				clocks = <&udphs_clk>, <&udpck>;
756
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_SYSTEM 7>;
1020
757
 				clock-names = "pclk", "hclk";
1021
758
 				status = "disabled";
1022
759
 			};
..
..
@@ -1026,7 +763,7 @@
1026
763
 			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1027
764
 			reg = <0x00500000 0x00100000>;
1028
765
 			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1029
-			clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
766
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
1030
767
 			clock-names = "ohci_clk", "hclk", "uhpck";
1031
768
 			status = "disabled";
1032
769
 		};
..
..
@@ -1044,7 +781,7 @@
1044
781
 				  0x3 0x0 0x40000000 0x10000000
1045
782
 				  0x4 0x0 0x50000000 0x10000000
1046
783
 				  0x5 0x0 0x60000000 0x10000000>;
1047
-			clocks = <&mck>;
784
+			clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
1048
785
 			status = "disabled";
1049
786
 
1050
787
 			nand_controller: nand-controller {