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2024-02-19 1c055e55a242a33e574e48be530e06770a210dcd 
 kernel/include/dt-bindings/clock/jz4780-cgu.h
....@@ -12,78 +12,80 @@
1212 #ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__
1313 #define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__
1414 
15
-#define JZ4780_CLK_EXCLK	0
16
-#define JZ4780_CLK_RTCLK	1
17
-#define JZ4780_CLK_APLL		2
18
-#define JZ4780_CLK_MPLL		3
19
-#define JZ4780_CLK_EPLL		4
20
-#define JZ4780_CLK_VPLL		5
21
-#define JZ4780_CLK_OTGPHY	6
22
-#define JZ4780_CLK_SCLKA	7
23
-#define JZ4780_CLK_CPUMUX	8
24
-#define JZ4780_CLK_CPU		9
25
-#define JZ4780_CLK_L2CACHE	10
26
-#define JZ4780_CLK_AHB0		11
27
-#define JZ4780_CLK_AHB2PMUX	12
28
-#define JZ4780_CLK_AHB2		13
29
-#define JZ4780_CLK_PCLK		14
30
-#define JZ4780_CLK_DDR		15
31
-#define JZ4780_CLK_VPU		16
32
-#define JZ4780_CLK_I2SPLL	17
33
-#define JZ4780_CLK_I2S		18
15
+#define JZ4780_CLK_EXCLK		0
16
+#define JZ4780_CLK_RTCLK		1
17
+#define JZ4780_CLK_APLL			2
18
+#define JZ4780_CLK_MPLL			3
19
+#define JZ4780_CLK_EPLL			4
20
+#define JZ4780_CLK_VPLL			5
21
+#define JZ4780_CLK_OTGPHY		6
22
+#define JZ4780_CLK_SCLKA		7
23
+#define JZ4780_CLK_CPUMUX		8
24
+#define JZ4780_CLK_CPU			9
25
+#define JZ4780_CLK_L2CACHE		10
26
+#define JZ4780_CLK_AHB0			11
27
+#define JZ4780_CLK_AHB2PMUX		12
28
+#define JZ4780_CLK_AHB2			13
29
+#define JZ4780_CLK_PCLK			14
30
+#define JZ4780_CLK_DDR			15
31
+#define JZ4780_CLK_VPU			16
32
+#define JZ4780_CLK_I2SPLL		17
33
+#define JZ4780_CLK_I2S			18
3434 #define JZ4780_CLK_LCD0PIXCLK	19
3535 #define JZ4780_CLK_LCD1PIXCLK	20
36
-#define JZ4780_CLK_MSCMUX	21
37
-#define JZ4780_CLK_MSC0		22
38
-#define JZ4780_CLK_MSC1		23
39
-#define JZ4780_CLK_MSC2		24
40
-#define JZ4780_CLK_UHC		25
41
-#define JZ4780_CLK_SSIPLL	26
42
-#define JZ4780_CLK_SSI		27
43
-#define JZ4780_CLK_CIMMCLK	28
44
-#define JZ4780_CLK_PCMPLL	29
45
-#define JZ4780_CLK_PCM		30
46
-#define JZ4780_CLK_GPU		31
47
-#define JZ4780_CLK_HDMI		32
48
-#define JZ4780_CLK_BCH		33
49
-#define JZ4780_CLK_NEMC		34
50
-#define JZ4780_CLK_OTG0		35
51
-#define JZ4780_CLK_SSI0		36
52
-#define JZ4780_CLK_SMB0		37
53
-#define JZ4780_CLK_SMB1		38
54
-#define JZ4780_CLK_SCC		39
55
-#define JZ4780_CLK_AIC		40
56
-#define JZ4780_CLK_TSSI0	41
57
-#define JZ4780_CLK_OWI		42
58
-#define JZ4780_CLK_KBC		43
59
-#define JZ4780_CLK_SADC		44
60
-#define JZ4780_CLK_UART0	45
61
-#define JZ4780_CLK_UART1	46
62
-#define JZ4780_CLK_UART2	47
63
-#define JZ4780_CLK_UART3	48
64
-#define JZ4780_CLK_SSI1		49
65
-#define JZ4780_CLK_SSI2		50
66
-#define JZ4780_CLK_PDMA		51
67
-#define JZ4780_CLK_GPS		52
68
-#define JZ4780_CLK_MAC		53
69
-#define JZ4780_CLK_SMB2		54
70
-#define JZ4780_CLK_CIM		55
71
-#define JZ4780_CLK_LCD		56
72
-#define JZ4780_CLK_TVE		57
73
-#define JZ4780_CLK_IPU		58
74
-#define JZ4780_CLK_DDR0		59
75
-#define JZ4780_CLK_DDR1		60
76
-#define JZ4780_CLK_SMB3		61
77
-#define JZ4780_CLK_TSSI1	62
78
-#define JZ4780_CLK_COMPRESS	63
79
-#define JZ4780_CLK_AIC1		64
80
-#define JZ4780_CLK_GPVLC	65
81
-#define JZ4780_CLK_OTG1		66
82
-#define JZ4780_CLK_UART4	67
83
-#define JZ4780_CLK_AHBMON	68
84
-#define JZ4780_CLK_SMB4		69
85
-#define JZ4780_CLK_DES		70
86
-#define JZ4780_CLK_X2D		71
87
-#define JZ4780_CLK_CORE1	72
36
+#define JZ4780_CLK_MSCMUX		21
37
+#define JZ4780_CLK_MSC0			22
38
+#define JZ4780_CLK_MSC1			23
39
+#define JZ4780_CLK_MSC2			24
40
+#define JZ4780_CLK_UHC			25
41
+#define JZ4780_CLK_SSIPLL		26
42
+#define JZ4780_CLK_SSI			27
43
+#define JZ4780_CLK_CIMMCLK		28
44
+#define JZ4780_CLK_PCMPLL		29
45
+#define JZ4780_CLK_PCM			30
46
+#define JZ4780_CLK_GPU			31
47
+#define JZ4780_CLK_HDMI			32
48
+#define JZ4780_CLK_BCH			33
49
+#define JZ4780_CLK_NEMC			34
50
+#define JZ4780_CLK_OTG0			35
51
+#define JZ4780_CLK_SSI0			36
52
+#define JZ4780_CLK_SMB0			37
53
+#define JZ4780_CLK_SMB1			38
54
+#define JZ4780_CLK_SCC			39
55
+#define JZ4780_CLK_AIC			40
56
+#define JZ4780_CLK_TSSI0		41
57
+#define JZ4780_CLK_OWI			42
58
+#define JZ4780_CLK_KBC			43
59
+#define JZ4780_CLK_SADC			44
60
+#define JZ4780_CLK_UART0		45
61
+#define JZ4780_CLK_UART1		46
62
+#define JZ4780_CLK_UART2		47
63
+#define JZ4780_CLK_UART3		48
64
+#define JZ4780_CLK_SSI1			49
65
+#define JZ4780_CLK_SSI2			50
66
+#define JZ4780_CLK_PDMA			51
67
+#define JZ4780_CLK_GPS			52
68
+#define JZ4780_CLK_MAC			53
69
+#define JZ4780_CLK_SMB2			54
70
+#define JZ4780_CLK_CIM			55
71
+#define JZ4780_CLK_LCD			56
72
+#define JZ4780_CLK_TVE			57
73
+#define JZ4780_CLK_IPU			58
74
+#define JZ4780_CLK_DDR0			59
75
+#define JZ4780_CLK_DDR1			60
76
+#define JZ4780_CLK_SMB3			61
77
+#define JZ4780_CLK_TSSI1		62
78
+#define JZ4780_CLK_COMPRESS		63
79
+#define JZ4780_CLK_AIC1			64
80
+#define JZ4780_CLK_GPVLC		65
81
+#define JZ4780_CLK_OTG1			66
82
+#define JZ4780_CLK_UART4		67
83
+#define JZ4780_CLK_AHBMON		68
84
+#define JZ4780_CLK_SMB4			69
85
+#define JZ4780_CLK_DES			70
86
+#define JZ4780_CLK_X2D			71
87
+#define JZ4780_CLK_CORE1		72
88
+#define JZ4780_CLK_EXCLK_DIV512	73
89
+#define JZ4780_CLK_RTC			74
8890 
8991 #endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */