~hc/RK356X_SDK_RELEASE.git

..	..	@@ -9,54 +9,55 @@
9	9	* Venu Byravarasu <vbyravarasu@nvidia.com>
10	10	*/
11	11
12		-#include <linux/resource.h>
13	12	#include <linux/delay.h>
14		-#include <linux/slab.h>
15	13	#include <linux/err.h>
16	14	#include <linux/export.h>
17		-#include <linux/module.h>
18		-#include <linux/platform_device.h>
	15	+#include <linux/gpio/consumer.h>
19	16	#include <linux/iopoll.h>
20		-#include <linux/gpio.h>
	17	+#include <linux/module.h>
21	18	#include <linux/of.h>
22	19	#include <linux/of_device.h>
23		-#include <linux/of_gpio.h>
24		-#include <linux/usb/otg.h>
25		-#include <linux/usb/ulpi.h>
26		-#include <linux/usb/of.h>
27		-#include <linux/usb/ehci_def.h>
28		-#include <linux/usb/tegra_usb_phy.h>
	20	+#include <linux/platform_device.h>
	21	+#include <linux/resource.h>
	22	+#include <linux/slab.h>
	23	+#include <linux/spinlock.h>
	24	+
29	25	#include <linux/regulator/consumer.h>
30	26
31		-#define ULPI_VIEWPORT 0x170
	27	+#include <linux/usb/ehci_def.h>
	28	+#include <linux/usb/of.h>
	29	+#include <linux/usb/tegra_usb_phy.h>
	30	+#include <linux/usb/ulpi.h>
	31	+
	32	+#define ULPI_VIEWPORT 0x170
32	33
33	34	/* PORTSC PTS/PHCD bits, Tegra20 only */
34		-#define TEGRA_USB_PORTSC1 0x184
35		-#define TEGRA_USB_PORTSC1_PTS(x) (((x) & 0x3) << 30)
36		-#define TEGRA_USB_PORTSC1_PHCD (1 << 23)
	35	+#define TEGRA_USB_PORTSC1 0x184
	36	+#define TEGRA_USB_PORTSC1_PTS(x) (((x) & 0x3) << 30)
	37	+#define TEGRA_USB_PORTSC1_PHCD BIT(23)
37	38
38	39	/* HOSTPC1 PTS/PHCD bits, Tegra30 and above */
39		-#define TEGRA_USB_HOSTPC1_DEVLC 0x1b4
40		-#define TEGRA_USB_HOSTPC1_DEVLC_PTS(x) (((x) & 0x7) << 29)
41		-#define TEGRA_USB_HOSTPC1_DEVLC_PHCD (1 << 22)
	40	+#define TEGRA_USB_HOSTPC1_DEVLC 0x1b4
	41	+#define TEGRA_USB_HOSTPC1_DEVLC_PTS(x) (((x) & 0x7) << 29)
	42	+#define TEGRA_USB_HOSTPC1_DEVLC_PHCD BIT(22)
42	43
43	44	/* Bits of PORTSC1, which will get cleared by writing 1 into them */
44	45	#define TEGRA_PORTSC1_RWC_BITS (PORT_CSC \| PORT_PEC \| PORT_OCC)
45	46
46		-#define USB_SUSP_CTRL 0x400
47		-#define USB_WAKE_ON_CNNT_EN_DEV (1 << 3)
48		-#define USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
49		-#define USB_SUSP_CLR (1 << 5)
50		-#define USB_PHY_CLK_VALID (1 << 7)
51		-#define UTMIP_RESET (1 << 11)
52		-#define UHSIC_RESET (1 << 11)
53		-#define UTMIP_PHY_ENABLE (1 << 12)
54		-#define ULPI_PHY_ENABLE (1 << 13)
55		-#define USB_SUSP_SET (1 << 14)
56		-#define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16)
	47	+#define USB_SUSP_CTRL 0x400
	48	+#define USB_WAKE_ON_CNNT_EN_DEV BIT(3)
	49	+#define USB_WAKE_ON_DISCON_EN_DEV BIT(4)
	50	+#define USB_SUSP_CLR BIT(5)
	51	+#define USB_PHY_CLK_VALID BIT(7)
	52	+#define UTMIP_RESET BIT(11)
	53	+#define UHSIC_RESET BIT(11)
	54	+#define UTMIP_PHY_ENABLE BIT(12)
	55	+#define ULPI_PHY_ENABLE BIT(13)
	56	+#define USB_SUSP_SET BIT(14)
	57	+#define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16)
57	58
58		-#define USB1_LEGACY_CTRL 0x410
59		-#define USB1_NO_LEGACY_MODE (1 << 0)
	59	+#define USB1_LEGACY_CTRL 0x410
	60	+#define USB1_NO_LEGACY_MODE BIT(0)
60	61	#define USB1_VBUS_SENSE_CTL_MASK (3 << 1)
61	62	#define USB1_VBUS_SENSE_CTL_VBUS_WAKEUP (0 << 1)
62	63	#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
..	..	@@ -64,94 +65,94 @@
64	65	#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD (2 << 1)
65	66	#define USB1_VBUS_SENSE_CTL_A_SESS_VLD (3 << 1)
66	67
67		-#define ULPI_TIMING_CTRL_0 0x424
68		-#define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
69		-#define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
	68	+#define ULPI_TIMING_CTRL_0 0x424
	69	+#define ULPI_OUTPUT_PINMUX_BYP BIT(10)
	70	+#define ULPI_CLKOUT_PINMUX_BYP BIT(11)
70	71
71		-#define ULPI_TIMING_CTRL_1 0x428
72		-#define ULPI_DATA_TRIMMER_LOAD (1 << 0)
73		-#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
74		-#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
75		-#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
76		-#define ULPI_DIR_TRIMMER_LOAD (1 << 24)
77		-#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
	72	+#define ULPI_TIMING_CTRL_1 0x428
	73	+#define ULPI_DATA_TRIMMER_LOAD BIT(0)
	74	+#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
	75	+#define ULPI_STPDIRNXT_TRIMMER_LOAD BIT(16)
	76	+#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
	77	+#define ULPI_DIR_TRIMMER_LOAD BIT(24)
	78	+#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
78	79
79		-#define UTMIP_PLL_CFG1 0x804
	80	+#define UTMIP_PLL_CFG1 0x804
80	81	#define UTMIP_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
81	82	#define UTMIP_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
82	83
83		-#define UTMIP_XCVR_CFG0 0x808
	84	+#define UTMIP_XCVR_CFG0 0x808
84	85	#define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0)
85	86	#define UTMIP_XCVR_SETUP_MSB(x) ((((x) & 0x70) >> 4) << 22)
86	87	#define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8)
87	88	#define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10)
88		-#define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
89		-#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
90		-#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
91		-#define UTMIP_XCVR_LSBIAS_SEL (1 << 21)
	89	+#define UTMIP_FORCE_PD_POWERDOWN BIT(14)
	90	+#define UTMIP_FORCE_PD2_POWERDOWN BIT(16)
	91	+#define UTMIP_FORCE_PDZI_POWERDOWN BIT(18)
	92	+#define UTMIP_XCVR_LSBIAS_SEL BIT(21)
92	93	#define UTMIP_XCVR_HSSLEW(x) (((x) & 0x3) << 4)
93	94	#define UTMIP_XCVR_HSSLEW_MSB(x) ((((x) & 0x1fc) >> 2) << 25)
94	95
95		-#define UTMIP_BIAS_CFG0 0x80c
96		-#define UTMIP_OTGPD (1 << 11)
97		-#define UTMIP_BIASPD (1 << 10)
98		-#define UTMIP_HSSQUELCH_LEVEL(x) (((x) & 0x3) << 0)
99		-#define UTMIP_HSDISCON_LEVEL(x) (((x) & 0x3) << 2)
100		-#define UTMIP_HSDISCON_LEVEL_MSB(x) ((((x) & 0x4) >> 2) << 24)
	96	+#define UTMIP_BIAS_CFG0 0x80c
	97	+#define UTMIP_OTGPD BIT(11)
	98	+#define UTMIP_BIASPD BIT(10)
	99	+#define UTMIP_HSSQUELCH_LEVEL(x) (((x) & 0x3) << 0)
	100	+#define UTMIP_HSDISCON_LEVEL(x) (((x) & 0x3) << 2)
	101	+#define UTMIP_HSDISCON_LEVEL_MSB(x) ((((x) & 0x4) >> 2) << 24)
101	102
102		-#define UTMIP_HSRX_CFG0 0x810
103		-#define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10)
104		-#define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15)
	103	+#define UTMIP_HSRX_CFG0 0x810
	104	+#define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10)
	105	+#define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15)
105	106
106		-#define UTMIP_HSRX_CFG1 0x814
107		-#define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1)
	107	+#define UTMIP_HSRX_CFG1 0x814
	108	+#define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1)
108	109
109		-#define UTMIP_TX_CFG0 0x820
110		-#define UTMIP_FS_PREABMLE_J (1 << 19)
111		-#define UTMIP_HS_DISCON_DISABLE (1 << 8)
	110	+#define UTMIP_TX_CFG0 0x820
	111	+#define UTMIP_FS_PREABMLE_J BIT(19)
	112	+#define UTMIP_HS_DISCON_DISABLE BIT(8)
112	113
113		-#define UTMIP_MISC_CFG0 0x824
114		-#define UTMIP_DPDM_OBSERVE (1 << 26)
115		-#define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
116		-#define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf)
117		-#define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe)
118		-#define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
119		-#define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
120		-#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
	114	+#define UTMIP_MISC_CFG0 0x824
	115	+#define UTMIP_DPDM_OBSERVE BIT(26)
	116	+#define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
	117	+#define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf)
	118	+#define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe)
	119	+#define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
	120	+#define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
	121	+#define UTMIP_SUSPEND_EXIT_ON_EDGE BIT(22)
121	122
122		-#define UTMIP_MISC_CFG1 0x828
123		-#define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
124		-#define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6)
	123	+#define UTMIP_MISC_CFG1 0x828
	124	+#define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
	125	+#define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6)
125	126
126		-#define UTMIP_DEBOUNCE_CFG0 0x82c
127		-#define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0)
	127	+#define UTMIP_DEBOUNCE_CFG0 0x82c
	128	+#define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0)
128	129
129		-#define UTMIP_BAT_CHRG_CFG0 0x830
130		-#define UTMIP_PD_CHRG (1 << 0)
	130	+#define UTMIP_BAT_CHRG_CFG0 0x830
	131	+#define UTMIP_PD_CHRG BIT(0)
131	132
132		-#define UTMIP_SPARE_CFG0 0x834
133		-#define FUSE_SETUP_SEL (1 << 3)
	133	+#define UTMIP_SPARE_CFG0 0x834
	134	+#define FUSE_SETUP_SEL BIT(3)
134	135
135		-#define UTMIP_XCVR_CFG1 0x838
136		-#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
137		-#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
138		-#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
139		-#define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18)
	136	+#define UTMIP_XCVR_CFG1 0x838
	137	+#define UTMIP_FORCE_PDDISC_POWERDOWN BIT(0)
	138	+#define UTMIP_FORCE_PDCHRP_POWERDOWN BIT(2)
	139	+#define UTMIP_FORCE_PDDR_POWERDOWN BIT(4)
	140	+#define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18)
140	141
141		-#define UTMIP_BIAS_CFG1 0x83c
142		-#define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
	142	+#define UTMIP_BIAS_CFG1 0x83c
	143	+#define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
143	144
144	145	/* For Tegra30 and above only, the address is different in Tegra20 */
145		-#define USB_USBMODE 0x1f8
146		-#define USB_USBMODE_MASK (3 << 0)
147		-#define USB_USBMODE_HOST (3 << 0)
148		-#define USB_USBMODE_DEVICE (2 << 0)
	146	+#define USB_USBMODE 0x1f8
	147	+#define USB_USBMODE_MASK (3 << 0)
	148	+#define USB_USBMODE_HOST (3 << 0)
	149	+#define USB_USBMODE_DEVICE (2 << 0)
149	150
150	151	static DEFINE_SPINLOCK(utmip_pad_lock);
151		-static int utmip_pad_count;
	152	+static unsigned int utmip_pad_count;
152	153
153	154	struct tegra_xtal_freq {
154		- int freq;
	155	+ unsigned int freq;
155	156	u8 enable_delay;
156	157	u8 stable_count;
157	158	u8 active_delay;
..	..	@@ -194,66 +195,55 @@
194	195	},
195	196	};
196	197
	198	+static inline struct tegra_usb_phy to_tegra_usb_phy(struct usb_phy u_phy)
	199	+{
	200	+ return container_of(u_phy, struct tegra_usb_phy, u_phy);
	201	+}
	202	+
197	203	static void set_pts(struct tegra_usb_phy *phy, u8 pts_val)
198	204	{
199	205	void __iomem *base = phy->regs;
200		- unsigned long val;
	206	+ u32 val;
201	207
202	208	if (phy->soc_config->has_hostpc) {
203		- val = readl(base + TEGRA_USB_HOSTPC1_DEVLC);
	209	+ val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC);
204	210	val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0);
205	211	val \|= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val);
206		- writel(val, base + TEGRA_USB_HOSTPC1_DEVLC);
	212	+ writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);
207	213	} else {
208		- val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS;
	214	+ val = readl_relaxed(base + TEGRA_USB_PORTSC1);
	215	+ val &= ~TEGRA_PORTSC1_RWC_BITS;
209	216	val &= ~TEGRA_USB_PORTSC1_PTS(~0);
210	217	val \|= TEGRA_USB_PORTSC1_PTS(pts_val);
211		- writel(val, base + TEGRA_USB_PORTSC1);
	218	+ writel_relaxed(val, base + TEGRA_USB_PORTSC1);
212	219	}
213	220	}
214	221
215	222	static void set_phcd(struct tegra_usb_phy *phy, bool enable)
216	223	{
217	224	void __iomem *base = phy->regs;
218		- unsigned long val;
	225	+ u32 val;
219	226
220	227	if (phy->soc_config->has_hostpc) {
221		- val = readl(base + TEGRA_USB_HOSTPC1_DEVLC);
	228	+ val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC);
222	229	if (enable)
223	230	val \|= TEGRA_USB_HOSTPC1_DEVLC_PHCD;
224	231	else
225	232	val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD;
226		- writel(val, base + TEGRA_USB_HOSTPC1_DEVLC);
	233	+ writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);
227	234	} else {
228		- val = readl(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS;
	235	+ val = readl_relaxed(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS;
229	236	if (enable)
230	237	val \|= TEGRA_USB_PORTSC1_PHCD;
231	238	else
232	239	val &= ~TEGRA_USB_PORTSC1_PHCD;
233		- writel(val, base + TEGRA_USB_PORTSC1);
	240	+ writel_relaxed(val, base + TEGRA_USB_PORTSC1);
234	241	}
235	242	}
236	243
237	244	static int utmip_pad_open(struct tegra_usb_phy *phy)
238	245	{
239	246	int ret;
240		-
241		- phy->pad_clk = devm_clk_get(phy->u_phy.dev, "utmi-pads");
242		- if (IS_ERR(phy->pad_clk)) {
243		- ret = PTR_ERR(phy->pad_clk);
244		- dev_err(phy->u_phy.dev,
245		- "Failed to get UTMIP pad clock: %d\n", ret);
246		- return ret;
247		- }
248		-
249		- phy->pad_rst = devm_reset_control_get_optional_shared(
250		- phy->u_phy.dev, "utmi-pads");
251		- if (IS_ERR(phy->pad_rst)) {
252		- ret = PTR_ERR(phy->pad_rst);
253		- dev_err(phy->u_phy.dev,
254		- "Failed to get UTMI-pads reset: %d\n", ret);
255		- return ret;
256		- }
257	247
258	248	ret = clk_prepare_enable(phy->pad_clk);
259	249	if (ret) {
..	..	@@ -315,18 +305,21 @@
315	305	return ret;
316	306	}
317	307
318		-static void utmip_pad_power_on(struct tegra_usb_phy *phy)
	308	+static int utmip_pad_power_on(struct tegra_usb_phy *phy)
319	309	{
320		- unsigned long val, flags;
321		- void __iomem *base = phy->pad_regs;
322	310	struct tegra_utmip_config *config = phy->config;
	311	+ void __iomem *base = phy->pad_regs;
	312	+ u32 val;
	313	+ int err;
323	314
324		- clk_prepare_enable(phy->pad_clk);
	315	+ err = clk_prepare_enable(phy->pad_clk);
	316	+ if (err)
	317	+ return err;
325	318
326		- spin_lock_irqsave(&utmip_pad_lock, flags);
	319	+ spin_lock(&utmip_pad_lock);
327	320
328	321	if (utmip_pad_count++ == 0) {
329		- val = readl(base + UTMIP_BIAS_CFG0);
	322	+ val = readl_relaxed(base + UTMIP_BIAS_CFG0);
330	323	val &= ~(UTMIP_OTGPD \| UTMIP_BIASPD);
331	324
332	325	if (phy->soc_config->requires_extra_tuning_parameters) {
..	..	@@ -338,53 +331,59 @@
338	331	val \|= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level);
339	332	val \|= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level);
340	333	}
341		- writel(val, base + UTMIP_BIAS_CFG0);
	334	+ writel_relaxed(val, base + UTMIP_BIAS_CFG0);
342	335	}
343	336
344		- spin_unlock_irqrestore(&utmip_pad_lock, flags);
345		-
346		- clk_disable_unprepare(phy->pad_clk);
347		-}
348		-
349		-static int utmip_pad_power_off(struct tegra_usb_phy *phy)
350		-{
351		- unsigned long val, flags;
352		- void __iomem *base = phy->pad_regs;
353		-
354		- if (!utmip_pad_count) {
355		- dev_err(phy->u_phy.dev, "UTMIP pad already powered off\n");
356		- return -EINVAL;
357		- }
358		-
359		- clk_prepare_enable(phy->pad_clk);
360		-
361		- spin_lock_irqsave(&utmip_pad_lock, flags);
362		-
363		- if (--utmip_pad_count == 0) {
364		- val = readl(base + UTMIP_BIAS_CFG0);
365		- val \|= UTMIP_OTGPD \| UTMIP_BIASPD;
366		- writel(val, base + UTMIP_BIAS_CFG0);
367		- }
368		-
369		- spin_unlock_irqrestore(&utmip_pad_lock, flags);
	337	+ spin_unlock(&utmip_pad_lock);
370	338
371	339	clk_disable_unprepare(phy->pad_clk);
372	340
373	341	return 0;
374	342	}
375	343
	344	+static int utmip_pad_power_off(struct tegra_usb_phy *phy)
	345	+{
	346	+ void __iomem *base = phy->pad_regs;
	347	+ u32 val;
	348	+ int ret;
	349	+
	350	+ ret = clk_prepare_enable(phy->pad_clk);
	351	+ if (ret)
	352	+ return ret;
	353	+
	354	+ spin_lock(&utmip_pad_lock);
	355	+
	356	+ if (!utmip_pad_count) {
	357	+ dev_err(phy->u_phy.dev, "UTMIP pad already powered off\n");
	358	+ ret = -EINVAL;
	359	+ goto ulock;
	360	+ }
	361	+
	362	+ if (--utmip_pad_count == 0) {
	363	+ val = readl_relaxed(base + UTMIP_BIAS_CFG0);
	364	+ val \|= UTMIP_OTGPD \| UTMIP_BIASPD;
	365	+ writel_relaxed(val, base + UTMIP_BIAS_CFG0);
	366	+ }
	367	+ulock:
	368	+ spin_unlock(&utmip_pad_lock);
	369	+
	370	+ clk_disable_unprepare(phy->pad_clk);
	371	+
	372	+ return ret;
	373	+}
	374	+
376	375	static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
377	376	{
378	377	u32 tmp;
379	378
380		- return readl_poll_timeout(reg, tmp, (tmp & mask) == result,
381		- 2000, 6000);
	379	+ return readl_relaxed_poll_timeout(reg, tmp, (tmp & mask) == result,
	380	+ 2000, 6000);
382	381	}
383	382
384	383	static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
385	384	{
386		- unsigned long val;
387	385	void __iomem *base = phy->regs;
	386	+ u32 val;
388	387
389	388	/*
390	389	* The USB driver may have already initiated the phy clock
..	..	@@ -395,27 +394,28 @@
395	394	return;
396	395
397	396	if (phy->is_legacy_phy) {
398		- val = readl(base + USB_SUSP_CTRL);
	397	+ val = readl_relaxed(base + USB_SUSP_CTRL);
399	398	val \|= USB_SUSP_SET;
400		- writel(val, base + USB_SUSP_CTRL);
	399	+ writel_relaxed(val, base + USB_SUSP_CTRL);
401	400
402		- udelay(10);
	401	+ usleep_range(10, 100);
403	402
404		- val = readl(base + USB_SUSP_CTRL);
	403	+ val = readl_relaxed(base + USB_SUSP_CTRL);
405	404	val &= ~USB_SUSP_SET;
406		- writel(val, base + USB_SUSP_CTRL);
407		- } else
	405	+ writel_relaxed(val, base + USB_SUSP_CTRL);
	406	+ } else {
408	407	set_phcd(phy, true);
	408	+ }
409	409
410		- if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
	410	+ if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0))
411	411	dev_err(phy->u_phy.dev,
412	412	"Timeout waiting for PHY to stabilize on disable\n");
413	413	}
414	414
415	415	static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
416	416	{
417		- unsigned long val;
418	417	void __iomem *base = phy->regs;
	418	+ u32 val;
419	419
420	420	/*
421	421	* The USB driver may have already initiated the phy clock
..	..	@@ -427,97 +427,101 @@
427	427	return;
428	428
429	429	if (phy->is_legacy_phy) {
430		- val = readl(base + USB_SUSP_CTRL);
	430	+ val = readl_relaxed(base + USB_SUSP_CTRL);
431	431	val \|= USB_SUSP_CLR;
432		- writel(val, base + USB_SUSP_CTRL);
	432	+ writel_relaxed(val, base + USB_SUSP_CTRL);
433	433
434		- udelay(10);
	434	+ usleep_range(10, 100);
435	435
436		- val = readl(base + USB_SUSP_CTRL);
	436	+ val = readl_relaxed(base + USB_SUSP_CTRL);
437	437	val &= ~USB_SUSP_CLR;
438		- writel(val, base + USB_SUSP_CTRL);
439		- } else
	438	+ writel_relaxed(val, base + USB_SUSP_CTRL);
	439	+ } else {
440	440	set_phcd(phy, false);
	441	+ }
441	442
442	443	if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
443		- USB_PHY_CLK_VALID))
	444	+ USB_PHY_CLK_VALID))
444	445	dev_err(phy->u_phy.dev,
445	446	"Timeout waiting for PHY to stabilize on enable\n");
446	447	}
447	448
448	449	static int utmi_phy_power_on(struct tegra_usb_phy *phy)
449	450	{
450		- unsigned long val;
451		- void __iomem *base = phy->regs;
452	451	struct tegra_utmip_config *config = phy->config;
	452	+ void __iomem *base = phy->regs;
	453	+ u32 val;
	454	+ int err;
453	455
454		- val = readl(base + USB_SUSP_CTRL);
	456	+ val = readl_relaxed(base + USB_SUSP_CTRL);
455	457	val \|= UTMIP_RESET;
456		- writel(val, base + USB_SUSP_CTRL);
	458	+ writel_relaxed(val, base + USB_SUSP_CTRL);
457	459
458	460	if (phy->is_legacy_phy) {
459		- val = readl(base + USB1_LEGACY_CTRL);
	461	+ val = readl_relaxed(base + USB1_LEGACY_CTRL);
460	462	val \|= USB1_NO_LEGACY_MODE;
461		- writel(val, base + USB1_LEGACY_CTRL);
	463	+ writel_relaxed(val, base + USB1_LEGACY_CTRL);
462	464	}
463	465
464		- val = readl(base + UTMIP_TX_CFG0);
	466	+ val = readl_relaxed(base + UTMIP_TX_CFG0);
465	467	val \|= UTMIP_FS_PREABMLE_J;
466		- writel(val, base + UTMIP_TX_CFG0);
	468	+ writel_relaxed(val, base + UTMIP_TX_CFG0);
467	469
468		- val = readl(base + UTMIP_HSRX_CFG0);
	470	+ val = readl_relaxed(base + UTMIP_HSRX_CFG0);
469	471	val &= ~(UTMIP_IDLE_WAIT(~0) \| UTMIP_ELASTIC_LIMIT(~0));
470	472	val \|= UTMIP_IDLE_WAIT(config->idle_wait_delay);
471	473	val \|= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
472		- writel(val, base + UTMIP_HSRX_CFG0);
	474	+ writel_relaxed(val, base + UTMIP_HSRX_CFG0);
473	475
474		- val = readl(base + UTMIP_HSRX_CFG1);
	476	+ val = readl_relaxed(base + UTMIP_HSRX_CFG1);
475	477	val &= ~UTMIP_HS_SYNC_START_DLY(~0);
476	478	val \|= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
477		- writel(val, base + UTMIP_HSRX_CFG1);
	479	+ writel_relaxed(val, base + UTMIP_HSRX_CFG1);
478	480
479		- val = readl(base + UTMIP_DEBOUNCE_CFG0);
	481	+ val = readl_relaxed(base + UTMIP_DEBOUNCE_CFG0);
480	482	val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
481	483	val \|= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
482		- writel(val, base + UTMIP_DEBOUNCE_CFG0);
	484	+ writel_relaxed(val, base + UTMIP_DEBOUNCE_CFG0);
483	485
484		- val = readl(base + UTMIP_MISC_CFG0);
	486	+ val = readl_relaxed(base + UTMIP_MISC_CFG0);
485	487	val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
486		- writel(val, base + UTMIP_MISC_CFG0);
	488	+ writel_relaxed(val, base + UTMIP_MISC_CFG0);
487	489
488	490	if (!phy->soc_config->utmi_pll_config_in_car_module) {
489		- val = readl(base + UTMIP_MISC_CFG1);
	491	+ val = readl_relaxed(base + UTMIP_MISC_CFG1);
490	492	val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) \|
491	493	UTMIP_PLLU_STABLE_COUNT(~0));
492	494	val \|= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) \|
493	495	UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
494		- writel(val, base + UTMIP_MISC_CFG1);
	496	+ writel_relaxed(val, base + UTMIP_MISC_CFG1);
495	497
496		- val = readl(base + UTMIP_PLL_CFG1);
	498	+ val = readl_relaxed(base + UTMIP_PLL_CFG1);
497	499	val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) \|
498	500	UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
499	501	val \|= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) \|
500	502	UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
501		- writel(val, base + UTMIP_PLL_CFG1);
	503	+ writel_relaxed(val, base + UTMIP_PLL_CFG1);
502	504	}
503	505
504	506	if (phy->mode == USB_DR_MODE_PERIPHERAL) {
505		- val = readl(base + USB_SUSP_CTRL);
	507	+ val = readl_relaxed(base + USB_SUSP_CTRL);
506	508	val &= ~(USB_WAKE_ON_CNNT_EN_DEV \| USB_WAKE_ON_DISCON_EN_DEV);
507		- writel(val, base + USB_SUSP_CTRL);
	509	+ writel_relaxed(val, base + USB_SUSP_CTRL);
508	510
509		- val = readl(base + UTMIP_BAT_CHRG_CFG0);
	511	+ val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
510	512	val &= ~UTMIP_PD_CHRG;
511		- writel(val, base + UTMIP_BAT_CHRG_CFG0);
	513	+ writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
512	514	} else {
513		- val = readl(base + UTMIP_BAT_CHRG_CFG0);
	515	+ val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
514	516	val \|= UTMIP_PD_CHRG;
515		- writel(val, base + UTMIP_BAT_CHRG_CFG0);
	517	+ writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
516	518	}
517	519
518		- utmip_pad_power_on(phy);
	520	+ err = utmip_pad_power_on(phy);
	521	+ if (err)
	522	+ return err;
519	523
520		- val = readl(base + UTMIP_XCVR_CFG0);
	524	+ val = readl_relaxed(base + UTMIP_XCVR_CFG0);
521	525	val &= ~(UTMIP_FORCE_PD_POWERDOWN \| UTMIP_FORCE_PD2_POWERDOWN \|
522	526	UTMIP_FORCE_PDZI_POWERDOWN \| UTMIP_XCVR_LSBIAS_SEL \|
523	527	UTMIP_XCVR_SETUP(~0) \| UTMIP_XCVR_SETUP_MSB(~0) \|
..	..	@@ -535,57 +539,57 @@
535	539	val \|= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew);
536	540	val \|= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew);
537	541	}
538		- writel(val, base + UTMIP_XCVR_CFG0);
	542	+ writel_relaxed(val, base + UTMIP_XCVR_CFG0);
539	543
540		- val = readl(base + UTMIP_XCVR_CFG1);
	544	+ val = readl_relaxed(base + UTMIP_XCVR_CFG1);
541	545	val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN \| UTMIP_FORCE_PDCHRP_POWERDOWN \|
542	546	UTMIP_FORCE_PDDR_POWERDOWN \| UTMIP_XCVR_TERM_RANGE_ADJ(~0));
543	547	val \|= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
544		- writel(val, base + UTMIP_XCVR_CFG1);
	548	+ writel_relaxed(val, base + UTMIP_XCVR_CFG1);
545	549
546		- val = readl(base + UTMIP_BIAS_CFG1);
	550	+ val = readl_relaxed(base + UTMIP_BIAS_CFG1);
547	551	val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
548	552	val \|= UTMIP_BIAS_PDTRK_COUNT(0x5);
549		- writel(val, base + UTMIP_BIAS_CFG1);
	553	+ writel_relaxed(val, base + UTMIP_BIAS_CFG1);
550	554
551		- val = readl(base + UTMIP_SPARE_CFG0);
	555	+ val = readl_relaxed(base + UTMIP_SPARE_CFG0);
552	556	if (config->xcvr_setup_use_fuses)
553	557	val \|= FUSE_SETUP_SEL;
554	558	else
555	559	val &= ~FUSE_SETUP_SEL;
556		- writel(val, base + UTMIP_SPARE_CFG0);
	560	+ writel_relaxed(val, base + UTMIP_SPARE_CFG0);
557	561
558	562	if (!phy->is_legacy_phy) {
559		- val = readl(base + USB_SUSP_CTRL);
	563	+ val = readl_relaxed(base + USB_SUSP_CTRL);
560	564	val \|= UTMIP_PHY_ENABLE;
561		- writel(val, base + USB_SUSP_CTRL);
	565	+ writel_relaxed(val, base + USB_SUSP_CTRL);
562	566	}
563	567
564		- val = readl(base + USB_SUSP_CTRL);
	568	+ val = readl_relaxed(base + USB_SUSP_CTRL);
565	569	val &= ~UTMIP_RESET;
566		- writel(val, base + USB_SUSP_CTRL);
	570	+ writel_relaxed(val, base + USB_SUSP_CTRL);
567	571
568	572	if (phy->is_legacy_phy) {
569		- val = readl(base + USB1_LEGACY_CTRL);
	573	+ val = readl_relaxed(base + USB1_LEGACY_CTRL);
570	574	val &= ~USB1_VBUS_SENSE_CTL_MASK;
571	575	val \|= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
572		- writel(val, base + USB1_LEGACY_CTRL);
	576	+ writel_relaxed(val, base + USB1_LEGACY_CTRL);
573	577
574		- val = readl(base + USB_SUSP_CTRL);
	578	+ val = readl_relaxed(base + USB_SUSP_CTRL);
575	579	val &= ~USB_SUSP_SET;
576		- writel(val, base + USB_SUSP_CTRL);
	580	+ writel_relaxed(val, base + USB_SUSP_CTRL);
577	581	}
578	582
579	583	utmi_phy_clk_enable(phy);
580	584
581	585	if (phy->soc_config->requires_usbmode_setup) {
582		- val = readl(base + USB_USBMODE);
	586	+ val = readl_relaxed(base + USB_USBMODE);
583	587	val &= ~USB_USBMODE_MASK;
584	588	if (phy->mode == USB_DR_MODE_HOST)
585	589	val \|= USB_USBMODE_HOST;
586	590	else
587	591	val \|= USB_USBMODE_DEVICE;
588		- writel(val, base + USB_USBMODE);
	592	+ writel_relaxed(val, base + USB_USBMODE);
589	593	}
590	594
591	595	if (!phy->is_legacy_phy)
..	..	@@ -596,258 +600,252 @@
596	600
597	601	static int utmi_phy_power_off(struct tegra_usb_phy *phy)
598	602	{
599		- unsigned long val;
600	603	void __iomem *base = phy->regs;
	604	+ u32 val;
601	605
602	606	utmi_phy_clk_disable(phy);
603	607
604	608	if (phy->mode == USB_DR_MODE_PERIPHERAL) {
605		- val = readl(base + USB_SUSP_CTRL);
	609	+ val = readl_relaxed(base + USB_SUSP_CTRL);
606	610	val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
607	611	val \|= USB_WAKE_ON_CNNT_EN_DEV \| USB_WAKEUP_DEBOUNCE_COUNT(5);
608		- writel(val, base + USB_SUSP_CTRL);
	612	+ writel_relaxed(val, base + USB_SUSP_CTRL);
609	613	}
610	614
611		- val = readl(base + USB_SUSP_CTRL);
	615	+ val = readl_relaxed(base + USB_SUSP_CTRL);
612	616	val \|= UTMIP_RESET;
613		- writel(val, base + USB_SUSP_CTRL);
	617	+ writel_relaxed(val, base + USB_SUSP_CTRL);
614	618
615		- val = readl(base + UTMIP_BAT_CHRG_CFG0);
	619	+ val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
616	620	val \|= UTMIP_PD_CHRG;
617		- writel(val, base + UTMIP_BAT_CHRG_CFG0);
	621	+ writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
618	622
619		- val = readl(base + UTMIP_XCVR_CFG0);
	623	+ val = readl_relaxed(base + UTMIP_XCVR_CFG0);
620	624	val \|= UTMIP_FORCE_PD_POWERDOWN \| UTMIP_FORCE_PD2_POWERDOWN \|
621	625	UTMIP_FORCE_PDZI_POWERDOWN;
622		- writel(val, base + UTMIP_XCVR_CFG0);
	626	+ writel_relaxed(val, base + UTMIP_XCVR_CFG0);
623	627
624		- val = readl(base + UTMIP_XCVR_CFG1);
	628	+ val = readl_relaxed(base + UTMIP_XCVR_CFG1);
625	629	val \|= UTMIP_FORCE_PDDISC_POWERDOWN \| UTMIP_FORCE_PDCHRP_POWERDOWN \|
626	630	UTMIP_FORCE_PDDR_POWERDOWN;
627		- writel(val, base + UTMIP_XCVR_CFG1);
	631	+ writel_relaxed(val, base + UTMIP_XCVR_CFG1);
628	632
629	633	return utmip_pad_power_off(phy);
630	634	}
631	635
632	636	static void utmi_phy_preresume(struct tegra_usb_phy *phy)
633	637	{
634		- unsigned long val;
635	638	void __iomem *base = phy->regs;
	639	+ u32 val;
636	640
637		- val = readl(base + UTMIP_TX_CFG0);
	641	+ val = readl_relaxed(base + UTMIP_TX_CFG0);
638	642	val \|= UTMIP_HS_DISCON_DISABLE;
639		- writel(val, base + UTMIP_TX_CFG0);
	643	+ writel_relaxed(val, base + UTMIP_TX_CFG0);
640	644	}
641	645
642	646	static void utmi_phy_postresume(struct tegra_usb_phy *phy)
643	647	{
644		- unsigned long val;
645	648	void __iomem *base = phy->regs;
	649	+ u32 val;
646	650
647		- val = readl(base + UTMIP_TX_CFG0);
	651	+ val = readl_relaxed(base + UTMIP_TX_CFG0);
648	652	val &= ~UTMIP_HS_DISCON_DISABLE;
649		- writel(val, base + UTMIP_TX_CFG0);
	653	+ writel_relaxed(val, base + UTMIP_TX_CFG0);
650	654	}
651	655
652	656	static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
653	657	enum tegra_usb_phy_port_speed port_speed)
654	658	{
655		- unsigned long val;
656	659	void __iomem *base = phy->regs;
	660	+ u32 val;
657	661
658		- val = readl(base + UTMIP_MISC_CFG0);
	662	+ val = readl_relaxed(base + UTMIP_MISC_CFG0);
659	663	val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
660	664	if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
661	665	val \|= UTMIP_DPDM_OBSERVE_SEL_FS_K;
662	666	else
663	667	val \|= UTMIP_DPDM_OBSERVE_SEL_FS_J;
664		- writel(val, base + UTMIP_MISC_CFG0);
665		- udelay(1);
	668	+ writel_relaxed(val, base + UTMIP_MISC_CFG0);
	669	+ usleep_range(1, 10);
666	670
667		- val = readl(base + UTMIP_MISC_CFG0);
	671	+ val = readl_relaxed(base + UTMIP_MISC_CFG0);
668	672	val \|= UTMIP_DPDM_OBSERVE;
669		- writel(val, base + UTMIP_MISC_CFG0);
670		- udelay(10);
	673	+ writel_relaxed(val, base + UTMIP_MISC_CFG0);
	674	+ usleep_range(10, 100);
671	675	}
672	676
673	677	static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
674	678	{
675		- unsigned long val;
676	679	void __iomem *base = phy->regs;
	680	+ u32 val;
677	681
678		- val = readl(base + UTMIP_MISC_CFG0);
	682	+ val = readl_relaxed(base + UTMIP_MISC_CFG0);
679	683	val &= ~UTMIP_DPDM_OBSERVE;
680		- writel(val, base + UTMIP_MISC_CFG0);
681		- udelay(10);
	684	+ writel_relaxed(val, base + UTMIP_MISC_CFG0);
	685	+ usleep_range(10, 100);
682	686	}
683	687
684	688	static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
685	689	{
686		- int ret;
687		- unsigned long val;
688	690	void __iomem *base = phy->regs;
	691	+ u32 val;
	692	+ int err;
689	693
690		- ret = gpio_direction_output(phy->reset_gpio, 0);
691		- if (ret < 0) {
692		- dev_err(phy->u_phy.dev, "GPIO %d not set to 0: %d\n",
693		- phy->reset_gpio, ret);
694		- return ret;
695		- }
696		- msleep(5);
697		- ret = gpio_direction_output(phy->reset_gpio, 1);
698		- if (ret < 0) {
699		- dev_err(phy->u_phy.dev, "GPIO %d not set to 1: %d\n",
700		- phy->reset_gpio, ret);
701		- return ret;
702		- }
	694	+ gpiod_set_value_cansleep(phy->reset_gpio, 1);
703	695
704		- clk_prepare_enable(phy->clk);
705		- msleep(1);
	696	+ err = clk_prepare_enable(phy->clk);
	697	+ if (err)
	698	+ return err;
706	699
707		- val = readl(base + USB_SUSP_CTRL);
	700	+ usleep_range(5000, 6000);
	701	+
	702	+ gpiod_set_value_cansleep(phy->reset_gpio, 0);
	703	+
	704	+ usleep_range(1000, 2000);
	705	+
	706	+ val = readl_relaxed(base + USB_SUSP_CTRL);
708	707	val \|= UHSIC_RESET;
709		- writel(val, base + USB_SUSP_CTRL);
	708	+ writel_relaxed(val, base + USB_SUSP_CTRL);
710	709
711		- val = readl(base + ULPI_TIMING_CTRL_0);
	710	+ val = readl_relaxed(base + ULPI_TIMING_CTRL_0);
712	711	val \|= ULPI_OUTPUT_PINMUX_BYP \| ULPI_CLKOUT_PINMUX_BYP;
713		- writel(val, base + ULPI_TIMING_CTRL_0);
	712	+ writel_relaxed(val, base + ULPI_TIMING_CTRL_0);
714	713
715		- val = readl(base + USB_SUSP_CTRL);
	714	+ val = readl_relaxed(base + USB_SUSP_CTRL);
716	715	val \|= ULPI_PHY_ENABLE;
717		- writel(val, base + USB_SUSP_CTRL);
	716	+ writel_relaxed(val, base + USB_SUSP_CTRL);
718	717
719	718	val = 0;
720		- writel(val, base + ULPI_TIMING_CTRL_1);
	719	+ writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
721	720
722	721	val \|= ULPI_DATA_TRIMMER_SEL(4);
723	722	val \|= ULPI_STPDIRNXT_TRIMMER_SEL(4);
724	723	val \|= ULPI_DIR_TRIMMER_SEL(4);
725		- writel(val, base + ULPI_TIMING_CTRL_1);
726		- udelay(10);
	724	+ writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
	725	+ usleep_range(10, 100);
727	726
728	727	val \|= ULPI_DATA_TRIMMER_LOAD;
729	728	val \|= ULPI_STPDIRNXT_TRIMMER_LOAD;
730	729	val \|= ULPI_DIR_TRIMMER_LOAD;
731		- writel(val, base + ULPI_TIMING_CTRL_1);
	730	+ writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
732	731
733	732	/* Fix VbusInvalid due to floating VBUS */
734		- ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
735		- if (ret) {
736		- dev_err(phy->u_phy.dev, "ULPI write failed: %d\n", ret);
737		- return ret;
	733	+ err = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
	734	+ if (err) {
	735	+ dev_err(phy->u_phy.dev, "ULPI write failed: %d\n", err);
	736	+ goto disable_clk;
738	737	}
739	738
740		- ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
741		- if (ret) {
742		- dev_err(phy->u_phy.dev, "ULPI write failed: %d\n", ret);
743		- return ret;
	739	+ err = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
	740	+ if (err) {
	741	+ dev_err(phy->u_phy.dev, "ULPI write failed: %d\n", err);
	742	+ goto disable_clk;
744	743	}
745	744
746		- val = readl(base + USB_SUSP_CTRL);
	745	+ val = readl_relaxed(base + USB_SUSP_CTRL);
747	746	val \|= USB_SUSP_CLR;
748		- writel(val, base + USB_SUSP_CTRL);
749		- udelay(100);
	747	+ writel_relaxed(val, base + USB_SUSP_CTRL);
	748	+ usleep_range(100, 1000);
750	749
751		- val = readl(base + USB_SUSP_CTRL);
	750	+ val = readl_relaxed(base + USB_SUSP_CTRL);
752	751	val &= ~USB_SUSP_CLR;
753		- writel(val, base + USB_SUSP_CTRL);
	752	+ writel_relaxed(val, base + USB_SUSP_CTRL);
754	753
755	754	return 0;
	755	+
	756	+disable_clk:
	757	+ clk_disable_unprepare(phy->clk);
	758	+
	759	+ return err;
756	760	}
757	761
758	762	static int ulpi_phy_power_off(struct tegra_usb_phy *phy)
759	763	{
760		- clk_disable(phy->clk);
761		- return gpio_direction_output(phy->reset_gpio, 0);
762		-}
	764	+ gpiod_set_value_cansleep(phy->reset_gpio, 1);
	765	+ usleep_range(5000, 6000);
	766	+ clk_disable_unprepare(phy->clk);
763	767
764		-static void tegra_usb_phy_close(struct tegra_usb_phy *phy)
765		-{
766		- if (!IS_ERR(phy->vbus))
767		- regulator_disable(phy->vbus);
768		-
769		- if (!phy->is_ulpi_phy)
770		- utmip_pad_close(phy);
771		-
772		- clk_disable_unprepare(phy->pll_u);
	768	+ return 0;
773	769	}
774	770
775	771	static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
776	772	{
	773	+ int err;
	774	+
	775	+ if (phy->powered_on)
	776	+ return 0;
	777	+
777	778	if (phy->is_ulpi_phy)
778		- return ulpi_phy_power_on(phy);
	779	+ err = ulpi_phy_power_on(phy);
779	780	else
780		- return utmi_phy_power_on(phy);
	781	+ err = utmi_phy_power_on(phy);
	782	+ if (err)
	783	+ return err;
	784	+
	785	+ phy->powered_on = true;
	786	+
	787	+ return 0;
781	788	}
782	789
783	790	static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
784	791	{
	792	+ int err;
	793	+
	794	+ if (!phy->powered_on)
	795	+ return 0;
	796	+
785	797	if (phy->is_ulpi_phy)
786		- return ulpi_phy_power_off(phy);
	798	+ err = ulpi_phy_power_off(phy);
787	799	else
788		- return utmi_phy_power_off(phy);
	800	+ err = utmi_phy_power_off(phy);
	801	+ if (err)
	802	+ return err;
	803	+
	804	+ phy->powered_on = false;
	805	+
	806	+ return 0;
789	807	}
790	808
791		-static int tegra_usb_phy_suspend(struct usb_phy *x, int suspend)
	809	+static void tegra_usb_phy_shutdown(struct usb_phy *u_phy)
792	810	{
793		- struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
	811	+ struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
	812	+
	813	+ if (WARN_ON(!phy->freq))
	814	+ return;
	815	+
	816	+ tegra_usb_phy_power_off(phy);
	817	+
	818	+ if (!phy->is_ulpi_phy)
	819	+ utmip_pad_close(phy);
	820	+
	821	+ regulator_disable(phy->vbus);
	822	+ clk_disable_unprepare(phy->pll_u);
	823	+
	824	+ phy->freq = NULL;
	825	+}
	826	+
	827	+static int tegra_usb_phy_set_suspend(struct usb_phy *u_phy, int suspend)
	828	+{
	829	+ struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
	830	+
	831	+ if (WARN_ON(!phy->freq))
	832	+ return -EINVAL;
	833	+
794	834	if (suspend)
795	835	return tegra_usb_phy_power_off(phy);
796	836	else
797	837	return tegra_usb_phy_power_on(phy);
798	838	}
799	839
800		-static int ulpi_open(struct tegra_usb_phy *phy)
	840	+static int tegra_usb_phy_init(struct usb_phy *u_phy)
801	841	{
802		- int err;
803		-
804		- phy->clk = devm_clk_get(phy->u_phy.dev, "ulpi-link");
805		- if (IS_ERR(phy->clk)) {
806		- err = PTR_ERR(phy->clk);
807		- dev_err(phy->u_phy.dev, "Failed to get ULPI clock: %d\n", err);
808		- return err;
809		- }
810		-
811		- err = devm_gpio_request(phy->u_phy.dev, phy->reset_gpio,
812		- "ulpi_phy_reset_b");
813		- if (err < 0) {
814		- dev_err(phy->u_phy.dev, "Request failed for GPIO %d: %d\n",
815		- phy->reset_gpio, err);
816		- return err;
817		- }
818		-
819		- err = gpio_direction_output(phy->reset_gpio, 0);
820		- if (err < 0) {
821		- dev_err(phy->u_phy.dev,
822		- "GPIO %d direction not set to output: %d\n",
823		- phy->reset_gpio, err);
824		- return err;
825		- }
826		-
827		- phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
828		- if (!phy->ulpi) {
829		- dev_err(phy->u_phy.dev, "Failed to create ULPI OTG\n");
830		- err = -ENOMEM;
831		- return err;
832		- }
833		-
834		- phy->ulpi->io_priv = phy->regs + ULPI_VIEWPORT;
835		- return 0;
836		-}
837		-
838		-static int tegra_usb_phy_init(struct tegra_usb_phy *phy)
839		-{
	842	+ struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
840	843	unsigned long parent_rate;
841		- int i;
	844	+ unsigned int i;
842	845	int err;
843	846
844		- phy->pll_u = devm_clk_get(phy->u_phy.dev, "pll_u");
845		- if (IS_ERR(phy->pll_u)) {
846		- err = PTR_ERR(phy->pll_u);
847		- dev_err(phy->u_phy.dev,
848		- "Failed to get pll_u clock: %d\n", err);
849		- return err;
850		- }
	847	+ if (WARN_ON(phy->freq))
	848	+ return 0;
851	849
852	850	err = clk_prepare_enable(phy->pll_u);
853	851	if (err)
..	..	@@ -864,64 +862,74 @@
864	862	dev_err(phy->u_phy.dev, "Invalid pll_u parent rate %ld\n",
865	863	parent_rate);
866	864	err = -EINVAL;
867		- goto fail;
	865	+ goto disable_clk;
868	866	}
869	867
870		- if (!IS_ERR(phy->vbus)) {
871		- err = regulator_enable(phy->vbus);
872		- if (err) {
873		- dev_err(phy->u_phy.dev,
874		- "Failed to enable USB VBUS regulator: %d\n",
875		- err);
876		- goto fail;
877		- }
	868	+ err = regulator_enable(phy->vbus);
	869	+ if (err) {
	870	+ dev_err(phy->u_phy.dev,
	871	+ "Failed to enable USB VBUS regulator: %d\n", err);
	872	+ goto disable_clk;
878	873	}
879	874
880		- if (phy->is_ulpi_phy)
881		- err = ulpi_open(phy);
882		- else
	875	+ if (!phy->is_ulpi_phy) {
883	876	err = utmip_pad_open(phy);
884		- if (err < 0)
885		- goto fail;
	877	+ if (err)
	878	+ goto disable_vbus;
	879	+ }
	880	+
	881	+ err = tegra_usb_phy_power_on(phy);
	882	+ if (err)
	883	+ goto close_phy;
886	884
887	885	return 0;
888	886
889		-fail:
	887	+close_phy:
	888	+ if (!phy->is_ulpi_phy)
	889	+ utmip_pad_close(phy);
	890	+
	891	+disable_vbus:
	892	+ regulator_disable(phy->vbus);
	893	+
	894	+disable_clk:
890	895	clk_disable_unprepare(phy->pll_u);
	896	+
	897	+ phy->freq = NULL;
	898	+
891	899	return err;
892	900	}
893	901
894		-void tegra_usb_phy_preresume(struct usb_phy *x)
	902	+void tegra_usb_phy_preresume(struct usb_phy *u_phy)
895	903	{
896		- struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
	904	+ struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
897	905
898	906	if (!phy->is_ulpi_phy)
899	907	utmi_phy_preresume(phy);
900	908	}
901	909	EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
902	910
903		-void tegra_usb_phy_postresume(struct usb_phy *x)
	911	+void tegra_usb_phy_postresume(struct usb_phy *u_phy)
904	912	{
905		- struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
	913	+ struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
906	914
907	915	if (!phy->is_ulpi_phy)
908	916	utmi_phy_postresume(phy);
909	917	}
910	918	EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
911	919
912		-void tegra_ehci_phy_restore_start(struct usb_phy *x,
913		- enum tegra_usb_phy_port_speed port_speed)
	920	+void tegra_ehci_phy_restore_start(struct usb_phy *u_phy,
	921	+ enum tegra_usb_phy_port_speed port_speed)
914	922	{
915		- struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
	923	+ struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
916	924
917	925	if (!phy->is_ulpi_phy)
918	926	utmi_phy_restore_start(phy, port_speed);
919	927	}
920	928	EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
921	929
922		-void tegra_ehci_phy_restore_end(struct usb_phy *x)
	930	+void tegra_ehci_phy_restore_end(struct usb_phy *u_phy)
923	931	{
924		- struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
	932	+ struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
925	933
926	934	if (!phy->is_ulpi_phy)
927	935	utmi_phy_restore_end(phy);
..	..	@@ -932,21 +940,25 @@
932	940	u8 *dest)
933	941	{
934	942	u32 value;
935		- int err = of_property_read_u32(pdev->dev.of_node, param, &value);
936		- *dest = (u8)value;
937		- if (err < 0)
	943	+ int err;
	944	+
	945	+ err = of_property_read_u32(pdev->dev.of_node, param, &value);
	946	+ if (err)
938	947	dev_err(&pdev->dev,
939	948	"Failed to read USB UTMI parameter %s: %d\n",
940	949	param, err);
	950	+ else
	951	+ *dest = value;
	952	+
941	953	return err;
942	954	}
943	955
944	956	static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy,
945	957	struct platform_device *pdev)
946	958	{
	959	+ struct tegra_utmip_config *config;
947	960	struct resource *res;
948	961	int err;
949		- struct tegra_utmip_config *config;
950	962
951	963	tegra_phy->is_ulpi_phy = false;
952	964
..	..	@@ -956,8 +968,12 @@
956	968	return -ENXIO;
957	969	}
958	970
	971	+ /*
	972	+ * Note that UTMI pad registers are shared by all PHYs, therefore
	973	+ * devm_platform_ioremap_resource() can't be used here.
	974	+ */
959	975	tegra_phy->pad_regs = devm_ioremap(&pdev->dev, res->start,
960		- resource_size(res));
	976	+ resource_size(res));
961	977	if (!tegra_phy->pad_regs) {
962	978	dev_err(&pdev->dev, "Failed to remap UTMI pad regs\n");
963	979	return -ENOMEM;
..	..	@@ -971,49 +987,49 @@
971	987	config = tegra_phy->config;
972	988
973	989	err = read_utmi_param(pdev, "nvidia,hssync-start-delay",
974		- &config->hssync_start_delay);
975		- if (err < 0)
	990	+ &config->hssync_start_delay);
	991	+ if (err)
976	992	return err;
977	993
978	994	err = read_utmi_param(pdev, "nvidia,elastic-limit",
979		- &config->elastic_limit);
980		- if (err < 0)
	995	+ &config->elastic_limit);
	996	+ if (err)
981	997	return err;
982	998
983	999	err = read_utmi_param(pdev, "nvidia,idle-wait-delay",
984		- &config->idle_wait_delay);
985		- if (err < 0)
	1000	+ &config->idle_wait_delay);
	1001	+ if (err)
986	1002	return err;
987	1003
988	1004	err = read_utmi_param(pdev, "nvidia,term-range-adj",
989		- &config->term_range_adj);
990		- if (err < 0)
	1005	+ &config->term_range_adj);
	1006	+ if (err)
991	1007	return err;
992	1008
993	1009	err = read_utmi_param(pdev, "nvidia,xcvr-lsfslew",
994		- &config->xcvr_lsfslew);
995		- if (err < 0)
	1010	+ &config->xcvr_lsfslew);
	1011	+ if (err)
996	1012	return err;
997	1013
998	1014	err = read_utmi_param(pdev, "nvidia,xcvr-lsrslew",
999		- &config->xcvr_lsrslew);
1000		- if (err < 0)
	1015	+ &config->xcvr_lsrslew);
	1016	+ if (err)
1001	1017	return err;
1002	1018
1003	1019	if (tegra_phy->soc_config->requires_extra_tuning_parameters) {
1004	1020	err = read_utmi_param(pdev, "nvidia,xcvr-hsslew",
1005		- &config->xcvr_hsslew);
1006		- if (err < 0)
	1021	+ &config->xcvr_hsslew);
	1022	+ if (err)
1007	1023	return err;
1008	1024
1009	1025	err = read_utmi_param(pdev, "nvidia,hssquelch-level",
1010		- &config->hssquelch_level);
1011		- if (err < 0)
	1026	+ &config->hssquelch_level);
	1027	+ if (err)
1012	1028	return err;
1013	1029
1014	1030	err = read_utmi_param(pdev, "nvidia,hsdiscon-level",
1015		- &config->hsdiscon_level);
1016		- if (err < 0)
	1031	+ &config->hsdiscon_level);
	1032	+ if (err)
1017	1033	return err;
1018	1034	}
1019	1035
..	..	@@ -1022,8 +1038,8 @@
1022	1038
1023	1039	if (!config->xcvr_setup_use_fuses) {
1024	1040	err = read_utmi_param(pdev, "nvidia,xcvr-setup",
1025		- &config->xcvr_setup);
1026		- if (err < 0)
	1041	+ &config->xcvr_setup);
	1042	+ if (err)
1027	1043	return err;
1028	1044	}
1029	1045
..	..	@@ -1053,23 +1069,20 @@
1053	1069
1054	1070	static int tegra_usb_phy_probe(struct platform_device *pdev)
1055	1071	{
1056		- const struct of_device_id *match;
1057		- struct resource *res;
1058		- struct tegra_usb_phy *tegra_phy = NULL;
1059	1072	struct device_node *np = pdev->dev.of_node;
	1073	+ struct tegra_usb_phy *tegra_phy;
1060	1074	enum usb_phy_interface phy_type;
	1075	+ struct reset_control *reset;
	1076	+ struct gpio_desc *gpiod;
	1077	+ struct resource *res;
	1078	+ struct usb_phy *phy;
1061	1079	int err;
1062	1080
1063	1081	tegra_phy = devm_kzalloc(&pdev->dev, sizeof(*tegra_phy), GFP_KERNEL);
1064	1082	if (!tegra_phy)
1065	1083	return -ENOMEM;
1066	1084
1067		- match = of_match_device(tegra_usb_phy_id_table, &pdev->dev);
1068		- if (!match) {
1069		- dev_err(&pdev->dev, "Error: No device match found\n");
1070		- return -ENODEV;
1071		- }
1072		- tegra_phy->soc_config = match->data;
	1085	+ tegra_phy->soc_config = of_device_get_match_data(&pdev->dev);
1073	1086
1074	1087	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1075	1088	if (!res) {
..	..	@@ -1077,8 +1090,12 @@
1077	1090	return -ENXIO;
1078	1091	}
1079	1092
	1093	+ /*
	1094	+ * Note that PHY and USB controller are using shared registers,
	1095	+ * therefore devm_platform_ioremap_resource() can't be used here.
	1096	+ */
1080	1097	tegra_phy->regs = devm_ioremap(&pdev->dev, res->start,
1081		- resource_size(res));
	1098	+ resource_size(res));
1082	1099	if (!tegra_phy->regs) {
1083	1100	dev_err(&pdev->dev, "Failed to remap I/O memory\n");
1084	1101	return -ENOMEM;
..	..	@@ -1086,33 +1103,6 @@
1086	1103
1087	1104	tegra_phy->is_legacy_phy =
1088	1105	of_property_read_bool(np, "nvidia,has-legacy-mode");
1089		-
1090		- phy_type = of_usb_get_phy_mode(np);
1091		- switch (phy_type) {
1092		- case USBPHY_INTERFACE_MODE_UTMI:
1093		- err = utmi_phy_probe(tegra_phy, pdev);
1094		- if (err < 0)
1095		- return err;
1096		- break;
1097		-
1098		- case USBPHY_INTERFACE_MODE_ULPI:
1099		- tegra_phy->is_ulpi_phy = true;
1100		-
1101		- tegra_phy->reset_gpio =
1102		- of_get_named_gpio(np, "nvidia,phy-reset-gpio", 0);
1103		- if (!gpio_is_valid(tegra_phy->reset_gpio)) {
1104		- dev_err(&pdev->dev,
1105		- "Invalid GPIO: %d\n", tegra_phy->reset_gpio);
1106		- return tegra_phy->reset_gpio;
1107		- }
1108		- tegra_phy->config = NULL;
1109		- break;
1110		-
1111		- default:
1112		- dev_err(&pdev->dev, "phy_type %u is invalid or unsupported\n",
1113		- phy_type);
1114		- return -EINVAL;
1115		- }
1116	1106
1117	1107	if (of_find_property(np, "dr_mode", NULL))
1118	1108	tegra_phy->mode = usb_get_dr_mode(&pdev->dev);
..	..	@@ -1125,31 +1115,91 @@
1125	1115	}
1126	1116
1127	1117	/* On some boards, the VBUS regulator doesn't need to be controlled */
1128		- if (of_find_property(np, "vbus-supply", NULL)) {
1129		- tegra_phy->vbus = devm_regulator_get(&pdev->dev, "vbus");
1130		- if (IS_ERR(tegra_phy->vbus))
1131		- return PTR_ERR(tegra_phy->vbus);
1132		- } else {
1133		- dev_notice(&pdev->dev, "no vbus regulator");
1134		- tegra_phy->vbus = ERR_PTR(-ENODEV);
	1118	+ tegra_phy->vbus = devm_regulator_get(&pdev->dev, "vbus");
	1119	+ if (IS_ERR(tegra_phy->vbus))
	1120	+ return PTR_ERR(tegra_phy->vbus);
	1121	+
	1122	+ tegra_phy->pll_u = devm_clk_get(&pdev->dev, "pll_u");
	1123	+ err = PTR_ERR_OR_ZERO(tegra_phy->pll_u);
	1124	+ if (err) {
	1125	+ dev_err(&pdev->dev, "Failed to get pll_u clock: %d\n", err);
	1126	+ return err;
	1127	+ }
	1128	+
	1129	+ phy_type = of_usb_get_phy_mode(np);
	1130	+ switch (phy_type) {
	1131	+ case USBPHY_INTERFACE_MODE_UTMI:
	1132	+ err = utmi_phy_probe(tegra_phy, pdev);
	1133	+ if (err)
	1134	+ return err;
	1135	+
	1136	+ tegra_phy->pad_clk = devm_clk_get(&pdev->dev, "utmi-pads");
	1137	+ err = PTR_ERR_OR_ZERO(tegra_phy->pad_clk);
	1138	+ if (err) {
	1139	+ dev_err(&pdev->dev,
	1140	+ "Failed to get UTMIP pad clock: %d\n", err);
	1141	+ return err;
	1142	+ }
	1143	+
	1144	+ reset = devm_reset_control_get_optional_shared(&pdev->dev,
	1145	+ "utmi-pads");
	1146	+ err = PTR_ERR_OR_ZERO(reset);
	1147	+ if (err) {
	1148	+ dev_err(&pdev->dev,
	1149	+ "Failed to get UTMI-pads reset: %d\n", err);
	1150	+ return err;
	1151	+ }
	1152	+ tegra_phy->pad_rst = reset;
	1153	+ break;
	1154	+
	1155	+ case USBPHY_INTERFACE_MODE_ULPI:
	1156	+ tegra_phy->is_ulpi_phy = true;
	1157	+
	1158	+ tegra_phy->clk = devm_clk_get(&pdev->dev, "ulpi-link");
	1159	+ err = PTR_ERR_OR_ZERO(tegra_phy->clk);
	1160	+ if (err) {
	1161	+ dev_err(&pdev->dev,
	1162	+ "Failed to get ULPI clock: %d\n", err);
	1163	+ return err;
	1164	+ }
	1165	+
	1166	+ gpiod = devm_gpiod_get_from_of_node(&pdev->dev, np,
	1167	+ "nvidia,phy-reset-gpio",
	1168	+ 0, GPIOD_OUT_HIGH,
	1169	+ "ulpi_phy_reset_b");
	1170	+ err = PTR_ERR_OR_ZERO(gpiod);
	1171	+ if (err) {
	1172	+ dev_err(&pdev->dev,
	1173	+ "Request failed for reset GPIO: %d\n", err);
	1174	+ return err;
	1175	+ }
	1176	+ tegra_phy->reset_gpio = gpiod;
	1177	+
	1178	+ phy = devm_otg_ulpi_create(&pdev->dev,
	1179	+ &ulpi_viewport_access_ops, 0);
	1180	+ if (!phy) {
	1181	+ dev_err(&pdev->dev, "Failed to create ULPI OTG\n");
	1182	+ return -ENOMEM;
	1183	+ }
	1184	+
	1185	+ tegra_phy->ulpi = phy;
	1186	+ tegra_phy->ulpi->io_priv = tegra_phy->regs + ULPI_VIEWPORT;
	1187	+ break;
	1188	+
	1189	+ default:
	1190	+ dev_err(&pdev->dev, "phy_type %u is invalid or unsupported\n",
	1191	+ phy_type);
	1192	+ return -EINVAL;
1135	1193	}
1136	1194
1137	1195	tegra_phy->u_phy.dev = &pdev->dev;
1138		- err = tegra_usb_phy_init(tegra_phy);
1139		- if (err < 0)
1140		- return err;
1141		-
1142		- tegra_phy->u_phy.set_suspend = tegra_usb_phy_suspend;
	1196	+ tegra_phy->u_phy.init = tegra_usb_phy_init;
	1197	+ tegra_phy->u_phy.shutdown = tegra_usb_phy_shutdown;
	1198	+ tegra_phy->u_phy.set_suspend = tegra_usb_phy_set_suspend;
1143	1199
1144	1200	platform_set_drvdata(pdev, tegra_phy);
1145	1201
1146		- err = usb_add_phy_dev(&tegra_phy->u_phy);
1147		- if (err < 0) {
1148		- tegra_usb_phy_close(tegra_phy);
1149		- return err;
1150		- }
1151		-
1152		- return 0;
	1202	+ return usb_add_phy_dev(&tegra_phy->u_phy);
1153	1203	}
1154	1204
1155	1205	static int tegra_usb_phy_remove(struct platform_device *pdev)
..	..	@@ -1157,7 +1207,6 @@
1157	1207	struct tegra_usb_phy *tegra_phy = platform_get_drvdata(pdev);
1158	1208
1159	1209	usb_remove_phy(&tegra_phy->u_phy);
1160		- tegra_usb_phy_close(tegra_phy);
1161	1210
1162	1211	return 0;
1163	1212	}