.. | .. |
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427 | 427 | return -EBUSY; |
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428 | 428 | |
---|
429 | 429 | if (port->flags & UPF_IOREMAP) { |
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430 | | - port->membase = devm_ioremap_nocache(port->dev, port->mapbase, |
---|
| 430 | + port->membase = devm_ioremap(port->dev, port->mapbase, |
---|
431 | 431 | resource_size(res)); |
---|
432 | 432 | if (!port->membase) |
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433 | 433 | return -EBUSY; |
---|
.. | .. |
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662 | 662 | } |
---|
663 | 663 | |
---|
664 | 664 | irq = platform_get_irq(pdev, 0); |
---|
665 | | - if (irq < 0) { |
---|
666 | | - dev_err(&pdev->dev, "could not get irq\n"); |
---|
| 665 | + if (irq < 0) |
---|
667 | 666 | return irq; |
---|
668 | | - } |
---|
669 | 667 | |
---|
670 | 668 | if (owl_uart_ports[pdev->id]) { |
---|
671 | 669 | dev_err(&pdev->dev, "port %d already allocated\n", pdev->id); |
---|
.. | .. |
---|
682 | 680 | return PTR_ERR(owl_port->clk); |
---|
683 | 681 | } |
---|
684 | 682 | |
---|
| 683 | + ret = clk_prepare_enable(owl_port->clk); |
---|
| 684 | + if (ret) { |
---|
| 685 | + dev_err(&pdev->dev, "could not enable clk\n"); |
---|
| 686 | + return ret; |
---|
| 687 | + } |
---|
| 688 | + |
---|
685 | 689 | owl_port->port.dev = &pdev->dev; |
---|
686 | 690 | owl_port->port.line = pdev->id; |
---|
687 | 691 | owl_port->port.type = PORT_OWL; |
---|
.. | .. |
---|
691 | 695 | owl_port->port.uartclk = clk_get_rate(owl_port->clk); |
---|
692 | 696 | if (owl_port->port.uartclk == 0) { |
---|
693 | 697 | dev_err(&pdev->dev, "clock rate is zero\n"); |
---|
| 698 | + clk_disable_unprepare(owl_port->clk); |
---|
694 | 699 | return -EINVAL; |
---|
695 | 700 | } |
---|
696 | 701 | owl_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_LOW_LATENCY; |
---|
.. | .. |
---|
714 | 719 | |
---|
715 | 720 | uart_remove_one_port(&owl_uart_driver, &owl_port->port); |
---|
716 | 721 | owl_uart_ports[pdev->id] = NULL; |
---|
| 722 | + clk_disable_unprepare(owl_port->clk); |
---|
717 | 723 | |
---|
718 | 724 | return 0; |
---|
719 | 725 | } |
---|