.. | .. |
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23 | 23 | #include <linux/nmi.h> |
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24 | 24 | #include <linux/io.h> |
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25 | 25 | #include <linux/irq.h> |
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26 | | -#include <linux/gpio.h> |
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27 | 26 | #include <linux/of.h> |
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28 | | -#include <mach/platform.h> |
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29 | | -#include <mach/hardware.h> |
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| 27 | +#include <linux/sizes.h> |
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| 28 | +#include <linux/soc/nxp/lpc32xx-misc.h> |
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30 | 29 | |
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31 | 30 | /* |
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32 | 31 | * High Speed UART register offsets |
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.. | .. |
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80 | 79 | #define LPC32XX_HSU_TX_TL4B (0x1 << 0) |
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81 | 80 | #define LPC32XX_HSU_TX_TL8B (0x2 << 0) |
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82 | 81 | #define LPC32XX_HSU_TX_TL16B (0x3 << 0) |
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| 82 | + |
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| 83 | +#define LPC32XX_MAIN_OSC_FREQ 13000000 |
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83 | 84 | |
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84 | 85 | #define MODNAME "lpc32xx_hsuart" |
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85 | 86 | |
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.. | .. |
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169 | 170 | |
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170 | 171 | if (options) |
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171 | 172 | uart_parse_options(options, &baud, &parity, &bits, &flow); |
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| 173 | + |
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| 174 | + lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */ |
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172 | 175 | |
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173 | 176 | return uart_set_options(port, co, baud, parity, bits, flow); |
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174 | 177 | } |
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.. | .. |
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341 | 344 | LPC32XX_HSUART_IIR(port->membase)); |
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342 | 345 | port->icount.overrun++; |
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343 | 346 | tty_insert_flip_char(tport, 0, TTY_OVERRUN); |
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344 | | - tty_schedule_flip(tport); |
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| 347 | + tty_flip_buffer_push(tport); |
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345 | 348 | } |
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346 | 349 | |
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347 | 350 | /* Data received? */ |
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.. | .. |
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433 | 436 | tmp &= ~LPC32XX_HSU_BREAK; |
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434 | 437 | writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); |
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435 | 438 | spin_unlock_irqrestore(&port->lock, flags); |
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436 | | -} |
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437 | | - |
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438 | | -/* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */ |
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439 | | -static void lpc32xx_loopback_set(resource_size_t mapbase, int state) |
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440 | | -{ |
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441 | | - int bit; |
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442 | | - u32 tmp; |
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443 | | - |
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444 | | - switch (mapbase) { |
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445 | | - case LPC32XX_HS_UART1_BASE: |
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446 | | - bit = 0; |
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447 | | - break; |
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448 | | - case LPC32XX_HS_UART2_BASE: |
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449 | | - bit = 1; |
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450 | | - break; |
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451 | | - case LPC32XX_HS_UART7_BASE: |
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452 | | - bit = 6; |
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453 | | - break; |
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454 | | - default: |
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455 | | - WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase); |
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456 | | - return; |
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457 | | - } |
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458 | | - |
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459 | | - tmp = readl(LPC32XX_UARTCTL_CLOOP); |
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460 | | - if (state) |
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461 | | - tmp |= (1 << bit); |
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462 | | - else |
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463 | | - tmp &= ~(1 << bit); |
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464 | | - writel(tmp, LPC32XX_UARTCTL_CLOOP); |
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465 | 439 | } |
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466 | 440 | |
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467 | 441 | /* port->lock is not held. */ |
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.. | .. |
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683 | 657 | p->port.membase = NULL; |
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684 | 658 | |
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685 | 659 | ret = platform_get_irq(pdev, 0); |
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686 | | - if (ret < 0) { |
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687 | | - dev_err(&pdev->dev, "Error getting irq for HS UART port %d\n", |
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688 | | - uarts_registered); |
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| 660 | + if (ret < 0) |
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689 | 661 | return ret; |
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690 | | - } |
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691 | 662 | p->port.irq = ret; |
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692 | 663 | |
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693 | 664 | p->port.iotype = UPIO_MEM32; |
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