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2024-02-19 1c055e55a242a33e574e48be530e06770a210dcd 
 kernel/drivers/thermal/mtk_thermal.c
....@@ -1,18 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (c) 2015 MediaTek Inc.
34  * Author: Hanyi Wu <hanyi.wu@mediatek.com>
45  *         Sascha Hauer <s.hauer@pengutronix.de>
56  *         Dawei Chien <dawei.chien@mediatek.com>
67  *         Louis Yu <louis.yu@mediatek.com>
7
- *
8
- * This program is free software; you can redistribute it and/or modify
9
- * it under the terms of the GNU General Public License version 2 as
10
- * published by the Free Software Foundation.
11
- *
12
- * This program is distributed in the hope that it will be useful,
13
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
14
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
- * GNU General Public License for more details.
168  */
179 
1810 #include <linux/clk.h>
....@@ -46,6 +38,7 @@
4638 #define TEMP_MONIDET0		0x014
4739 #define TEMP_MONIDET1		0x018
4840 #define TEMP_MSRCTL0		0x038
41
+#define TEMP_MSRCTL1		0x03c
4942 #define TEMP_AHBPOLL		0x040
5043 #define TEMP_AHBTO		0x044
5144 #define TEMP_ADCPNP0		0x048
....@@ -70,6 +63,15 @@
7063 #define TEMP_MSR3		0x0B8
7164 
7265 #define TEMP_SPARE0		0x0f0
66
+
67
+#define TEMP_ADCPNP0_1          0x148
68
+#define TEMP_ADCPNP1_1          0x14c
69
+#define TEMP_ADCPNP2_1          0x150
70
+#define TEMP_MSR0_1             0x190
71
+#define TEMP_MSR1_1             0x194
72
+#define TEMP_MSR2_1             0x198
73
+#define TEMP_ADCPNP3_1          0x1b4
74
+#define TEMP_MSR3_1             0x1B8
7375 
7476 #define PTPCORESEL		0x400
7577 
....@@ -105,24 +107,61 @@
105107 /* The number of sensing points per bank */
106108 #define MT8173_NUM_SENSORS_PER_ZONE	4
107109 
110
+/* The number of controller in the MT8173 */
111
+#define MT8173_NUM_CONTROLLER		1
112
+
113
+/* The calibration coefficient of sensor  */
114
+#define MT8173_CALIBRATION	165
115
+
108116 /*
109117  * Layout of the fuses providing the calibration data
110
- * These macros could be used for MT8173, MT2701, and MT2712.
118
+ * These macros could be used for MT8183, MT8173, MT2701, and MT2712.
119
+ * MT8183 has 6 sensors and needs 6 VTS calibration data.
111120  * MT8173 has 5 sensors and needs 5 VTS calibration data.
112121  * MT2701 has 3 sensors and needs 3 VTS calibration data.
113122  * MT2712 has 4 sensors and needs 4 VTS calibration data.
114123  */
115
-#define MT8173_CALIB_BUF0_VALID		BIT(0)
116
-#define MT8173_CALIB_BUF1_ADC_GE(x)	(((x) >> 22) & 0x3ff)
117
-#define MT8173_CALIB_BUF0_VTS_TS1(x)	(((x) >> 17) & 0x1ff)
118
-#define MT8173_CALIB_BUF0_VTS_TS2(x)	(((x) >> 8) & 0x1ff)
119
-#define MT8173_CALIB_BUF1_VTS_TS3(x)	(((x) >> 0) & 0x1ff)
120
-#define MT8173_CALIB_BUF2_VTS_TS4(x)	(((x) >> 23) & 0x1ff)
121
-#define MT8173_CALIB_BUF2_VTS_TSABB(x)	(((x) >> 14) & 0x1ff)
122
-#define MT8173_CALIB_BUF0_DEGC_CALI(x)	(((x) >> 1) & 0x3f)
123
-#define MT8173_CALIB_BUF0_O_SLOPE(x)	(((x) >> 26) & 0x3f)
124
-#define MT8173_CALIB_BUF0_O_SLOPE_SIGN(x)	(((x) >> 7) & 0x1)
125
-#define MT8173_CALIB_BUF1_ID(x)	(((x) >> 9) & 0x1)
124
+#define CALIB_BUF0_VALID_V1		BIT(0)
125
+#define CALIB_BUF1_ADC_GE_V1(x)		(((x) >> 22) & 0x3ff)
126
+#define CALIB_BUF0_VTS_TS1_V1(x)	(((x) >> 17) & 0x1ff)
127
+#define CALIB_BUF0_VTS_TS2_V1(x)	(((x) >> 8) & 0x1ff)
128
+#define CALIB_BUF1_VTS_TS3_V1(x)	(((x) >> 0) & 0x1ff)
129
+#define CALIB_BUF2_VTS_TS4_V1(x)	(((x) >> 23) & 0x1ff)
130
+#define CALIB_BUF2_VTS_TS5_V1(x)	(((x) >> 5) & 0x1ff)
131
+#define CALIB_BUF2_VTS_TSABB_V1(x)	(((x) >> 14) & 0x1ff)
132
+#define CALIB_BUF0_DEGC_CALI_V1(x)	(((x) >> 1) & 0x3f)
133
+#define CALIB_BUF0_O_SLOPE_V1(x)	(((x) >> 26) & 0x3f)
134
+#define CALIB_BUF0_O_SLOPE_SIGN_V1(x)	(((x) >> 7) & 0x1)
135
+#define CALIB_BUF1_ID_V1(x)		(((x) >> 9) & 0x1)
136
+
137
+/*
138
+ * Layout of the fuses providing the calibration data
139
+ * These macros could be used for MT7622.
140
+ */
141
+#define CALIB_BUF0_ADC_OE_V2(x)		(((x) >> 22) & 0x3ff)
142
+#define CALIB_BUF0_ADC_GE_V2(x)		(((x) >> 12) & 0x3ff)
143
+#define CALIB_BUF0_DEGC_CALI_V2(x)	(((x) >> 6) & 0x3f)
144
+#define CALIB_BUF0_O_SLOPE_V2(x)	(((x) >> 0) & 0x3f)
145
+#define CALIB_BUF1_VTS_TS1_V2(x)	(((x) >> 23) & 0x1ff)
146
+#define CALIB_BUF1_VTS_TS2_V2(x)	(((x) >> 14) & 0x1ff)
147
+#define CALIB_BUF1_VTS_TSABB_V2(x)	(((x) >> 5) & 0x1ff)
148
+#define CALIB_BUF1_VALID_V2(x)		(((x) >> 4) & 0x1)
149
+#define CALIB_BUF1_O_SLOPE_SIGN_V2(x)	(((x) >> 3) & 0x1)
150
+
151
+enum {
152
+	VTS1,
153
+	VTS2,
154
+	VTS3,
155
+	VTS4,
156
+	VTS5,
157
+	VTSABB,
158
+	MAX_NUM_VTS,
159
+};
160
+
161
+enum mtk_thermal_version {
162
+	MTK_THERMAL_V1 = 1,
163
+	MTK_THERMAL_V2,
164
+};
126165 
127166 /* MT2701 thermal sensors */
128167 #define MT2701_TS1	0
....@@ -137,6 +176,12 @@
137176 
138177 /* The number of sensing points per bank */
139178 #define MT2701_NUM_SENSORS_PER_ZONE	3
179
+
180
+/* The number of controller in the MT2701 */
181
+#define MT2701_NUM_CONTROLLER		1
182
+
183
+/* The calibration coefficient of sensor  */
184
+#define MT2701_CALIBRATION	165
140185 
141186 /* MT2712 thermal sensors */
142187 #define MT2712_TS1	0
....@@ -153,11 +198,50 @@
153198 /* The number of sensing points per bank */
154199 #define MT2712_NUM_SENSORS_PER_ZONE	4
155200 
201
+/* The number of controller in the MT2712 */
202
+#define MT2712_NUM_CONTROLLER		1
203
+
204
+/* The calibration coefficient of sensor  */
205
+#define MT2712_CALIBRATION	165
206
+
156207 #define MT7622_TEMP_AUXADC_CHANNEL	11
157208 #define MT7622_NUM_SENSORS		1
158209 #define MT7622_NUM_ZONES		1
159210 #define MT7622_NUM_SENSORS_PER_ZONE	1
160211 #define MT7622_TS1	0
212
+#define MT7622_NUM_CONTROLLER		1
213
+
214
+/* The maximum number of banks */
215
+#define MAX_NUM_ZONES		8
216
+
217
+/* The calibration coefficient of sensor  */
218
+#define MT7622_CALIBRATION	165
219
+
220
+/* MT8183 thermal sensors */
221
+#define MT8183_TS1	0
222
+#define MT8183_TS2	1
223
+#define MT8183_TS3	2
224
+#define MT8183_TS4	3
225
+#define MT8183_TS5	4
226
+#define MT8183_TSABB	5
227
+
228
+/* AUXADC channel  is used for the temperature sensors */
229
+#define MT8183_TEMP_AUXADC_CHANNEL	11
230
+
231
+/* The total number of temperature sensors in the MT8183 */
232
+#define MT8183_NUM_SENSORS	6
233
+
234
+/* The number of banks in the MT8183 */
235
+#define MT8183_NUM_ZONES               1
236
+
237
+/* The number of sensing points per bank */
238
+#define MT8183_NUM_SENSORS_PER_ZONE	 6
239
+
240
+/* The number of controller in the MT8183 */
241
+#define MT8183_NUM_CONTROLLER		2
242
+
243
+/* The calibration coefficient of sensor  */
244
+#define MT8183_CALIBRATION	153
161245 
162246 struct mtk_thermal;
163247 
....@@ -175,10 +259,16 @@
175259 	s32 num_banks;
176260 	s32 num_sensors;
177261 	s32 auxadc_channel;
262
+	const int *vts_index;
178263 	const int *sensor_mux_values;
179264 	const int *msr;
180265 	const int *adcpnp;
181
-	struct thermal_bank_cfg bank_data[];
266
+	const int cali_val;
267
+	const int num_controller;
268
+	const int *controller_offset;
269
+	bool need_switch_bank;
270
+	struct thermal_bank_cfg bank_data[MAX_NUM_ZONES];
271
+	enum mtk_thermal_version version;
182272 };
183273 
184274 struct mtk_thermal {
....@@ -192,12 +282,35 @@
192282 
193283 	/* Calibration values */
194284 	s32 adc_ge;
285
+	s32 adc_oe;
195286 	s32 degc_cali;
196287 	s32 o_slope;
197
-	s32 vts[MT8173_NUM_SENSORS];
288
+	s32 o_slope_sign;
289
+	s32 vts[MAX_NUM_VTS];
198290 
199291 	const struct mtk_thermal_data *conf;
200
-	struct mtk_thermal_bank banks[];
292
+	struct mtk_thermal_bank banks[MAX_NUM_ZONES];
293
+};
294
+
295
+/* MT8183 thermal sensor data */
296
+static const int mt8183_bank_data[MT8183_NUM_SENSORS] = {
297
+	MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB
298
+};
299
+
300
+static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = {
301
+	TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1
302
+};
303
+
304
+static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = {
305
+	TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1,
306
+	TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1
307
+};
308
+
309
+static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 };
310
+static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100};
311
+
312
+static const int mt8183_vts_index[MT8183_NUM_SENSORS] = {
313
+	VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB
201314 };
202315 
203316 /* MT8173 thermal sensor data */
....@@ -217,6 +330,11 @@
217330 };
218331 
219332 static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
333
+static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, };
334
+
335
+static const int mt8173_vts_index[MT8173_NUM_SENSORS] = {
336
+	VTS1, VTS2, VTS3, VTS4, VTSABB
337
+};
220338 
221339 /* MT2701 thermal sensor data */
222340 static const int mt2701_bank_data[MT2701_NUM_SENSORS] = {
....@@ -232,6 +350,11 @@
232350 };
233351 
234352 static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 };
353
+static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, };
354
+
355
+static const int mt2701_vts_index[MT2701_NUM_SENSORS] = {
356
+	VTS1, VTS2, VTS3
357
+};
235358 
236359 /* MT2712 thermal sensor data */
237360 static const int mt2712_bank_data[MT2712_NUM_SENSORS] = {
....@@ -247,14 +370,21 @@
247370 };
248371 
249372 static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 };
373
+static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, };
374
+
375
+static const int mt2712_vts_index[MT2712_NUM_SENSORS] = {
376
+	VTS1, VTS2, VTS3, VTS4
377
+};
250378 
251379 /* MT7622 thermal sensor data */
252380 static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, };
253381 static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
254382 static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
255383 static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, };
384
+static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
385
+static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
256386 
257
-/**
387
+/*
258388  * The MT8173 thermal controller has four banks. Each bank can read up to
259389  * four temperature sensors simultaneously. The MT8173 has a total of 5
260390  * temperature sensors. We use each bank to measure a certain area of the
....@@ -271,6 +401,11 @@
271401 	.auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL,
272402 	.num_banks = MT8173_NUM_ZONES,
273403 	.num_sensors = MT8173_NUM_SENSORS,
404
+	.vts_index = mt8173_vts_index,
405
+	.cali_val = MT8173_CALIBRATION,
406
+	.num_controller = MT8173_NUM_CONTROLLER,
407
+	.controller_offset = mt8173_tc_offset,
408
+	.need_switch_bank = true,
274409 	.bank_data = {
275410 		{
276411 			.num_sensors = 2,
....@@ -289,9 +424,10 @@
289424 	.msr = mt8173_msr,
290425 	.adcpnp = mt8173_adcpnp,
291426 	.sensor_mux_values = mt8173_mux_values,
427
+	.version = MTK_THERMAL_V1,
292428 };
293429 
294
-/**
430
+/*
295431  * The MT2701 thermal controller has one bank, which can read up to
296432  * three temperature sensors simultaneously. The MT2701 has a total of 3
297433  * temperature sensors.
....@@ -305,6 +441,11 @@
305441 	.auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL,
306442 	.num_banks = 1,
307443 	.num_sensors = MT2701_NUM_SENSORS,
444
+	.vts_index = mt2701_vts_index,
445
+	.cali_val = MT2701_CALIBRATION,
446
+	.num_controller = MT2701_NUM_CONTROLLER,
447
+	.controller_offset = mt2701_tc_offset,
448
+	.need_switch_bank = true,
308449 	.bank_data = {
309450 		{
310451 			.num_sensors = 3,
....@@ -314,9 +455,10 @@
314455 	.msr = mt2701_msr,
315456 	.adcpnp = mt2701_adcpnp,
316457 	.sensor_mux_values = mt2701_mux_values,
458
+	.version = MTK_THERMAL_V1,
317459 };
318460 
319
-/**
461
+/*
320462  * The MT2712 thermal controller has one bank, which can read up to
321463  * four temperature sensors simultaneously. The MT2712 has a total of 4
322464  * temperature sensors.
....@@ -330,6 +472,11 @@
330472 	.auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL,
331473 	.num_banks = 1,
332474 	.num_sensors = MT2712_NUM_SENSORS,
475
+	.vts_index = mt2712_vts_index,
476
+	.cali_val = MT2712_CALIBRATION,
477
+	.num_controller = MT2712_NUM_CONTROLLER,
478
+	.controller_offset = mt2712_tc_offset,
479
+	.need_switch_bank = true,
333480 	.bank_data = {
334481 		{
335482 			.num_sensors = 4,
....@@ -339,6 +486,7 @@
339486 	.msr = mt2712_msr,
340487 	.adcpnp = mt2712_adcpnp,
341488 	.sensor_mux_values = mt2712_mux_values,
489
+	.version = MTK_THERMAL_V1,
342490 };
343491 
344492 /*
....@@ -349,6 +497,11 @@
349497 	.auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL,
350498 	.num_banks = MT7622_NUM_ZONES,
351499 	.num_sensors = MT7622_NUM_SENSORS,
500
+	.vts_index = mt7622_vts_index,
501
+	.cali_val = MT7622_CALIBRATION,
502
+	.num_controller = MT7622_NUM_CONTROLLER,
503
+	.controller_offset = mt7622_tc_offset,
504
+	.need_switch_bank = true,
352505 	.bank_data = {
353506 		{
354507 			.num_sensors = 1,
....@@ -358,29 +511,94 @@
358511 	.msr = mt7622_msr,
359512 	.adcpnp = mt7622_adcpnp,
360513 	.sensor_mux_values = mt7622_mux_values,
514
+	.version = MTK_THERMAL_V2,
515
+};
516
+
517
+/*
518
+ * The MT8183 thermal controller has one bank for the current SW framework.
519
+ * The MT8183 has a total of 6 temperature sensors.
520
+ * There are two thermal controller to control the six sensor.
521
+ * The first one bind 2 sensor, and the other bind 4 sensors.
522
+ * The thermal core only gets the maximum temperature of all sensor, so
523
+ * the bank concept wouldn't be necessary here. However, the SVS (Smart
524
+ * Voltage Scaling) unit makes its decisions based on the same bank
525
+ * data, and this indeed needs the temperatures of the individual banks
526
+ * for making better decisions.
527
+ */
528
+static const struct mtk_thermal_data mt8183_thermal_data = {
529
+	.auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL,
530
+	.num_banks = MT8183_NUM_ZONES,
531
+	.num_sensors = MT8183_NUM_SENSORS,
532
+	.vts_index = mt8183_vts_index,
533
+	.cali_val = MT8183_CALIBRATION,
534
+	.num_controller = MT8183_NUM_CONTROLLER,
535
+	.controller_offset = mt8183_tc_offset,
536
+	.need_switch_bank = false,
537
+	.bank_data = {
538
+		{
539
+			.num_sensors = 6,
540
+			.sensors = mt8183_bank_data,
541
+		},
542
+	},
543
+
544
+	.msr = mt8183_msr,
545
+	.adcpnp = mt8183_adcpnp,
546
+	.sensor_mux_values = mt8183_mux_values,
547
+	.version = MTK_THERMAL_V1,
361548 };
362549 
363550 /**
364551  * raw_to_mcelsius - convert a raw ADC value to mcelsius
365
- * @mt:		The thermal controller
552
+ * @mt:	The thermal controller
553
+ * @sensno:	sensor number
366554  * @raw:	raw ADC value
367555  *
368556  * This converts the raw ADC value to mcelsius using the SoC specific
369557  * calibration constants
370558  */
371
-static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw)
559
+static int raw_to_mcelsius_v1(struct mtk_thermal *mt, int sensno, s32 raw)
372560 {
373561 	s32 tmp;
374562 
375563 	raw &= 0xfff;
376564 
377565 	tmp = 203450520 << 3;
378
-	tmp /= 165 + mt->o_slope;
566
+	tmp /= mt->conf->cali_val + mt->o_slope;
379567 	tmp /= 10000 + mt->adc_ge;
380568 	tmp *= raw - mt->vts[sensno] - 3350;
381569 	tmp >>= 3;
382570 
383571 	return mt->degc_cali * 500 - tmp;
572
+}
573
+
574
+static int raw_to_mcelsius_v2(struct mtk_thermal *mt, int sensno, s32 raw)
575
+{
576
+	s32 format_1 = 0;
577
+	s32 format_2 = 0;
578
+	s32 g_oe = 1;
579
+	s32 g_gain = 1;
580
+	s32 g_x_roomt = 0;
581
+	s32 tmp = 0;
582
+
583
+	if (raw == 0)
584
+		return 0;
585
+
586
+	raw &= 0xfff;
587
+	g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12);
588
+	g_oe = mt->adc_oe - 512;
589
+	format_1 = mt->vts[VTS2] + 3105 - g_oe;
590
+	format_2 = (mt->degc_cali * 10) >> 1;
591
+	g_x_roomt = (((format_1 * 10000) >> 12) * 10000) / g_gain;
592
+
593
+	tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt;
594
+	tmp = tmp * 10 * 100 / 11;
595
+
596
+	if (mt->o_slope_sign == 0)
597
+		tmp = tmp / (165 - mt->o_slope);
598
+	else
599
+		tmp = tmp / (165 + mt->o_slope);
600
+
601
+	return (format_2 - tmp) * 100;
384602 }
385603 
386604 /**
....@@ -395,12 +613,14 @@
395613 	struct mtk_thermal *mt = bank->mt;
396614 	u32 val;
397615 
398
-	mutex_lock(&mt->lock);
616
+	if (mt->conf->need_switch_bank) {
617
+		mutex_lock(&mt->lock);
399618 
400
-	val = readl(mt->thermal_base + PTPCORESEL);
401
-	val &= ~0xf;
402
-	val |= bank->id;
403
-	writel(val, mt->thermal_base + PTPCORESEL);
619
+		val = readl(mt->thermal_base + PTPCORESEL);
620
+		val &= ~0xf;
621
+		val |= bank->id;
622
+		writel(val, mt->thermal_base + PTPCORESEL);
623
+	}
404624 }
405625 
406626 /**
....@@ -413,7 +633,8 @@
413633 {
414634 	struct mtk_thermal *mt = bank->mt;
415635 
416
-	mutex_unlock(&mt->lock);
636
+	if (mt->conf->need_switch_bank)
637
+		mutex_unlock(&mt->lock);
417638 }
418639 
419640 /**
....@@ -433,9 +654,13 @@
433654 	for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
434655 		raw = readl(mt->thermal_base + conf->msr[i]);
435656 
436
-		temp = raw_to_mcelsius(mt,
437
-				       conf->bank_data[bank->id].sensors[i],
438
-				       raw);
657
+		if (mt->conf->version == MTK_THERMAL_V1) {
658
+			temp = raw_to_mcelsius_v1(
659
+				mt, conf->bank_data[bank->id].sensors[i], raw);
660
+		} else {
661
+			temp = raw_to_mcelsius_v2(
662
+				mt, conf->bank_data[bank->id].sensors[i], raw);
663
+		}
439664 
440665 		/*
441666 		 * The first read of a sensor often contains very high bogus
....@@ -478,11 +703,15 @@
478703 };
479704 
480705 static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
481
-				  u32 apmixed_phys_base, u32 auxadc_phys_base)
706
+				  u32 apmixed_phys_base, u32 auxadc_phys_base,
707
+				  int ctrl_id)
482708 {
483709 	struct mtk_thermal_bank *bank = &mt->banks[num];
484710 	const struct mtk_thermal_data *conf = mt->conf;
485711 	int i;
712
+
713
+	int offset = mt->conf->controller_offset[ctrl_id];
714
+	void __iomem *controller_base = mt->thermal_base + offset;
486715 
487716 	bank->id = num;
488717 	bank->mt = mt;
....@@ -490,7 +719,7 @@
490719 	mtk_thermal_get_bank(bank);
491720 
492721 	/* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
493
-	writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1);
722
+	writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1);
494723 
495724 	/*
496725 	 * filt interval is 1 * 46.540us = 46.54us,
....@@ -498,21 +727,21 @@
498727 	 */
499728 	writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
500729 			TEMP_MONCTL2_SENSOR_INTERVAL(429),
501
-			mt->thermal_base + TEMP_MONCTL2);
730
+			controller_base + TEMP_MONCTL2);
502731 
503732 	/* poll is set to 10u */
504733 	writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
505
-	       mt->thermal_base + TEMP_AHBPOLL);
734
+	       controller_base + TEMP_AHBPOLL);
506735 
507736 	/* temperature sampling control, 1 sample */
508
-	writel(0x0, mt->thermal_base + TEMP_MSRCTL0);
737
+	writel(0x0, controller_base + TEMP_MSRCTL0);
509738 
510739 	/* exceed this polling time, IRQ would be inserted */
511
-	writel(0xffffffff, mt->thermal_base + TEMP_AHBTO);
740
+	writel(0xffffffff, controller_base + TEMP_AHBTO);
512741 
513742 	/* number of interrupts per event, 1 is enough */
514
-	writel(0x0, mt->thermal_base + TEMP_MONIDET0);
515
-	writel(0x0, mt->thermal_base + TEMP_MONIDET1);
743
+	writel(0x0, controller_base + TEMP_MONIDET0);
744
+	writel(0x0, controller_base + TEMP_MONIDET1);
516745 
517746 	/*
518747 	 * The MT8173 thermal controller does not have its own ADC. Instead it
....@@ -527,55 +756,57 @@
527756 	 * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
528757 	 * automatically by hw
529758 	 */
530
-	writel(BIT(conf->auxadc_channel), mt->thermal_base + TEMP_ADCMUX);
759
+	writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX);
531760 
532761 	/* AHB address for auxadc mux selection */
533762 	writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
534
-	       mt->thermal_base + TEMP_ADCMUXADDR);
763
+	       controller_base + TEMP_ADCMUXADDR);
535764 
536
-	/* AHB address for pnp sensor mux selection */
537
-	writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
538
-	       mt->thermal_base + TEMP_PNPMUXADDR);
765
+	if (mt->conf->version == MTK_THERMAL_V1) {
766
+		/* AHB address for pnp sensor mux selection */
767
+		writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
768
+		       controller_base + TEMP_PNPMUXADDR);
769
+	}
539770 
540771 	/* AHB value for auxadc enable */
541
-	writel(BIT(conf->auxadc_channel), mt->thermal_base + TEMP_ADCEN);
772
+	writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN);
542773 
543774 	/* AHB address for auxadc enable (channel 0 immediate mode selected) */
544775 	writel(auxadc_phys_base + AUXADC_CON1_SET_V,
545
-	       mt->thermal_base + TEMP_ADCENADDR);
776
+	       controller_base + TEMP_ADCENADDR);
546777 
547778 	/* AHB address for auxadc valid bit */
548779 	writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
549
-	       mt->thermal_base + TEMP_ADCVALIDADDR);
780
+	       controller_base + TEMP_ADCVALIDADDR);
550781 
551782 	/* AHB address for auxadc voltage output */
552783 	writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
553
-	       mt->thermal_base + TEMP_ADCVOLTADDR);
784
+	       controller_base + TEMP_ADCVOLTADDR);
554785 
555786 	/* read valid & voltage are at the same register */
556
-	writel(0x0, mt->thermal_base + TEMP_RDCTRL);
787
+	writel(0x0, controller_base + TEMP_RDCTRL);
557788 
558789 	/* indicate where the valid bit is */
559790 	writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
560
-	       mt->thermal_base + TEMP_ADCVALIDMASK);
791
+	       controller_base + TEMP_ADCVALIDMASK);
561792 
562793 	/* no shift */
563
-	writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT);
794
+	writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);
564795 
565796 	/* enable auxadc mux write transaction */
566797 	writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
567
-	       mt->thermal_base + TEMP_ADCWRITECTRL);
798
+		controller_base + TEMP_ADCWRITECTRL);
568799 
569800 	for (i = 0; i < conf->bank_data[num].num_sensors; i++)
570801 		writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]],
571802 		       mt->thermal_base + conf->adcpnp[i]);
572803 
573804 	writel((1 << conf->bank_data[num].num_sensors) - 1,
574
-	       mt->thermal_base + TEMP_MONCTL0);
805
+	       controller_base + TEMP_MONCTL0);
575806 
576807 	writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
577808 	       TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
578
-	       mt->thermal_base + TEMP_ADCWRITECTRL);
809
+	       controller_base + TEMP_ADCWRITECTRL);
579810 
580811 	mtk_thermal_put_bank(bank);
581812 }
....@@ -590,6 +821,68 @@
590821 		return OF_BAD_ADDR;
591822 
592823 	return of_translate_address(np, regaddr_p);
824
+}
825
+
826
+static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf)
827
+{
828
+	int i;
829
+
830
+	if (!(buf[0] & CALIB_BUF0_VALID_V1))
831
+		return -EINVAL;
832
+
833
+	mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]);
834
+
835
+	for (i = 0; i < mt->conf->num_sensors; i++) {
836
+		switch (mt->conf->vts_index[i]) {
837
+		case VTS1:
838
+			mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]);
839
+			break;
840
+		case VTS2:
841
+			mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]);
842
+			break;
843
+		case VTS3:
844
+			mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]);
845
+			break;
846
+		case VTS4:
847
+			mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]);
848
+			break;
849
+		case VTS5:
850
+			mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]);
851
+			break;
852
+		case VTSABB:
853
+			mt->vts[VTSABB] =
854
+				CALIB_BUF2_VTS_TSABB_V1(buf[2]);
855
+			break;
856
+		default:
857
+			break;
858
+		}
859
+	}
860
+
861
+	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]);
862
+	if (CALIB_BUF1_ID_V1(buf[1]) &
863
+	    CALIB_BUF0_O_SLOPE_SIGN_V1(buf[0]))
864
+		mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]);
865
+	else
866
+		mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]);
867
+
868
+	return 0;
869
+}
870
+
871
+static int mtk_thermal_extract_efuse_v2(struct mtk_thermal *mt, u32 *buf)
872
+{
873
+	if (!CALIB_BUF1_VALID_V2(buf[1]))
874
+		return -EINVAL;
875
+
876
+	mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]);
877
+	mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]);
878
+	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]);
879
+	mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]);
880
+	mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]);
881
+	mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]);
882
+	mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]);
883
+	mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]);
884
+
885
+	return 0;
593886 }
594887 
595888 static int mtk_thermal_get_calibration_data(struct device *dev,
....@@ -627,21 +920,14 @@
627920 		goto out;
628921 	}
629922 
630
-	if (buf[0] & MT8173_CALIB_BUF0_VALID) {
631
-		mt->adc_ge = MT8173_CALIB_BUF1_ADC_GE(buf[1]);
632
-		mt->vts[MT8173_TS1] = MT8173_CALIB_BUF0_VTS_TS1(buf[0]);
633
-		mt->vts[MT8173_TS2] = MT8173_CALIB_BUF0_VTS_TS2(buf[0]);
634
-		mt->vts[MT8173_TS3] = MT8173_CALIB_BUF1_VTS_TS3(buf[1]);
635
-		mt->vts[MT8173_TS4] = MT8173_CALIB_BUF2_VTS_TS4(buf[2]);
636
-		mt->vts[MT8173_TSABB] = MT8173_CALIB_BUF2_VTS_TSABB(buf[2]);
637
-		mt->degc_cali = MT8173_CALIB_BUF0_DEGC_CALI(buf[0]);
638
-		if (MT8173_CALIB_BUF1_ID(buf[1]) &
639
-		    MT8173_CALIB_BUF0_O_SLOPE_SIGN(buf[0]))
640
-			mt->o_slope = -MT8173_CALIB_BUF0_O_SLOPE(buf[0]);
641
-		else
642
-			mt->o_slope = MT8173_CALIB_BUF0_O_SLOPE(buf[0]);
643
-	} else {
923
+	if (mt->conf->version == MTK_THERMAL_V1)
924
+		ret = mtk_thermal_extract_efuse_v1(mt, buf);
925
+	else
926
+		ret = mtk_thermal_extract_efuse_v2(mt, buf);
927
+
928
+	if (ret) {
644929 		dev_info(dev, "Device not calibrated, using default calibration values\n");
930
+		ret = 0;
645931 	}
646932 
647933 out:
....@@ -666,19 +952,46 @@
666952 	{
667953 		.compatible = "mediatek,mt7622-thermal",
668954 		.data = (void *)&mt7622_thermal_data,
955
+	},
956
+	{
957
+		.compatible = "mediatek,mt8183-thermal",
958
+		.data = (void *)&mt8183_thermal_data,
669959 	}, {
670960 	},
671961 };
672962 MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
673963 
964
+static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base)
965
+{
966
+	int tmp;
967
+
968
+	tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1);
969
+	tmp &= ~(0x37);
970
+	tmp |= 0x1;
971
+	writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1);
972
+	udelay(200);
973
+}
974
+
975
+static void mtk_thermal_release_periodic_ts(struct mtk_thermal *mt,
976
+					    void __iomem *auxadc_base)
977
+{
978
+	int tmp;
979
+
980
+	writel(0x800, auxadc_base + AUXADC_CON1_SET_V);
981
+	writel(0x1, mt->thermal_base + TEMP_MONCTL0);
982
+	tmp = readl(mt->thermal_base + TEMP_MSRCTL1);
983
+	writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1);
984
+}
985
+
674986 static int mtk_thermal_probe(struct platform_device *pdev)
675987 {
676
-	int ret, i;
988
+	int ret, i, ctrl_id;
677989 	struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
678990 	struct mtk_thermal *mt;
679991 	struct resource *res;
680992 	u64 auxadc_phys_base, apmixed_phys_base;
681993 	struct thermal_zone_device *tzdev;
994
+	void __iomem *apmixed_base, *auxadc_base;
682995 
683996 	mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
684997 	if (!mt)
....@@ -713,6 +1026,7 @@
7131026 		return -ENODEV;
7141027 	}
7151028 
1029
+	auxadc_base = of_iomap(auxadc, 0);
7161030 	auxadc_phys_base = of_get_phys_base(auxadc);
7171031 
7181032 	of_node_put(auxadc);
....@@ -728,6 +1042,7 @@
7281042 		return -ENODEV;
7291043 	}
7301044 
1045
+	apmixed_base = of_iomap(apmixedsys, 0);
7311046 	apmixed_phys_base = of_get_phys_base(apmixedsys);
7321047 
7331048 	of_node_put(apmixedsys);
....@@ -753,9 +1068,15 @@
7531068 		goto err_disable_clk_auxadc;
7541069 	}
7551070 
756
-	for (i = 0; i < mt->conf->num_banks; i++)
757
-		mtk_thermal_init_bank(mt, i, apmixed_phys_base,
758
-				      auxadc_phys_base);
1071
+	if (mt->conf->version == MTK_THERMAL_V2) {
1072
+		mtk_thermal_turn_on_buffer(apmixed_base);
1073
+		mtk_thermal_release_periodic_ts(mt, auxadc_base);
1074
+	}
1075
+
1076
+	for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
1077
+		for (i = 0; i < mt->conf->num_banks; i++)
1078
+			mtk_thermal_init_bank(mt, i, apmixed_phys_base,
1079
+					      auxadc_phys_base, ctrl_id);
7591080 
7601081 	platform_set_drvdata(pdev, mt);
7611082 
....@@ -797,6 +1118,7 @@
7971118 
7981119 module_platform_driver(mtk_thermal_driver);
7991120 
1121
+MODULE_AUTHOR("Michael Kao <michael.kao@mediatek.com>");
8001122 MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>");
8011123 MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>");
8021124 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");