add r8169 read mac form eeprom

hc

2024-02-19 1c055e55a242a33e574e48be530e06770a210dcd

 kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/spid.h
..
..
@@ -1,15 +1,16 @@
1
-/* SPDX-License-Identifier: GPL-2.0 */
2
1
 /*
3
2
  * SPI device spec header file
4
3
  *
5
- * Copyright (C) 1999-2019, Broadcom Corporation
6
- * 
4
+ * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation
5
+ *
6
+ * Copyright (C) 1999-2017, Broadcom Corporation
7
+ *
7
8
  *      Unless you and Broadcom execute a separate written software license
8
9
  * agreement governing use of this software, this software is licensed to you
9
10
  * under the terms of the GNU General Public License version 2 (the "GPL"),
10
11
  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
11
12
  * following added to such license:
12
- * 
13
+ *
13
14
  *      As a special exception, the copyright holders of this software give you
14
15
  * permission to link this software with independent modules, and to copy and
15
16
  * distribute the resulting executable under terms of your choice, provided that
..
..
@@ -17,7 +18,7 @@
17
18
  * the license of that module.  An independent module is a module which is not
18
19
  * derived from this software.  The special exception does not apply to any
19
20
  * modifications of the software.
20
- * 
21
+ *
21
22
  *      Notwithstanding the above, under no circumstances may you combine this
22
23
  * software in any way with any other Broadcom software provided under a license
23
24
  * other than the GPL, without Broadcom's express prior written consent.
..
..
@@ -100,6 +101,10 @@
100
101
 #define RESET_ON_BT_BP_RESET	0x8	/* enable reset for BT backplane */
101
102
 #define RESET_SPI		0x80	/* reset the above enabled logic */
102
103
 
104
+/* Bit mask for card capability */
105
+#define SPID_CHIPID_PRESENT		0x20	/* duplicate of cardcapability chipid present */
106
+#define SPID_SECURE_MODE		0x40	/* duplicate of cardcapability secure mode */
107
+
103
108
 /* Bit mask for SPID_INTR_REG device register */
104
109
 #define DATA_UNAVAILABLE	0x0001	/* Requested data not available; Clear by writing a "1" */
105
110
 #define F2_F3_FIFO_RD_UNDERFLOW	0x0002
..
..
@@ -163,7 +168,12 @@
163
168
 #define SPI_FUNC_2		2
164
169
 #define SPI_FUNC_3		3
165
170
 
166
-#define WAIT_F2RXFIFORDY	100
167
-#define WAIT_F2RXFIFORDY_DELAY	20
171
+#ifdef BCMQT
172
+#define WAIT_F2RXFIFORDY        200
173
+#define WAIT_F2RXFIFORDY_DELAY  100
174
+#else
175
+#define WAIT_F2RXFIFORDY        100
176
+#define WAIT_F2RXFIFORDY_DELAY  20
177
+#endif // endif
168
178
 
169
179
 #endif /* _SPI_H */