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2024-02-19 1c055e55a242a33e574e48be530e06770a210dcd 
 kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/bcmsrom_fmt.h
....@@ -1,15 +1,16 @@
1
-/* SPDX-License-Identifier: GPL-2.0 */
21 /*
32  * SROM format definition.
43  *
5
- * Copyright (C) 1999-2019, Broadcom Corporation
6
- * 
4
+ * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation
5
+ *
6
+ * Copyright (C) 1999-2017, Broadcom Corporation
7
+ *
78  *      Unless you and Broadcom execute a separate written software license
89  * agreement governing use of this software, this software is licensed to you
910  * under the terms of the GNU General Public License version 2 (the "GPL"),
1011  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
1112  * following added to such license:
12
- * 
13
+ *
1314  *      As a special exception, the copyright holders of this software give you
1415  * permission to link this software with independent modules, and to copy and
1516  * distribute the resulting executable under terms of your choice, provided that
....@@ -17,7 +18,7 @@
1718  * the license of that module.  An independent module is a module which is not
1819  * derived from this software.  The special exception does not apply to any
1920  * modifications of the software.
20
- * 
21
+ *
2122  *      Notwithstanding the above, under no circumstances may you combine this
2223  * software in any way with any other Broadcom software provided under a license
2324  * other than the GPL, without Broadcom's express prior written consent.
....@@ -25,31 +26,31 @@
2526  *
2627  * <<Broadcom-WL-IPTag/Open:>>
2728  *
28
- * $Id: bcmsrom_fmt.h 553280 2015-04-29 07:55:29Z $
29
+ * $Id: bcmsrom_fmt.h 688657 2017-03-07 10:12:56Z $
2930  */
3031 
3132 #ifndef	_bcmsrom_fmt_h_
3233 #define	_bcmsrom_fmt_h_
3334 
34
-#define SROM_MAXREV		13	/* max revision supported by driver */
35
+#define SROM_MAXREV		16	/* max revision supported by driver */
3536 
36
-/* Maximum srom: 12 Kilobits == 1536 bytes */
37
+/* Maximum srom: 16 Kilobits == 2048 bytes */
3738 
38
-#define	SROM_MAX		1536
39
-#define SROM_MAXW		594
39
+#define	SROM_MAX		2048
40
+#define SROM_MAXW		1024
4041 
4142 #ifdef LARGE_NVRAM_MAXSZ
42
-#define VARS_MAX                LARGE_NVRAM_MAXSZ
43
+#define VARS_MAX		LARGE_NVRAM_MAXSZ
4344 #else
44
-#define VARS_MAX                4096
45
+#define LARGE_NVRAM_MAXSZ	8192
46
+#define VARS_MAX		LARGE_NVRAM_MAXSZ
4547 #endif /* LARGE_NVRAM_MAXSZ */
4648 
4749 /* PCI fields */
4850 #define PCI_F0DEVID		48
4951 
50
-
5152 #define	SROM_WORDS		64
52
-
53
+#define SROM_SIGN_MINWORDS 128
5354 #define SROM3_SWRGN_OFF		28	/* s/w region offset in words */
5455 
5556 #define	SROM_SSID		2
....@@ -191,7 +192,6 @@
191192 #define SROM4_SWITCH_MASK	0xff00
192193 #define SROM4_SWITCH_SHIFT	8
193194 
194
-
195195 /* Per-path fields */
196196 #define	MAX_PATH_SROM		4
197197 #define	SROM4_PATH0		64
....@@ -231,7 +231,6 @@
231231 #define	SROM4_BWDUPPO		200
232232 
233233 #define	SROM4_CRCREV		219
234
-
235234 
236235 /* SROM Rev 8: Make space for a 48word hardware header for PCIe rev >= 6.
237236  * This is acombined srom for both MIMO and SISO boards, usable in
....@@ -300,7 +299,6 @@
300299 
301300 /* Measured power 1 & 2, 0-13 bits at offset 95, MSB 2 bits are unused for now. */
302301 #define SROM8_MPWR_1_AND_2	95
303
-
304302 
305303 /* Per-path offsets & fields */
306304 #define	SROM8_PATH0		96
....@@ -413,7 +411,6 @@
413411 
414412 #define	SROM10_WORDS		230
415413 #define	SROM10_SIGNATURE	SROM4_SIGNATURE
416
-
417414 
418415 /* SROM REV 11 */
419416 #define SROM11_BREV			65
....@@ -638,7 +635,6 @@
638635 #define	SROM11_WORDS				234
639636 #define	SROM11_SIGNATURE		0x0634
640637 
641
-
642638 /* SROM REV 12 */
643639 #define SROM12_SIGN                     64
644640 #define SROM12_WORDS			512
....@@ -811,16 +807,6 @@
811807 #define SROM12_PDOFF_20in80M_5G_B3		491
812808 #define SROM12_PDOFF_20in80M_5G_B4		492
813809 
814
-#define SROM13_PDOFFSET20IN40M5GCORE3           98
815
-#define SROM13_PDOFFSET20IN40M5GCORE3_1         99
816
-#define SROM13_PDOFFSET20IN80M5GCORE3           510
817
-#define SROM13_PDOFFSET20IN80M5GCORE3_1         511
818
-#define SROM13_PDOFFSET40IN80M5GCORE3           105
819
-#define SROM13_PDOFFSET40IN80M5GCORE3_1         106
820
-
821
-#define SROM13_PDOFFSET20IN40M2G                94
822
-#define SROM13_PDOFFSET20IN40M2GCORE3           95
823
-
824810 #define SROM12_GPDN_L				91  /* GPIO pull down bits [15:0]  */
825811 #define SROM12_GPDN_H				233 /* GPIO pull down bits [31:16] */
826812 
....@@ -828,7 +814,6 @@
828814 #define SROM13_WORDS                    590
829815 #define SROM13_SIGNATURE                0x4d55
830816 #define SROM13_CRCREV                   589
831
-
832817 
833818 /* Per-path fields and offset */
834819 #define MAX_PATH_SROM_13                        4
....@@ -850,11 +835,6 @@
850835 #define SROM13_PDOFFSET20IN40M5GCORE3_1 99
851836 
852837 #define SROM13_ANTGAIN_BANDBGA          100
853
-
854
-#define SROM13_RXGAINS2CORE0            101
855
-#define SROM13_RXGAINS2CORE1            102
856
-#define SROM13_RXGAINS2CORE2            103
857
-#define SROM13_RXGAINS2CORE3            104
858838 
859839 #define SROM13_PDOFFSET40IN80M5GCORE3   105
860840 #define SROM13_PDOFFSET40IN80M5GCORE3_1 106
....@@ -925,6 +905,11 @@
925905 #define SROM13_ULBPDOFFS2GA3		166
926906 
927907 #define SROM13_RPCAL5GB4                199
908
+#define SROM13_RPCAL2GCORE3             101
909
+#define SROM13_RPCAL5GB01CORE3          102
910
+#define SROM13_RPCAL5GB23CORE3          103
911
+
912
+#define SROM13_SW_TXRX_MASK		104
928913 
929914 #define SROM13_EU_EDCRSTH               232
930915 
....@@ -954,6 +939,70 @@
954939 #define SROM13_RXGAINERRCORE3           586
955940 #define SROM13_RXGAINERRCORE3_1         587
956941 
942
+#define SROM13_PDOFF_2G_CCK_20M		167
943
+
944
+#define SROM15_CALDATA_WORDS		943
945
+#define SROM15_CAL_OFFSET_LOC		68
946
+#define MAX_IOCTL_TXCHUNK_SIZE		1500
947
+#define SROM15_MAX_CAL_SIZE		1886
948
+#define SROM15_SIGNATURE		0x110c
949
+#define SROM15_WORDS			1024
950
+#define SROM15_MACHI			65
951
+#define SROM15_CRCREV			1023
952
+#define SROM15_BRDREV			69
953
+#define SROM15_CCODE			70
954
+#define SROM15_REGREV			71
955
+#define SROM15_SIGN				64
956
+
957
+#define SROM16_SIGN			128
958
+#define SROM16_WORDS			1024
959
+#define SROM16_SIGNATURE		0x4357
960
+#define SROM16_CRCREV			1023
961
+#define SROM16_MACHI			129
962
+#define SROM16_CALDATA_OFFSET_LOC	132
963
+#define SROM16_BOARDREV		133
964
+#define SROM16_CCODE			134
965
+#define SROM16_REGREV			135
966
+
967
+#define SROM_CALDATA_WORDS		832
968
+
969
+#define SROM17_SIGN		64
970
+#define SROM17_BRDREV		65
971
+#define SROM17_MACADDR		66
972
+#define SROM17_CCODE		69
973
+#define SROM17_CALDATA		70
974
+#define SROM17_GCALTMP		71
975
+
976
+#define SROM17_C0SRD202G	72
977
+#define SROM17_C0SRD202G_1	73
978
+#define SROM17_C0SRD205GL	74
979
+#define SROM17_C0SRD205GL_1	75
980
+#define SROM17_C0SRD205GML	76
981
+#define SROM17_C0SRD205GML_1	77
982
+#define SROM17_C0SRD205GMU	78
983
+#define SROM17_C0SRD205GMU_1	79
984
+#define SROM17_C0SRD205GH	80
985
+#define SROM17_C0SRD205GH_1	81
986
+
987
+#define SROM17_C1SRD202G	82
988
+#define SROM17_C1SRD202G_1	83
989
+#define SROM17_C1SRD205GL	84
990
+#define SROM17_C1SRD205GL_1	85
991
+#define SROM17_C1SRD205GML	86
992
+#define SROM17_C1SRD205GML_1	87
993
+#define SROM17_C1SRD205GMU	88
994
+#define SROM17_C1SRD205GMU_1	89
995
+#define SROM17_C1SRD205GH	90
996
+#define SROM17_C1SRD205GH_1	91
997
+
998
+#define SROM17_TRAMMAGIC	92
999
+#define SROM17_TRAMMAGIC_1	93
1000
+#define SROM17_TRAMDATA		94
1001
+
1002
+#define SROM17_WORDS		256
1003
+#define SROM17_CRCREV		255
1004
+#define SROM17_CALDATA_WORDS	161
1005
+#define SROM17_SIGNATURE	0x1103	/* 4355 in hex format */
9571006 
9581007 typedef struct {
9591008 	uint8 tssipos;		/* TSSI positive slope, 1: positive, 0: negative */