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2024-02-19 1c055e55a242a33e574e48be530e06770a210dcd 
 kernel/drivers/net/fddi/skfp/h/skfbi.h
....@@ -1,12 +1,8 @@
1
+/* SPDX-License-Identifier: GPL-2.0-or-later */
12 /******************************************************************************
23  *
34  *	(C)Copyright 1998,1999 SysKonnect,
45  *	a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5
- *
6
- *	This program is free software; you can redistribute it and/or modify
7
- *	it under the terms of the GNU General Public License as published by
8
- *	the Free Software Foundation; either version 2 of the License, or
9
- *	(at your option) any later version.
106  *
117  *	The information in this file is provided "AS IS" without warranty.
128  *
....@@ -28,49 +24,6 @@
2824  *	(ML)	= only defined for Monalisa
2925  */
3026 
31
-/*
32
- * Configuration Space header
33
- */
34
-#define	PCI_VENDOR_ID	0x00	/* 16 bit	Vendor ID */
35
-#define	PCI_DEVICE_ID	0x02	/* 16 bit	Device ID */
36
-#define	PCI_COMMAND	0x04	/* 16 bit	Command */
37
-#define	PCI_STATUS	0x06	/* 16 bit	Status */
38
-#define	PCI_REV_ID	0x08	/*  8 bit	Revision ID */
39
-#define	PCI_CLASS_CODE	0x09	/* 24 bit	Class Code */
40
-#define	PCI_CACHE_LSZ	0x0c	/*  8 bit	Cache Line Size */
41
-#define	PCI_LAT_TIM	0x0d	/*  8 bit	Latency Timer */
42
-#define	PCI_HEADER_T	0x0e	/*  8 bit	Header Type */
43
-#define	PCI_BIST	0x0f	/*  8 bit	Built-in selftest */
44
-#define	PCI_BASE_1ST	0x10	/* 32 bit	1st Base address */
45
-#define	PCI_BASE_2ND	0x14	/* 32 bit	2nd Base address */
46
-/* Byte 18..2b:	Reserved */
47
-#define	PCI_SUB_VID	0x2c	/* 16 bit	Subsystem Vendor ID */
48
-#define	PCI_SUB_ID	0x2e	/* 16 bit	Subsystem ID */
49
-#define	PCI_BASE_ROM	0x30	/* 32 bit	Expansion ROM Base Address */
50
-/* Byte 34..33:	Reserved */
51
-#define PCI_CAP_PTR	0x34	/*  8 bit (ML)	Capabilities Ptr */
52
-/* Byte 35..3b:	Reserved */
53
-#define	PCI_IRQ_LINE	0x3c	/*  8 bit	Interrupt Line */
54
-#define	PCI_IRQ_PIN	0x3d	/*  8 bit	Interrupt Pin */
55
-#define	PCI_MIN_GNT	0x3e	/*  8 bit	Min_Gnt */
56
-#define	PCI_MAX_LAT	0x3f	/*  8 bit	Max_Lat */
57
-/* Device Dependent Region */
58
-#define	PCI_OUR_REG	0x40	/* 32 bit (DV)	Our Register */
59
-#define	PCI_OUR_REG_1	0x40	/* 32 bit (ML)	Our Register 1 */
60
-#define	PCI_OUR_REG_2	0x44	/* 32 bit (ML)	Our Register 2 */
61
-/* Power Management Region */
62
-#define PCI_PM_CAP_ID	0x48	/*  8 bit (ML)	Power Management Cap. ID */
63
-#define PCI_PM_NITEM	0x49	/*  8 bit (ML)	Next Item Ptr */
64
-#define PCI_PM_CAP_REG	0x4a	/* 16 bit (ML)	Power Management Capabilities */
65
-#define PCI_PM_CTL_STS	0x4c	/* 16 bit (ML)	Power Manag. Control/Status */
66
-/* Byte 0x4e:	Reserved */
67
-#define PCI_PM_DAT_REG	0x4f	/*  8 bit (ML)	Power Manag. Data Register */
68
-/* VPD Region */
69
-#define	PCI_VPD_CAP_ID	0x50	/*  8 bit (ML)	VPD Cap. ID */
70
-#define PCI_VPD_NITEM	0x51	/*  8 bit (ML)	Next Item Ptr */
71
-#define PCI_VPD_ADR_REG	0x52	/* 16 bit (ML)	VPD Address Register */
72
-#define PCI_VPD_DAT_REG	0x54	/* 32 bit (ML)	VPD Data Register */
73
-/* Byte 58..ff:	Reserved */
7427 
7528 /*
7629  * I2C Address (PCI Config)
....@@ -79,177 +32,6 @@
7932  *	 I2C bus.
8033  */
8134 #define I2C_ADDR_VPD	0xA0	/* I2C address for the VPD EEPROM */ 
82
-
83
-/*
84
- * Define Bits and Values of the registers
85
- */
86
-/*	PCI_VENDOR_ID	16 bit	Vendor ID */
87
-/*	PCI_DEVICE_ID	16 bit	Device ID */
88
-/* Values for Vendor ID and Device ID shall be patched into the code */
89
-/*	PCI_COMMAND	16 bit	Command */
90
-#define	PCI_FBTEN	0x0200	/* Bit 9:	Fast Back-To-Back enable */
91
-#define	PCI_SERREN	0x0100	/* Bit 8:	SERR enable */
92
-#define	PCI_ADSTEP	0x0080	/* Bit 7:	Address Stepping */
93
-#define	PCI_PERREN	0x0040	/* Bit 6:	Parity Report Response enable */
94
-#define	PCI_VGA_SNOOP	0x0020	/* Bit 5:	VGA palette snoop */
95
-#define	PCI_MWIEN	0x0010	/* Bit 4:	Memory write an inv cycl ena */
96
-#define	PCI_SCYCEN	0x0008	/* Bit 3:	Special Cycle enable */
97
-#define	PCI_BMEN	0x0004	/* Bit 2:	Bus Master enable */
98
-#define	PCI_MEMEN	0x0002	/* Bit 1:	Memory Space Access enable */
99
-#define	PCI_IOEN	0x0001	/* Bit 0:	IO Space Access enable */
100
-
101
-/*	PCI_STATUS	16 bit	Status */
102
-#define	PCI_PERR	0x8000	/* Bit 15:	Parity Error */
103
-#define	PCI_SERR	0x4000	/* Bit 14:	Signaled SERR */
104
-#define	PCI_RMABORT	0x2000	/* Bit 13:	Received Master Abort */
105
-#define	PCI_RTABORT	0x1000	/* Bit 12:	Received Target Abort */
106
-#define	PCI_STABORT	0x0800	/* Bit 11:	Sent Target Abort */
107
-#define	PCI_DEVSEL	0x0600	/* Bit 10..9:	DEVSEL Timing */
108
-#define	PCI_DEV_FAST	(0<<9)	/*		fast */
109
-#define	PCI_DEV_MEDIUM	(1<<9)	/*		medium */
110
-#define	PCI_DEV_SLOW	(2<<9)	/*		slow */
111
-#define	PCI_DATAPERR	0x0100	/* Bit 8:	DATA Parity error detected */
112
-#define	PCI_FB2BCAP	0x0080	/* Bit 7:	Fast Back-to-Back Capability */
113
-#define	PCI_UDF		0x0040	/* Bit 6:	User Defined Features */
114
-#define PCI_66MHZCAP	0x0020	/* Bit 5:	66 MHz PCI bus clock capable */
115
-#define PCI_NEWCAP	0x0010	/* Bit 4:	New cap. list implemented */
116
-
117
-#define PCI_ERRBITS	(PCI_PERR|PCI_SERR|PCI_RMABORT|PCI_STABORT|PCI_DATAPERR)
118
-
119
-/*	PCI_REV_ID	8 bit	Revision ID */
120
-/*	PCI_CLASS_CODE	24 bit	Class Code */
121
-/*	Byte 2:		Base Class		(02) */
122
-/*	Byte 1:		SubClass		(02) */
123
-/*	Byte 0:		Programming Interface	(00) */
124
-
125
-/*	PCI_CACHE_LSZ	8 bit	Cache Line Size */
126
-/*	Possible values: 0,2,4,8,16	*/
127
-
128
-/*	PCI_LAT_TIM	8 bit	Latency Timer */
129
-
130
-/*	PCI_HEADER_T	8 bit	Header Type */
131
-#define	PCI_HD_MF_DEV	0x80	/* Bit 7:	0= single, 1= multi-func dev */
132
-#define	PCI_HD_TYPE	0x7f	/* Bit 6..0:	Header Layout 0= normal */
133
-
134
-/*	PCI_BIST	8 bit	Built-in selftest */
135
-#define	PCI_BIST_CAP	0x80	/* Bit 7:	BIST Capable */
136
-#define	PCI_BIST_ST	0x40	/* Bit 6:	Start BIST */
137
-#define	PCI_BIST_RET	0x0f	/* Bit 3..0:	Completion Code */
138
-
139
-/*	PCI_BASE_1ST	32 bit	1st Base address */
140
-#define	PCI_MEMSIZE	0x800L       /* use 2 kB Memory Base */
141
-#define	PCI_MEMBASE_BITS 0xfffff800L /* Bit 31..11:	Memory Base Address */
142
-#define	PCI_MEMSIZE_BIIS 0x000007f0L /* Bit 10..4:	Memory Size Req. */
143
-#define	PCI_PREFEN	0x00000008L  /* Bit 3:		Prefetchable */
144
-#define	PCI_MEM_TYP	0x00000006L  /* Bit 2..1:	Memory Type */
145
-#define	PCI_MEM32BIT	(0<<1)	     /* Base addr anywhere in 32 Bit range */
146
-#define	PCI_MEM1M	(1<<1)	     /* Base addr below 1 MegaByte */
147
-#define	PCI_MEM64BIT	(2<<1)	     /* Base addr anywhere in 64 Bit range */
148
-#define	PCI_MEMSPACE	0x00000001L  /* Bit 0:	Memory Space Indic. */
149
-
150
-/*	PCI_SUB_VID	16 bit	Subsystem Vendor ID */
151
-/*	PCI_SUB_ID	16 bit	Subsystem ID */
152
-
153
-/*	PCI_BASE_ROM	32 bit	Expansion ROM Base Address */
154
-#define	PCI_ROMBASE	0xfffe0000L  /* Bit 31..17: ROM BASE address (1st) */
155
-#define	PCI_ROMBASZ	0x0001c000L  /* Bit 16..14: Treat as BASE or SIZE */
156
-#define	PCI_ROMSIZE	0x00003800L  /* Bit 13..11: ROM Size Requirements */
157
-#define	PCI_ROMEN	0x00000001L  /* Bit 0:	    Address Decode enable */
158
-
159
-/*	PCI_CAP_PTR	8 bit	New Capabilities Pointers */
160
-/*	PCI_IRQ_LINE	8 bit	Interrupt Line */
161
-/*	PCI_IRQ_PIN	8 bit	Interrupt Pin */
162
-/*	PCI_MIN_GNT	8 bit	Min_Gnt */
163
-/*	PCI_MAX_LAT	8 bit	Max_Lat */
164
-/* Device Dependent Region */
165
-/*	PCI_OUR_REG	(DV)	32 bit	Our Register */
166
-/*	PCI_OUR_REG_1	(ML)	32 bit	Our Register 1 */
167
-				  /*	 Bit 31..29:	reserved */
168
-#define	PCI_PATCH_DIR	(3L<<27)  /*(DV) Bit 28..27:	Ext Patchs direction */
169
-#define PCI_PATCH_DIR_0	(1L<<27)  /*(DV) Type of the pins EXT_PATCHS<1..0>   */
170
-#define PCI_PATCH_DIR_1 (1L<<28)  /*	   0 = input			     */
171
-				  /*	   1 = output			     */
172
-#define	PCI_EXT_PATCHS	(3L<<25)  /*(DV) Bit 26..25:	Extended Patches     */
173
-#define PCI_EXT_PATCH_0 (1L<<25)  /*(DV)				     */
174
-#define PCI_EXT_PATCH_1 (1L<<26)  /*	 CLK for MicroWire (ML)		     */
175
-#define PCI_VIO		(1L<<25)  /*(ML)				     */
176
-#define	PCI_EN_BOOT	(1L<<24)  /*	 Bit 24:	Enable BOOT via ROM  */
177
-				  /*	   1 = Don't boot with ROM	     */
178
-				  /*	   0 = Boot with ROM		     */
179
-#define	PCI_EN_IO	(1L<<23)  /*	 Bit 23:	Mapping to IO space  */
180
-#define	PCI_EN_FPROM	(1L<<22)  /*	 Bit 22:	FLASH mapped to mem? */
181
-				  /*	   1 = Map Flash to Memory	     */
182
-			  	  /*	   0 = Disable all addr. decoding    */
183
-#define	PCI_PAGESIZE	(3L<<20)  /*	 Bit 21..20:	FLASH Page Size	     */
184
-#define	PCI_PAGE_16	(0L<<20)  /*		16 k pages		     */
185
-#define	PCI_PAGE_32K	(1L<<20)  /*		32 k pages		     */
186
-#define	PCI_PAGE_64K	(2L<<20)  /*		64 k pages		     */
187
-#define	PCI_PAGE_128K	(3L<<20)  /*		128 k pages		     */
188
-				  /*	 Bit 19: reserved (ML) and (DV)	     */
189
-#define	PCI_PAGEREG	(7L<<16)  /*	 Bit 18..16:	Page Register	     */
190
-				  /*	 Bit 15:	reserved	     */
191
-#define	PCI_FORCE_BE	(1L<<14)  /*	 Bit 14:	Assert all BEs on MR */
192
-#define	PCI_DIS_MRL	(1L<<13)  /*	 Bit 13:	Disable Mem R Line   */
193
-#define	PCI_DIS_MRM	(1L<<12)  /*	 Bit 12:	Disable Mem R multip */
194
-#define	PCI_DIS_MWI	(1L<<11)  /*	 Bit 11:	Disable Mem W & inv  */
195
-#define	PCI_DISC_CLS	(1L<<10)  /*	 Bit 10:	Disc: cacheLsz bound */
196
-#define	PCI_BURST_DIS	(1L<<9)	  /*	 Bit  9:	Burst Disable	     */
197
-#define	PCI_BYTE_SWAP	(1L<<8)	  /*(DV) Bit  8:	Byte Swap in DATA    */
198
-#define	PCI_SKEW_DAS	(0xfL<<4) /*	 Bit 7..4:	Skew Ctrl, DAS Ext   */
199
-#define	PCI_SKEW_BASE	(0xfL<<0) /*	 Bit 3..0:	Skew Ctrl, Base	     */
200
-
201
-/*	PCI_OUR_REG_2	(ML)	32 bit	Our Register 2 (Monalisa only) */
202
-#define PCI_VPD_WR_TH	(0xffL<<24)	/* Bit 24..31	VPD Write Threshold  */
203
-#define	PCI_DEV_SEL	(0x7fL<<17)	/* Bit 17..23	EEPROM Device Select */
204
-#define	PCI_VPD_ROM_SZ	(7L<<14)	/* Bit 14..16	VPD ROM Size	     */
205
-					/* Bit 12..13	reserved	     */
206
-#define	PCI_PATCH_DIR2	(0xfL<<8)	/* Bit  8..11	Ext Patchs dir 2..5  */
207
-#define	PCI_PATCH_DIR_2	(1L<<8)		/* Bit  8	CS for MicroWire     */
208
-#define	PCI_PATCH_DIR_3	(1L<<9)
209
-#define	PCI_PATCH_DIR_4	(1L<<10)
210
-#define	PCI_PATCH_DIR_5	(1L<<11)
211
-#define PCI_EXT_PATCHS2 (0xfL<<4)	/* Bit  4..7	Extended Patches     */
212
-#define	PCI_EXT_PATCH_2	(1L<<4)		/* Bit  4	CS for MicroWire     */
213
-#define	PCI_EXT_PATCH_3	(1L<<5)
214
-#define	PCI_EXT_PATCH_4	(1L<<6)
215
-#define	PCI_EXT_PATCH_5	(1L<<7)
216
-#define	PCI_EN_DUMMY_RD	(1L<<3)		/* Bit  3	Enable Dummy Read    */
217
-#define PCI_REV_DESC	(1L<<2)		/* Bit  2	Reverse Desc. Bytes  */
218
-#define PCI_USEADDR64	(1L<<1)		/* Bit  1	Use 64 Bit Addresse  */
219
-#define PCI_USEDATA64	(1L<<0)		/* Bit  0	Use 64 Bit Data bus ext*/
220
-
221
-/* Power Management Region */
222
-/*	PCI_PM_CAP_ID		 8 bit (ML)	Power Management Cap. ID */
223
-/*	PCI_PM_NITEM		 8 bit (ML)	Next Item Ptr */
224
-/*	PCI_PM_CAP_REG		16 bit (ML)	Power Management Capabilities*/
225
-#define	PCI_PME_SUP	(0x1f<<11)	/* Bit 11..15	PM Manag. Event Support*/
226
-#define PCI_PM_D2_SUB	(1<<10)		/* Bit 10	D2 Support Bit	     */
227
-#define PCI_PM_D1_SUB	(1<<9)		/* Bit 9	D1 Support Bit       */
228
-					/* Bit 6..8 reserved		     */
229
-#define PCI_PM_DSI	(1<<5)		/* Bit 5	Device Specific Init.*/
230
-#define PCI_PM_APS	(1<<4)		/* Bit 4	Auxialiary Power Src */
231
-#define PCI_PME_CLOCK	(1<<3)		/* Bit 3	PM Event Clock       */
232
-#define PCI_PM_VER	(7<<0)		/* Bit 0..2	PM PCI Spec. version */
233
-
234
-/*	PCI_PM_CTL_STS		16 bit (ML)	Power Manag. Control/Status  */
235
-#define	PCI_PME_STATUS	(1<<15)		/* Bit 15 	PFA doesn't sup. PME#*/
236
-#define PCI_PM_DAT_SCL	(3<<13)		/* Bit 13..14	dat reg Scaling factor */
237
-#define PCI_PM_DAT_SEL	(0xf<<9)	/* Bit  9..12	PM data selector field */
238
-					/* Bit  7.. 2	reserved	     */
239
-#define PCI_PM_STATE	(3<<0)		/* Bit  0.. 1	Power Management State */
240
-#define PCI_PM_STATE_D0	(0<<0)		/* D0:	Operational (default) */
241
-#define	PCI_PM_STATE_D1	(1<<0)		/* D1:	not supported */
242
-#define PCI_PM_STATE_D2	(2<<0)		/* D2:	not supported */
243
-#define PCI_PM_STATE_D3 (3<<0)		/* D3:	HOT, Power Down and Reset */
244
-
245
-/*	PCI_PM_DAT_REG		 8 bit (ML)	Power Manag. Data Register */
246
-/* VPD Region */
247
-/*	PCI_VPD_CAP_ID		 8 bit (ML)	VPD Cap. ID */
248
-/*	PCI_VPD_NITEM		 8 bit (ML)	Next Item Ptr */
249
-/*	PCI_VPD_ADR_REG		16 bit (ML)	VPD Address Register */
250
-#define	PCI_VPD_FLAG	(1<<15)		/* Bit 15	starts VPD rd/wd cycle*/
251
-
252
-/*	PCI_VPD_DAT_REG		32 bit (ML)	VPD Data Register */
25335 
25436 /*
25537  *	Control Register File:
....@@ -877,20 +659,6 @@
877659 #define	T3_MUX		(3<<2)	/* Bit 3..2:	Mux position */
878660 #define	T3_VRAM		(3<<0)	/* Bit 1..0:	Virtual RAM buffer Address */
879661 
880
-/* PCI card IDs */
881
-/*
882
- * Note: The following 4 byte definitions shall not be used! Use OEM Concept!
883
- */
884
-#define	PCI_VEND_ID0	0x48		/* PCI vendor ID (SysKonnect) */
885
-#define	PCI_VEND_ID1	0x11		/* PCI vendor ID (SysKonnect) */
886
-					/*		 (High byte) */
887
-#define	PCI_DEV_ID0	0x00		/* PCI device ID */
888
-#define	PCI_DEV_ID1	0x40		/* PCI device ID (High byte) */
889
-
890
-/*#define PCI_CLASS	0x02*/		/* PCI class code: network device */
891
-#define PCI_NW_CLASS	0x02		/* PCI class code: network device */
892
-#define PCI_SUB_CLASS	0x02		/* PCI subclass ID: FDDI device */
893
-#define PCI_PROG_INTFC	0x00		/* PCI programming Interface (=0) */
894662 
895663 /*
896664  * address transmission from logical to physical offset address on board