forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-02-19 1c055e55a242a33e574e48be530e06770a210dcd 
 kernel/drivers/gpu/drm/amd/amdgpu/vi.c
....@@ -20,8 +20,10 @@
2020  * OTHER DEALINGS IN THE SOFTWARE.
2121  *
2222  */
23
+
24
+#include <linux/pci.h>
2325 #include <linux/slab.h>
24
-#include <drm/drmP.h>
26
+
2527 #include "amdgpu.h"
2628 #include "amdgpu_atombios.h"
2729 #include "amdgpu_ih.h"
....@@ -57,7 +59,6 @@
5759 
5860 #include "vid.h"
5961 #include "vi.h"
60
-#include "vi_dpm.h"
6162 #include "gmc_v8_0.h"
6263 #include "gmc_v7_0.h"
6364 #include "gfx_v8_0.h"
....@@ -87,9 +88,9 @@
8788 	u32 r;
8889 
8990 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
90
-	WREG32(mmPCIE_INDEX, reg);
91
-	(void)RREG32(mmPCIE_INDEX);
92
-	r = RREG32(mmPCIE_DATA);
91
+	WREG32_NO_KIQ(mmPCIE_INDEX, reg);
92
+	(void)RREG32_NO_KIQ(mmPCIE_INDEX);
93
+	r = RREG32_NO_KIQ(mmPCIE_DATA);
9394 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
9495 	return r;
9596 }
....@@ -99,10 +100,10 @@
99100 	unsigned long flags;
100101 
101102 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
102
-	WREG32(mmPCIE_INDEX, reg);
103
-	(void)RREG32(mmPCIE_INDEX);
104
-	WREG32(mmPCIE_DATA, v);
105
-	(void)RREG32(mmPCIE_DATA);
103
+	WREG32_NO_KIQ(mmPCIE_INDEX, reg);
104
+	(void)RREG32_NO_KIQ(mmPCIE_INDEX);
105
+	WREG32_NO_KIQ(mmPCIE_DATA, v);
106
+	(void)RREG32_NO_KIQ(mmPCIE_DATA);
106107 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
107108 }
108109 
....@@ -123,8 +124,8 @@
123124 	unsigned long flags;
124125 
125126 	spin_lock_irqsave(&adev->smc_idx_lock, flags);
126
-	WREG32(mmSMC_IND_INDEX_11, (reg));
127
-	WREG32(mmSMC_IND_DATA_11, (v));
127
+	WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));
128
+	WREG32_NO_KIQ(mmSMC_IND_DATA_11, (v));
128129 	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
129130 }
130131 
....@@ -328,8 +329,15 @@
328329 	u32 reference_clock = adev->clock.spll.reference_freq;
329330 	u32 tmp;
330331 
331
-	if (adev->flags & AMD_IS_APU)
332
-		return reference_clock;
332
+	if (adev->flags & AMD_IS_APU) {
333
+		switch (adev->asic_type) {
334
+		case CHIP_STONEY:
335
+			/* vbios says 48Mhz, but the actual freq is 100Mhz */
336
+			return 10000;
337
+		default:
338
+			return reference_clock;
339
+		}
340
+	}
333341 
334342 	tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
335343 	if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
....@@ -445,27 +453,6 @@
445453 	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
446454 
447455 	return true;
448
-}
449
-
450
-static void vi_detect_hw_virtualization(struct amdgpu_device *adev)
451
-{
452
-	uint32_t reg = 0;
453
-
454
-	if (adev->asic_type == CHIP_TONGA ||
455
-	    adev->asic_type == CHIP_FIJI) {
456
-	       reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
457
-	       /* bit0: 0 means pf and 1 means vf */
458
-	       if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, FUNC_IDENTIFIER))
459
-		       adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
460
-	       /* bit31: 0 means disable IOV and 1 means enable */
461
-	       if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, IOV_ENABLE))
462
-		       adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
463
-	}
464
-
465
-	if (reg == 0) {
466
-		if (is_virtual_machine()) /* passthrough mode exclus sr-iov mode */
467
-			adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
468
-	}
469456 }
470457 
471458 static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
....@@ -689,6 +676,76 @@
689676 }
690677 
691678 /**
679
+ * vi_asic_pci_config_reset - soft reset GPU
680
+ *
681
+ * @adev: amdgpu_device pointer
682
+ *
683
+ * Use PCI Config method to reset the GPU.
684
+ *
685
+ * Returns 0 for success.
686
+ */
687
+static int vi_asic_pci_config_reset(struct amdgpu_device *adev)
688
+{
689
+	int r;
690
+
691
+	amdgpu_atombios_scratch_regs_engine_hung(adev, true);
692
+
693
+	r = vi_gpu_pci_config_reset(adev);
694
+
695
+	amdgpu_atombios_scratch_regs_engine_hung(adev, false);
696
+
697
+	return r;
698
+}
699
+
700
+static bool vi_asic_supports_baco(struct amdgpu_device *adev)
701
+{
702
+	switch (adev->asic_type) {
703
+	case CHIP_FIJI:
704
+	case CHIP_TONGA:
705
+	case CHIP_POLARIS10:
706
+	case CHIP_POLARIS11:
707
+	case CHIP_POLARIS12:
708
+	case CHIP_TOPAZ:
709
+		return amdgpu_dpm_is_baco_supported(adev);
710
+	default:
711
+		return false;
712
+	}
713
+}
714
+
715
+static enum amd_reset_method
716
+vi_asic_reset_method(struct amdgpu_device *adev)
717
+{
718
+	bool baco_reset;
719
+
720
+	if (amdgpu_reset_method == AMD_RESET_METHOD_LEGACY ||
721
+	    amdgpu_reset_method == AMD_RESET_METHOD_BACO)
722
+		return amdgpu_reset_method;
723
+
724
+	if (amdgpu_reset_method != -1)
725
+		dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
726
+				  amdgpu_reset_method);
727
+
728
+	switch (adev->asic_type) {
729
+	case CHIP_FIJI:
730
+	case CHIP_TONGA:
731
+	case CHIP_POLARIS10:
732
+	case CHIP_POLARIS11:
733
+	case CHIP_POLARIS12:
734
+	case CHIP_TOPAZ:
735
+		baco_reset = amdgpu_dpm_is_baco_supported(adev);
736
+		break;
737
+	default:
738
+		baco_reset = false;
739
+		break;
740
+	}
741
+
742
+	if (baco_reset)
743
+		return AMD_RESET_METHOD_BACO;
744
+	else
745
+		return AMD_RESET_METHOD_LEGACY;
746
+}
747
+
748
+/**
692749  * vi_asic_reset - soft reset GPU
693750  *
694751  * @adev: amdgpu_device pointer
....@@ -701,11 +758,13 @@
701758 {
702759 	int r;
703760 
704
-	amdgpu_atombios_scratch_regs_engine_hung(adev, true);
705
-
706
-	r = vi_gpu_pci_config_reset(adev);
707
-
708
-	amdgpu_atombios_scratch_regs_engine_hung(adev, false);
761
+	if (vi_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
762
+		dev_info(adev->dev, "BACO reset\n");
763
+		r = amdgpu_dpm_baco_reset(adev);
764
+	} else {
765
+		dev_info(adev->dev, "PCI CONFIG reset\n");
766
+		r = vi_asic_pci_config_reset(adev);
767
+	}
709768 
710769 	return r;
711770 }
....@@ -941,12 +1000,92 @@
9411000 	}
9421001 }
9431002 
1003
+static void vi_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
1004
+			      uint64_t *count1)
1005
+{
1006
+	uint32_t perfctr = 0;
1007
+	uint64_t cnt0_of, cnt1_of;
1008
+	int tmp;
1009
+
1010
+	/* This reports 0 on APUs, so return to avoid writing/reading registers
1011
+	 * that may or may not be different from their GPU counterparts
1012
+	 */
1013
+	if (adev->flags & AMD_IS_APU)
1014
+		return;
1015
+
1016
+	/* Set the 2 events that we wish to watch, defined above */
1017
+	/* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
1018
+	perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
1019
+	perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
1020
+
1021
+	/* Write to enable desired perf counters */
1022
+	WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr);
1023
+	/* Zero out and enable the perf counters
1024
+	 * Write 0x5:
1025
+	 * Bit 0 = Start all counters(1)
1026
+	 * Bit 2 = Global counter reset enable(1)
1027
+	 */
1028
+	WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005);
1029
+
1030
+	msleep(1000);
1031
+
1032
+	/* Load the shadow and disable the perf counters
1033
+	 * Write 0x2:
1034
+	 * Bit 0 = Stop counters(0)
1035
+	 * Bit 1 = Load the shadow counters(1)
1036
+	 */
1037
+	WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002);
1038
+
1039
+	/* Read register values to get any >32bit overflow */
1040
+	tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK);
1041
+	cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
1042
+	cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
1043
+
1044
+	/* Get the values and add the overflow */
1045
+	*count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
1046
+	*count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
1047
+}
1048
+
1049
+static uint64_t vi_get_pcie_replay_count(struct amdgpu_device *adev)
1050
+{
1051
+	uint64_t nak_r, nak_g;
1052
+
1053
+	/* Get the number of NAKs received and generated */
1054
+	nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK);
1055
+	nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED);
1056
+
1057
+	/* Add the total number of NAKs, i.e the number of replays */
1058
+	return (nak_r + nak_g);
1059
+}
1060
+
1061
+static bool vi_need_reset_on_init(struct amdgpu_device *adev)
1062
+{
1063
+	u32 clock_cntl, pc;
1064
+
1065
+	if (adev->flags & AMD_IS_APU)
1066
+		return false;
1067
+
1068
+	/* check if the SMC is already running */
1069
+	clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
1070
+	pc = RREG32_SMC(ixSMC_PC_C);
1071
+	if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) &&
1072
+	    (0x20100 <= pc))
1073
+		return true;
1074
+
1075
+	return false;
1076
+}
1077
+
1078
+static void vi_pre_asic_init(struct amdgpu_device *adev)
1079
+{
1080
+}
1081
+
9441082 static const struct amdgpu_asic_funcs vi_asic_funcs =
9451083 {
9461084 	.read_disabled_bios = &vi_read_disabled_bios,
9471085 	.read_bios_from_rom = &vi_read_bios_from_rom,
9481086 	.read_register = &vi_read_register,
9491087 	.reset = &vi_asic_reset,
1088
+	.reset_method = &vi_asic_reset_method,
9501089 	.set_vga_state = &vi_vga_set_state,
9511090 	.get_xclk = &vi_get_xclk,
9521091 	.set_uvd_clocks = &vi_set_uvd_clocks,
....@@ -955,6 +1094,12 @@
9551094 	.flush_hdp = &vi_flush_hdp,
9561095 	.invalidate_hdp = &vi_invalidate_hdp,
9571096 	.need_full_reset = &vi_need_full_reset,
1097
+	.init_doorbell_index = &legacy_doorbell_index_init,
1098
+	.get_pcie_usage = &vi_get_pcie_usage,
1099
+	.need_reset_on_init = &vi_need_reset_on_init,
1100
+	.get_pcie_replay_count = &vi_get_pcie_replay_count,
1101
+	.supports_baco = &vi_asic_supports_baco,
1102
+	.pre_asic_init = &vi_pre_asic_init,
9581103 };
9591104 
9601105 #define CZ_REV_BRISTOL(rev)	 \
....@@ -1376,8 +1521,7 @@
13761521 			       PP_BLOCK_SYS_MC,
13771522 			       pp_support_state,
13781523 			       pp_state);
1379
-		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1380
-			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1524
+		amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
13811525 	}
13821526 
13831527 	if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) {
....@@ -1395,8 +1539,7 @@
13951539 			       PP_BLOCK_SYS_SDMA,
13961540 			       pp_support_state,
13971541 			       pp_state);
1398
-		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1399
-			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1542
+		amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
14001543 	}
14011544 
14021545 	if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) {
....@@ -1414,8 +1557,7 @@
14141557 			       PP_BLOCK_SYS_HDP,
14151558 			       pp_support_state,
14161559 			       pp_state);
1417
-		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1418
-			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1560
+		amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
14191561 	}
14201562 
14211563 
....@@ -1429,8 +1571,7 @@
14291571 			       PP_BLOCK_SYS_BIF,
14301572 			       PP_STATE_SUPPORT_LS,
14311573 			        pp_state);
1432
-		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1433
-			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1574
+		amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
14341575 	}
14351576 	if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) {
14361577 		if (state == AMD_CG_STATE_UNGATE)
....@@ -1442,8 +1583,7 @@
14421583 			       PP_BLOCK_SYS_BIF,
14431584 			       PP_STATE_SUPPORT_CG,
14441585 			       pp_state);
1445
-		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1446
-			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1586
+		amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
14471587 	}
14481588 
14491589 	if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) {
....@@ -1457,8 +1597,7 @@
14571597 			       PP_BLOCK_SYS_DRM,
14581598 			       PP_STATE_SUPPORT_LS,
14591599 			       pp_state);
1460
-		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1461
-			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1600
+		amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
14621601 	}
14631602 
14641603 	if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) {
....@@ -1472,8 +1611,7 @@
14721611 			       PP_BLOCK_SYS_ROM,
14731612 			       PP_STATE_SUPPORT_CG,
14741613 			       pp_state);
1475
-		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1476
-			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1614
+		amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
14771615 	}
14781616 	return 0;
14791617 }
....@@ -1582,30 +1720,31 @@
15821720 	.funcs = &vi_common_ip_funcs,
15831721 };
15841722 
1723
+void vi_set_virt_ops(struct amdgpu_device *adev)
1724
+{
1725
+	adev->virt.ops = &xgpu_vi_virt_ops;
1726
+}
1727
+
15851728 int vi_set_ip_blocks(struct amdgpu_device *adev)
15861729 {
1587
-	/* in early init stage, vbios code won't work */
1588
-	vi_detect_hw_virtualization(adev);
1589
-
1590
-	if (amdgpu_sriov_vf(adev))
1591
-		adev->virt.ops = &xgpu_vi_virt_ops;
1592
-
15931730 	switch (adev->asic_type) {
15941731 	case CHIP_TOPAZ:
15951732 		/* topaz has no DCE, UVD, VCE */
15961733 		amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
15971734 		amdgpu_device_ip_block_add(adev, &gmc_v7_4_ip_block);
15981735 		amdgpu_device_ip_block_add(adev, &iceland_ih_ip_block);
1736
+		amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1737
+		amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block);
15991738 		amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
16001739 		if (adev->enable_virtual_display)
16011740 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1602
-		amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1603
-		amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block);
16041741 		break;
16051742 	case CHIP_FIJI:
16061743 		amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
16071744 		amdgpu_device_ip_block_add(adev, &gmc_v8_5_ip_block);
16081745 		amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
1746
+		amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1747
+		amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
16091748 		amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
16101749 		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
16111750 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
....@@ -1615,8 +1754,6 @@
16151754 #endif
16161755 		else
16171756 			amdgpu_device_ip_block_add(adev, &dce_v10_1_ip_block);
1618
-		amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1619
-		amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
16201757 		if (!amdgpu_sriov_vf(adev)) {
16211758 			amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
16221759 			amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
....@@ -1626,6 +1763,8 @@
16261763 		amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
16271764 		amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
16281765 		amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
1766
+		amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1767
+		amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
16291768 		amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
16301769 		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
16311770 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
....@@ -1635,8 +1774,6 @@
16351774 #endif
16361775 		else
16371776 			amdgpu_device_ip_block_add(adev, &dce_v10_0_ip_block);
1638
-		amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1639
-		amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
16401777 		if (!amdgpu_sriov_vf(adev)) {
16411778 			amdgpu_device_ip_block_add(adev, &uvd_v5_0_ip_block);
16421779 			amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
....@@ -1649,6 +1786,8 @@
16491786 		amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
16501787 		amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block);
16511788 		amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
1789
+		amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1790
+		amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block);
16521791 		amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
16531792 		if (adev->enable_virtual_display)
16541793 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
....@@ -1658,8 +1797,6 @@
16581797 #endif
16591798 		else
16601799 			amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_block);
1661
-		amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1662
-		amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block);
16631800 		amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block);
16641801 		amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
16651802 		break;
....@@ -1667,6 +1804,8 @@
16671804 		amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
16681805 		amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
16691806 		amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
1807
+		amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1808
+		amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
16701809 		amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
16711810 		if (adev->enable_virtual_display)
16721811 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
....@@ -1676,8 +1815,6 @@
16761815 #endif
16771816 		else
16781817 			amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
1679
-		amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1680
-		amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
16811818 		amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
16821819 		amdgpu_device_ip_block_add(adev, &vce_v3_1_ip_block);
16831820 #if defined(CONFIG_DRM_AMD_ACP)
....@@ -1688,6 +1825,8 @@
16881825 		amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
16891826 		amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
16901827 		amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
1828
+		amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block);
1829
+		amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
16911830 		amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
16921831 		if (adev->enable_virtual_display)
16931832 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
....@@ -1697,8 +1836,6 @@
16971836 #endif
16981837 		else
16991838 			amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
1700
-		amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block);
1701
-		amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
17021839 		amdgpu_device_ip_block_add(adev, &uvd_v6_2_ip_block);
17031840 		amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
17041841 #if defined(CONFIG_DRM_AMD_ACP)
....@@ -1712,3 +1849,21 @@
17121849 
17131850 	return 0;
17141851 }
1852
+
1853
+void legacy_doorbell_index_init(struct amdgpu_device *adev)
1854
+{
1855
+	adev->doorbell_index.kiq = AMDGPU_DOORBELL_KIQ;
1856
+	adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL_MEC_RING0;
1857
+	adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL_MEC_RING1;
1858
+	adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL_MEC_RING2;
1859
+	adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL_MEC_RING3;
1860
+	adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL_MEC_RING4;
1861
+	adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL_MEC_RING5;
1862
+	adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL_MEC_RING6;
1863
+	adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL_MEC_RING7;
1864
+	adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL_GFX_RING0;
1865
+	adev->doorbell_index.sdma_engine[0] = AMDGPU_DOORBELL_sDMA_ENGINE0;
1866
+	adev->doorbell_index.sdma_engine[1] = AMDGPU_DOORBELL_sDMA_ENGINE1;
1867
+	adev->doorbell_index.ih = AMDGPU_DOORBELL_IH;
1868
+	adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_MAX_ASSIGNMENT;
1869
+}