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2024-02-19 1c055e55a242a33e574e48be530e06770a210dcd 
 kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
....@@ -23,6 +23,8 @@
2323 #ifndef __AMDGPU_UCODE_H__
2424 #define __AMDGPU_UCODE_H__
2525 
26
+#include "amdgpu_socbb.h"
27
+
2628 struct common_firmware_header {
2729 	uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
2830 	uint32_t header_size_bytes; /* size of just the header in bytes */
....@@ -49,6 +51,26 @@
4951 	uint32_t ucode_start_addr;
5052 };
5153 
54
+/* version_major=2, version_minor=0 */
55
+struct smc_firmware_header_v2_0 {
56
+	struct smc_firmware_header_v1_0 v1_0;
57
+	uint32_t ppt_offset_bytes; /* soft pptable offset */
58
+	uint32_t ppt_size_bytes; /* soft pptable size */
59
+};
60
+
61
+struct smc_soft_pptable_entry {
62
+        uint32_t id;
63
+        uint32_t ppt_offset_bytes;
64
+        uint32_t ppt_size_bytes;
65
+};
66
+
67
+/* version_major=2, version_minor=1 */
68
+struct smc_firmware_header_v2_1 {
69
+        struct smc_firmware_header_v1_0 v1_0;
70
+        uint32_t pptable_count;
71
+        uint32_t pptable_entry_offset;
72
+};
73
+
5274 /* version_major=1, version_minor=0 */
5375 struct psp_firmware_header_v1_0 {
5476 	struct common_firmware_header header;
....@@ -57,12 +79,96 @@
5779 	uint32_t sos_size_bytes;
5880 };
5981 
82
+/* version_major=1, version_minor=1 */
83
+struct psp_firmware_header_v1_1 {
84
+	struct psp_firmware_header_v1_0 v1_0;
85
+	uint32_t toc_header_version;
86
+	uint32_t toc_offset_bytes;
87
+	uint32_t toc_size_bytes;
88
+	uint32_t kdb_header_version;
89
+	uint32_t kdb_offset_bytes;
90
+	uint32_t kdb_size_bytes;
91
+};
92
+
93
+/* version_major=1, version_minor=2 */
94
+struct psp_firmware_header_v1_2 {
95
+	struct psp_firmware_header_v1_0 v1_0;
96
+	uint32_t reserve[3];
97
+	uint32_t kdb_header_version;
98
+	uint32_t kdb_offset_bytes;
99
+	uint32_t kdb_size_bytes;
100
+};
101
+
102
+/* version_major=1, version_minor=3 */
103
+struct psp_firmware_header_v1_3 {
104
+	struct psp_firmware_header_v1_1 v1_1;
105
+	uint32_t spl_header_version;
106
+	uint32_t spl_offset_bytes;
107
+	uint32_t spl_size_bytes;
108
+};
109
+
110
+/* version_major=1, version_minor=0 */
111
+struct ta_firmware_header_v1_0 {
112
+	struct common_firmware_header header;
113
+	uint32_t ta_xgmi_ucode_version;
114
+	uint32_t ta_xgmi_offset_bytes;
115
+	uint32_t ta_xgmi_size_bytes;
116
+	uint32_t ta_ras_ucode_version;
117
+	uint32_t ta_ras_offset_bytes;
118
+	uint32_t ta_ras_size_bytes;
119
+	uint32_t ta_hdcp_ucode_version;
120
+	uint32_t ta_hdcp_offset_bytes;
121
+	uint32_t ta_hdcp_size_bytes;
122
+	uint32_t ta_dtm_ucode_version;
123
+	uint32_t ta_dtm_offset_bytes;
124
+	uint32_t ta_dtm_size_bytes;
125
+};
126
+
127
+enum ta_fw_type {
128
+	TA_FW_TYPE_UNKOWN,
129
+	TA_FW_TYPE_PSP_ASD,
130
+	TA_FW_TYPE_PSP_XGMI,
131
+	TA_FW_TYPE_PSP_RAS,
132
+	TA_FW_TYPE_PSP_HDCP,
133
+	TA_FW_TYPE_PSP_DTM,
134
+	TA_FW_TYPE_PSP_RAP,
135
+};
136
+
137
+struct ta_fw_bin_desc {
138
+	uint32_t fw_type;
139
+	uint32_t fw_version;
140
+	uint32_t offset_bytes;
141
+	uint32_t size_bytes;
142
+};
143
+
144
+/* version_major=2, version_minor=0 */
145
+struct ta_firmware_header_v2_0 {
146
+	struct common_firmware_header header;
147
+	uint32_t ta_fw_bin_count;
148
+	struct ta_fw_bin_desc ta_fw_bin[];
149
+};
150
+
60151 /* version_major=1, version_minor=0 */
61152 struct gfx_firmware_header_v1_0 {
62153 	struct common_firmware_header header;
63154 	uint32_t ucode_feature_version;
64155 	uint32_t jt_offset; /* jt location */
65156 	uint32_t jt_size;  /* size of jt */
157
+};
158
+
159
+/* version_major=1, version_minor=0 */
160
+struct mes_firmware_header_v1_0 {
161
+	struct common_firmware_header header;
162
+	uint32_t mes_ucode_version;
163
+	uint32_t mes_ucode_size_bytes;
164
+	uint32_t mes_ucode_offset_bytes;
165
+	uint32_t mes_ucode_data_version;
166
+	uint32_t mes_ucode_data_size_bytes;
167
+	uint32_t mes_ucode_data_offset_bytes;
168
+	uint32_t mes_uc_start_addr_lo;
169
+	uint32_t mes_uc_start_addr_hi;
170
+	uint32_t mes_data_start_addr_lo;
171
+	uint32_t mes_data_start_addr_hi;
66172 };
67173 
68174 /* version_major=1, version_minor=0 */
....@@ -116,6 +222,15 @@
116222 	uint32_t save_restore_list_srm_offset_bytes;
117223 };
118224 
225
+/* version_major=2, version_minor=1 */
226
+struct rlc_firmware_header_v2_2 {
227
+	struct rlc_firmware_header_v2_1 v2_1;
228
+	uint32_t rlc_iram_ucode_size_bytes;
229
+	uint32_t rlc_iram_ucode_offset_bytes;
230
+	uint32_t rlc_dram_ucode_size_bytes;
231
+	uint32_t rlc_dram_ucode_offset_bytes;
232
+};
233
+
119234 /* version_major=1, version_minor=0 */
120235 struct sdma_firmware_header_v1_0 {
121236 	struct common_firmware_header header;
....@@ -150,6 +265,19 @@
150265 	uint32_t gc_lds_size;
151266 };
152267 
268
+struct gpu_info_firmware_v1_1 {
269
+	struct gpu_info_firmware_v1_0 v1_0;
270
+	uint32_t num_sc_per_sh;
271
+	uint32_t num_packer_per_sc;
272
+};
273
+
274
+/* gpu info payload
275
+ * version_major=1, version_minor=1 */
276
+struct gpu_info_firmware_v1_2 {
277
+	struct gpu_info_firmware_v1_1 v1_1;
278
+	struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box;
279
+};
280
+
153281 /* version_major=1, version_minor=0 */
154282 struct gpu_info_firmware_header_v1_0 {
155283 	struct common_firmware_header header;
....@@ -157,12 +285,31 @@
157285 	uint16_t version_minor; /* version */
158286 };
159287 
288
+/* version_major=1, version_minor=0 */
289
+struct dmcu_firmware_header_v1_0 {
290
+	struct common_firmware_header header;
291
+	uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */
292
+	uint32_t intv_size_bytes;  /* size of interrupt vectors, in bytes */
293
+};
294
+
295
+/* version_major=1, version_minor=0 */
296
+struct dmcub_firmware_header_v1_0 {
297
+	struct common_firmware_header header;
298
+	uint32_t inst_const_bytes; /* size of instruction region, in bytes */
299
+	uint32_t bss_data_bytes; /* size of bss/data region, in bytes */
300
+};
301
+
160302 /* header is fixed size */
161303 union amdgpu_firmware_header {
162304 	struct common_firmware_header common;
163305 	struct mc_firmware_header_v1_0 mc;
164306 	struct smc_firmware_header_v1_0 smc;
307
+	struct smc_firmware_header_v2_0 smc_v2_0;
165308 	struct psp_firmware_header_v1_0 psp;
309
+	struct psp_firmware_header_v1_1 psp_v1_1;
310
+	struct psp_firmware_header_v1_3 psp_v1_3;
311
+	struct ta_firmware_header_v1_0 ta;
312
+	struct ta_firmware_header_v2_0 ta_v2_0;
166313 	struct gfx_firmware_header_v1_0 gfx;
167314 	struct rlc_firmware_header_v1_0 rlc;
168315 	struct rlc_firmware_header_v2_0 rlc_v2_0;
....@@ -170,8 +317,12 @@
170317 	struct sdma_firmware_header_v1_0 sdma;
171318 	struct sdma_firmware_header_v1_1 sdma_v1_1;
172319 	struct gpu_info_firmware_header_v1_0 gpu_info;
320
+	struct dmcu_firmware_header_v1_0 dmcu;
321
+	struct dmcub_firmware_header_v1_0 dmcub;
173322 	uint8_t raw[0x100];
174323 };
324
+
325
+#define UCODE_MAX_TA_PACKAGING ((sizeof(union amdgpu_firmware_header) - sizeof(struct common_firmware_header) - 4) / sizeof(struct ta_fw_bin_desc))
175326 
176327 /*
177328  * fw loading support
....@@ -179,6 +330,12 @@
179330 enum AMDGPU_UCODE_ID {
180331 	AMDGPU_UCODE_ID_SDMA0 = 0,
181332 	AMDGPU_UCODE_ID_SDMA1,
333
+	AMDGPU_UCODE_ID_SDMA2,
334
+	AMDGPU_UCODE_ID_SDMA3,
335
+	AMDGPU_UCODE_ID_SDMA4,
336
+	AMDGPU_UCODE_ID_SDMA5,
337
+	AMDGPU_UCODE_ID_SDMA6,
338
+	AMDGPU_UCODE_ID_SDMA7,
182339 	AMDGPU_UCODE_ID_CP_CE,
183340 	AMDGPU_UCODE_ID_CP_PFP,
184341 	AMDGPU_UCODE_ID_CP_ME,
....@@ -186,15 +343,26 @@
186343 	AMDGPU_UCODE_ID_CP_MEC1_JT,
187344 	AMDGPU_UCODE_ID_CP_MEC2,
188345 	AMDGPU_UCODE_ID_CP_MEC2_JT,
189
-	AMDGPU_UCODE_ID_RLC_G,
346
+	AMDGPU_UCODE_ID_CP_MES,
347
+	AMDGPU_UCODE_ID_CP_MES_DATA,
190348 	AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,
191349 	AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,
192350 	AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,
351
+	AMDGPU_UCODE_ID_RLC_IRAM,
352
+	AMDGPU_UCODE_ID_RLC_DRAM,
353
+	AMDGPU_UCODE_ID_RLC_G,
193354 	AMDGPU_UCODE_ID_STORAGE,
194355 	AMDGPU_UCODE_ID_SMC,
195356 	AMDGPU_UCODE_ID_UVD,
357
+	AMDGPU_UCODE_ID_UVD1,
196358 	AMDGPU_UCODE_ID_VCE,
197359 	AMDGPU_UCODE_ID_VCN,
360
+	AMDGPU_UCODE_ID_VCN1,
361
+	AMDGPU_UCODE_ID_DMCU_ERAM,
362
+	AMDGPU_UCODE_ID_DMCU_INTV,
363
+	AMDGPU_UCODE_ID_VCN0_RAM,
364
+	AMDGPU_UCODE_ID_VCN1_RAM,
365
+	AMDGPU_UCODE_ID_DMCUB,
198366 	AMDGPU_UCODE_ID_MAXIMUM,
199367 };
200368 
....@@ -203,6 +371,13 @@
203371 	AMDGPU_UCODE_STATUS_INVALID,
204372 	AMDGPU_UCODE_STATUS_NOT_LOADED,
205373 	AMDGPU_UCODE_STATUS_LOADED,
374
+};
375
+
376
+enum amdgpu_firmware_load_type {
377
+	AMDGPU_FW_LOAD_DIRECT = 0,
378
+	AMDGPU_FW_LOAD_SMU,
379
+	AMDGPU_FW_LOAD_PSP,
380
+	AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO,
206381 };
207382 
208383 /* conform to smu_ucode_xfer_cz.h */
....@@ -232,17 +407,40 @@
232407 	uint32_t tmr_mc_addr_hi;
233408 };
234409 
410
+struct amdgpu_firmware {
411
+	struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
412
+	enum amdgpu_firmware_load_type load_type;
413
+	struct amdgpu_bo *fw_buf;
414
+	unsigned int fw_size;
415
+	unsigned int max_ucodes;
416
+	/* firmwares are loaded by psp instead of smu from vega10 */
417
+	const struct amdgpu_psp_funcs *funcs;
418
+	struct amdgpu_bo *rbuf;
419
+	struct mutex mutex;
420
+
421
+	/* gpu info firmware data pointer */
422
+	const struct firmware *gpu_info_fw;
423
+
424
+	void *fw_buf_ptr;
425
+	uint64_t fw_buf_mc;
426
+};
427
+
235428 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
236429 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
237430 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
238431 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
239432 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
433
+void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr);
240434 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr);
241435 int amdgpu_ucode_validate(const struct firmware *fw);
242436 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
243437 				uint16_t hdr_major, uint16_t hdr_minor);
438
+
244439 int amdgpu_ucode_init_bo(struct amdgpu_device *adev);
245
-int amdgpu_ucode_fini_bo(struct amdgpu_device *adev);
440
+int amdgpu_ucode_create_bo(struct amdgpu_device *adev);
441
+int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev);
442
+void amdgpu_ucode_free_bo(struct amdgpu_device *adev);
443
+void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev);
246444 
247445 enum amdgpu_firmware_load_type
248446 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type);