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2024-02-19 1c055e55a242a33e574e48be530e06770a210dcd

 kernel/drivers/devfreq/event/rockchip-dfi.c
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@@ -1,15 +1,7 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
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  * Author: Lin Huang <hl@rock-chips.com>
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms and conditions of the GNU General Public License,
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- * version 2, as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope it will be useful, but WITHOUT
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- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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- * more details.
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  */
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6
 
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 #include <linux/clk.h>
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@@ -26,8 +18,12 @@
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 #include <linux/list.h>
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 #include <linux/of.h>
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20
 
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+#include <soc/rockchip/rk3399_grf.h>
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+
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 #define PX30_PMUGRF_OS_REG2		0x208
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 #define PX30_PMUGRF_OS_REG3		0x20c
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+
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+#define RK3588_PMUGRF_OS_REG(n)		(0x200 + (n) * 4)
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 #define RK3128_GRF_SOC_CON0		0x140
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 #define RK3128_GRF_OS_REG1		0x1cc
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@@ -60,14 +56,18 @@
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 #define RK3528_PMUGRF_OS_REG18		0x248
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 #define RK3528_PMUGRF_OS_REG19		0x24c
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58
 
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-#define MAX_DMC_NUM_CH			2
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+#define MAX_DMC_NUM_CH			4
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 #define READ_DRAMTYPE_INFO(n)		(((n) >> 13) & 0x7)
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 #define READ_CH_INFO(n)			(((n) >> 28) & 0x3)
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 #define READ_DRAMTYPE_INFO_V3(n, m)	((((n) >> 13) & 0x7) | ((((m) >> 12) & 0x3) << 3))
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 #define READ_SYSREG_VERSION(m)		(((m) >> 28) & 0xf)
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+#define READ_LP5_BANK_MODE(m)		(((m) >> 1) & 0x3)
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+#define READ_LP5_CKR(m)			(((m) >> 0) & 0x1)
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 /* DDRMON_CTRL */
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 #define DDRMON_CTRL			0x04
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-#define CLR_DDRMON_CTRL			(0x3f0000 << 0)
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+#define CLR_DDRMON_CTRL			(0xffff0000 << 0)
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+#define LPDDR5_BANK_MODE(m)		((0x30000 | ((m) & 0x3)) << 7)
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+#define LPDDR5_EN			(0x10001 << 6)
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 #define DDR4_EN				(0x10001 << 5)
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 #define LPDDR4_EN			(0x10001 << 4)
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 #define HARDWARE_EN			(0x10001 << 3)
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@@ -91,12 +91,14 @@
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 	LPDDR3 = 6,
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 	LPDDR4 = 7,
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 	LPDDR4X = 8,
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+	LPDDR5 = 9,
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+	DDR5 = 10,
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 	UNUSED = 0xFF
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 };
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98
 
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 struct dmc_usage {
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-	u32 access;
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-	u32 total;
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+	u64 access;
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+	u64 total;
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 };
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103
 
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 /*
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..
@@ -115,7 +117,13 @@
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 	struct regmap *regmap_pmugrf;
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 	struct clk *clk;
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 	u32 dram_type;
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+	u32 mon_idx;
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 	u32 count_rate;
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+	u32 dram_dynamic_info_reg;
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+	/* 0: BG mode, 1: 16 Bank mode, 2: 8 bank mode */
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+	u32 lp5_bank_mode;
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+	/* 0: clk:dqs = 1:2, 1: 1:4 */
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+	u32 lp5_ckr;
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 	/*
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 	 * available mask, 1: available, 0: not available
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 	 * each bit represent a channel
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@@ -352,28 +360,56 @@
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 {
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 	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
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 	void __iomem *dfi_regs = info->regs;
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+	u32 mon_idx = 0, val_6 = 0;
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+	u32 i;
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365
 
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-	/* clear DDRMON_CTRL setting */
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-	writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
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+	if (info->mon_idx)
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+		mon_idx = info->mon_idx;
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368
 
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-	/* set ddr type to dfi */
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-	if (info->dram_type == LPDDR3 || info->dram_type == LPDDR2)
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-		writel_relaxed(LPDDR2_3_EN, dfi_regs + DDRMON_CTRL);
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-	else if (info->dram_type == LPDDR4 || info->dram_type == LPDDR4X)
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-		writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
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-	else if (info->dram_type == DDR4)
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-		writel_relaxed(DDR4_EN, dfi_regs + DDRMON_CTRL);
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+	if (info->dram_dynamic_info_reg)
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+		regmap_read(info->regmap_pmugrf, info->dram_dynamic_info_reg, &val_6);
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-	/* enable count, use software mode */
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-	writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL);
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+	if (info->dram_type == LPDDR5) {
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+		info->lp5_bank_mode = READ_LP5_BANK_MODE(val_6);
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+		info->lp5_ckr = READ_LP5_CKR(val_6);
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+	}
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+
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+	for (i = 0; i < MAX_DMC_NUM_CH; i++) {
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+		if (!(info->ch_msk & BIT(i)))
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+			continue;
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+		/* clear DDRMON_CTRL setting */
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+		writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + i * mon_idx + DDRMON_CTRL);
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+
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+		/* set ddr type to dfi */
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+		if (info->dram_type == LPDDR3 || info->dram_type == LPDDR2)
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+			writel_relaxed(LPDDR2_3_EN, dfi_regs + i * mon_idx + DDRMON_CTRL);
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+		else if (info->dram_type == LPDDR4 || info->dram_type == LPDDR4X)
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+			writel_relaxed(LPDDR4_EN, dfi_regs + i * mon_idx + DDRMON_CTRL);
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+		else if (info->dram_type == DDR4)
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+			writel_relaxed(DDR4_EN, dfi_regs + i * mon_idx + DDRMON_CTRL);
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+		else if (info->dram_type == LPDDR5)
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+			writel_relaxed(LPDDR5_EN | LPDDR5_BANK_MODE(info->lp5_bank_mode),
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+				       dfi_regs + i * mon_idx + DDRMON_CTRL);
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+
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+		/* enable count, use software mode */
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+		writel_relaxed(SOFTWARE_EN, dfi_regs + i * mon_idx + DDRMON_CTRL);
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+	}
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 }
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398
 
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 static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
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 {
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 	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
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 	void __iomem *dfi_regs = info->regs;
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+	u32 mon_idx = 0, i;
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404
 
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-	writel_relaxed(SOFTWARE_DIS, dfi_regs + DDRMON_CTRL);
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+	if (info->mon_idx)
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+		mon_idx = info->mon_idx;
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+
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+	for (i = 0; i < MAX_DMC_NUM_CH; i++) {
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+		if (!(info->ch_msk & BIT(i)))
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+			continue;
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+		writel_relaxed(SOFTWARE_DIS, dfi_regs + i * mon_idx + DDRMON_CTRL);
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+	}
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 }
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414
 
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 static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev)
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@@ -382,10 +418,12 @@
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 	u32 tmp, max = 0;
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 	u32 i, busier_ch = 0;
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 	void __iomem *dfi_regs = info->regs;
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-	u32 count_rate = 1;
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+	u32 mon_idx = 0x20, count_rate = 1;
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422
 
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 	rockchip_dfi_stop_hardware_counter(edev);
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+	if (info->mon_idx)
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+		mon_idx = info->mon_idx;
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 	if (info->count_rate)
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 		count_rate = info->count_rate;
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429
 
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@@ -394,14 +432,17 @@
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 		if (!(info->ch_msk & BIT(i)))
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 			continue;
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434
 
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+		/* rk3588 counter is dfi clk rate */
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 		info->ch_usage[i].total = readl_relaxed(dfi_regs +
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-				DDRMON_CH0_COUNT_NUM + i * 20) * count_rate;
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+				DDRMON_CH0_COUNT_NUM + i * mon_idx) * count_rate;
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438
 
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-		/* LPDDR4 and LPDDR4X BL = 16,other DDR type BL = 8 */
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+		/* LPDDR5 LPDDR4 and LPDDR4X BL = 16,other DDR type BL = 8 */
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 		tmp = readl_relaxed(dfi_regs +
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-				DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
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+				DDRMON_CH0_DFI_ACCESS_NUM + i * mon_idx);
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 		if (info->dram_type == LPDDR4 || info->dram_type == LPDDR4X)
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 			tmp *= 8;
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+		else if (info->dram_type == LPDDR5)
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+			tmp *= 16 / (4 << info->lp5_ckr);
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 		else
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 			tmp *= 4;
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 		info->ch_usage[i].access = tmp;
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@@ -473,6 +514,45 @@
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 	.get_event = rockchip_dfi_get_event,
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 	.set_event = rockchip_dfi_set_event,
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 };
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+
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+static __maybe_unused __init int rk3588_dfi_init(struct platform_device *pdev,
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+						 struct rockchip_dfi *data,
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+						 struct devfreq_event_desc *desc)
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+{
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+	struct device_node *np = pdev->dev.of_node;
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+	struct resource *res;
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+	u32 val_2, val_3, val_4;
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+
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+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+	data->regs = devm_ioremap_resource(&pdev->dev, res);
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+	if (IS_ERR(data->regs))
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+		return PTR_ERR(data->regs);
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+
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+	data->regmap_pmugrf = syscon_regmap_lookup_by_phandle(np, "rockchip,pmu_grf");
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+	if (IS_ERR(data->regmap_pmugrf))
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+		return PTR_ERR(data->regmap_pmugrf);
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+
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+	regmap_read(data->regmap_pmugrf, RK3588_PMUGRF_OS_REG(2), &val_2);
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+	regmap_read(data->regmap_pmugrf, RK3588_PMUGRF_OS_REG(3), &val_3);
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+	regmap_read(data->regmap_pmugrf, RK3588_PMUGRF_OS_REG(4), &val_4);
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+	if (READ_SYSREG_VERSION(val_3) >= 0x3)
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+		data->dram_type = READ_DRAMTYPE_INFO_V3(val_2, val_3);
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+	else
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+		data->dram_type = READ_DRAMTYPE_INFO(val_2);
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+
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+	data->mon_idx = 0x4000;
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+	if (data->dram_type == LPDDR5)
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+		data->count_rate = 1;
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+	else
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+		data->count_rate = 2;
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+	data->dram_dynamic_info_reg = RK3588_PMUGRF_OS_REG(6);
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+	data->ch_msk = READ_CH_INFO(val_2) | READ_CH_INFO(val_4) << 2;
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+	data->clk = NULL;
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+
552
+	desc->ops = &rockchip_dfi_ops;
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+
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+	return 0;
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+}
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556
 
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 static __maybe_unused __init int px30_dfi_init(struct platform_device *pdev,
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 					       struct rockchip_dfi *data,
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@@ -586,12 +666,10 @@
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 						   struct devfreq_event_desc *desc)
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 {
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 	struct device *dev = &pdev->dev;
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-	struct resource *res;
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669
 	struct device_node *np = pdev->dev.of_node, *node;
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 	u32 val;
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671
 
593
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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-	data->regs = devm_ioremap_resource(&pdev->dev, res);
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+	data->regs = devm_platform_ioremap_resource(pdev, 0);
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673
 	if (IS_ERR(data->regs))
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 		return PTR_ERR(data->regs);
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675
 
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@@ -605,6 +683,7 @@
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 	node = of_parse_phandle(np, "rockchip,pmu", 0);
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 	if (node) {
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 		data->regmap_pmu = syscon_node_to_regmap(node);
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+		of_node_put(node);
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 		if (IS_ERR(data->regmap_pmu))
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 			return PTR_ERR(data->regmap_pmu);
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 	}
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@@ -708,9 +787,15 @@
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 #ifdef CONFIG_CPU_RK3528
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 	{ .compatible = "rockchip,rk3528-dfi", .data = rk3528_dfi_init },
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 #endif
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+#ifdef CONFIG_CPU_RK3562
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+	{ .compatible = "rockchip,rk3562-dfi", .data = px30_dfi_init },
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+#endif
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 #ifdef CONFIG_CPU_RK3568
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 	{ .compatible = "rockchip,rk3568-dfi", .data = px30_dfi_init },
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 #endif
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+#ifdef CONFIG_CPU_RK3588
797
+	{ .compatible = "rockchip,rk3588-dfi", .data = rk3588_dfi_init },
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+#endif
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 #ifdef CONFIG_CPU_RV1126
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 	{ .compatible = "rockchip,rv1126-dfi", .data = px30_dfi_init },
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 #endif