hc
2024-02-19 1c055e55a242a33e574e48be530e06770a210dcd
kernel/arch/powerpc/include/asm/nohash/32/pte-40x.h
....@@ -33,7 +33,7 @@
3333 * is cleared in the TLB miss handler before the TLB entry is loaded.
3434 * - All other bits of the PTE are loaded into TLBLO without
3535 * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
36
- * software PTE bits. We actually use use bits 21, 24, 25, and
36
+ * software PTE bits. We actually use bits 21, 24, 25, and
3737 * 30 respectively for the software bits: ACCESSED, DIRTY, RW, and
3838 * PRESENT.
3939 */
....@@ -44,19 +44,45 @@
4444 #define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */
4545 #define _PAGE_USER 0x010 /* matches one of the zone permission bits */
4646 #define _PAGE_SPECIAL 0x020 /* software: Special page */
47
-#define _PAGE_RW 0x040 /* software: Writes permitted */
4847 #define _PAGE_DIRTY 0x080 /* software: dirty page */
49
-#define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */
48
+#define _PAGE_RW 0x100 /* hardware: WR, anded with dirty in exception */
5049 #define _PAGE_EXEC 0x200 /* hardware: EX permission */
5150 #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
5251
52
+/* No page size encoding in the linux PTE */
53
+#define _PAGE_PSIZE 0
54
+
55
+/* cache related flags non existing on 40x */
56
+#define _PAGE_COHERENT 0
57
+
58
+#define _PAGE_KERNEL_RO 0
59
+#define _PAGE_KERNEL_ROX _PAGE_EXEC
60
+#define _PAGE_KERNEL_RW (_PAGE_DIRTY | _PAGE_RW)
61
+#define _PAGE_KERNEL_RWX (_PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC)
62
+
5363 #define _PMD_PRESENT 0x400 /* PMD points to page of PTEs */
64
+#define _PMD_PRESENT_MASK _PMD_PRESENT
5465 #define _PMD_BAD 0x802
5566 #define _PMD_SIZE_4M 0x0c0
5667 #define _PMD_SIZE_16M 0x0e0
68
+#define _PMD_USER 0
69
+
70
+#define _PTE_NONE_MASK 0
5771
5872 /* Until my rework is finished, 40x still needs atomic PTE updates */
5973 #define PTE_ATOMIC_UPDATES 1
6074
75
+#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED)
76
+#define _PAGE_BASE (_PAGE_BASE_NC)
77
+
78
+/* Permission masks used to generate the __P and __S table */
79
+#define PAGE_NONE __pgprot(_PAGE_BASE)
80
+#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
81
+#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
82
+#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
83
+#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
84
+#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
85
+#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
86
+
6187 #endif /* __KERNEL__ */
6288 #endif /* _ASM_POWERPC_NOHASH_32_PTE_40x_H */