.. | .. |
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33 | 33 | * is cleared in the TLB miss handler before the TLB entry is loaded. |
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34 | 34 | * - All other bits of the PTE are loaded into TLBLO without |
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35 | 35 | * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for |
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36 | | - * software PTE bits. We actually use use bits 21, 24, 25, and |
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| 36 | + * software PTE bits. We actually use bits 21, 24, 25, and |
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37 | 37 | * 30 respectively for the software bits: ACCESSED, DIRTY, RW, and |
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38 | 38 | * PRESENT. |
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39 | 39 | */ |
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.. | .. |
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44 | 44 | #define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */ |
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45 | 45 | #define _PAGE_USER 0x010 /* matches one of the zone permission bits */ |
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46 | 46 | #define _PAGE_SPECIAL 0x020 /* software: Special page */ |
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47 | | -#define _PAGE_RW 0x040 /* software: Writes permitted */ |
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48 | 47 | #define _PAGE_DIRTY 0x080 /* software: dirty page */ |
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49 | | -#define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */ |
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| 48 | +#define _PAGE_RW 0x100 /* hardware: WR, anded with dirty in exception */ |
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50 | 49 | #define _PAGE_EXEC 0x200 /* hardware: EX permission */ |
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51 | 50 | #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */ |
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52 | 51 | |
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| 52 | +/* No page size encoding in the linux PTE */ |
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| 53 | +#define _PAGE_PSIZE 0 |
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| 54 | + |
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| 55 | +/* cache related flags non existing on 40x */ |
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| 56 | +#define _PAGE_COHERENT 0 |
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| 57 | + |
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| 58 | +#define _PAGE_KERNEL_RO 0 |
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| 59 | +#define _PAGE_KERNEL_ROX _PAGE_EXEC |
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| 60 | +#define _PAGE_KERNEL_RW (_PAGE_DIRTY | _PAGE_RW) |
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| 61 | +#define _PAGE_KERNEL_RWX (_PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC) |
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| 62 | + |
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53 | 63 | #define _PMD_PRESENT 0x400 /* PMD points to page of PTEs */ |
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| 64 | +#define _PMD_PRESENT_MASK _PMD_PRESENT |
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54 | 65 | #define _PMD_BAD 0x802 |
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55 | 66 | #define _PMD_SIZE_4M 0x0c0 |
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56 | 67 | #define _PMD_SIZE_16M 0x0e0 |
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| 68 | +#define _PMD_USER 0 |
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| 69 | + |
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| 70 | +#define _PTE_NONE_MASK 0 |
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57 | 71 | |
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58 | 72 | /* Until my rework is finished, 40x still needs atomic PTE updates */ |
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59 | 73 | #define PTE_ATOMIC_UPDATES 1 |
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60 | 74 | |
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| 75 | +#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) |
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| 76 | +#define _PAGE_BASE (_PAGE_BASE_NC) |
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| 77 | + |
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| 78 | +/* Permission masks used to generate the __P and __S table */ |
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| 79 | +#define PAGE_NONE __pgprot(_PAGE_BASE) |
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| 80 | +#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW) |
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| 81 | +#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC) |
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| 82 | +#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER) |
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| 83 | +#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) |
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| 84 | +#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER) |
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| 85 | +#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) |
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| 86 | + |
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61 | 87 | #endif /* __KERNEL__ */ |
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62 | 88 | #endif /* _ASM_POWERPC_NOHASH_32_PTE_40x_H */ |
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