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2024-02-19 1c055e55a242a33e574e48be530e06770a210dcd 
 kernel/arch/arm64/include/asm/insn.h
....@@ -1,27 +1,16 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Copyright (C) 2013 Huawei Ltd.
34  * Author: Jiang Liu <liuj97@gmail.com>
45  *
56  * Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com>
6
- *
7
- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
187  */
198 #ifndef	__ASM_INSN_H
209 #define	__ASM_INSN_H
10
+#include <linux/build_bug.h>
2111 #include <linux/types.h>
2212 
23
-/* A64 instructions are always 32 bits. */
24
-#define	AARCH64_INSN_SIZE		4
13
+#include <asm/alternative.h>
2514 
2615 #ifndef __ASSEMBLY__
2716 /*
....@@ -49,13 +38,38 @@
4938 					 * system instructions */
5039 };
5140 
52
-enum aarch64_insn_hint_op {
41
+enum aarch64_insn_hint_cr_op {
5342 	AARCH64_INSN_HINT_NOP	= 0x0 << 5,
5443 	AARCH64_INSN_HINT_YIELD	= 0x1 << 5,
5544 	AARCH64_INSN_HINT_WFE	= 0x2 << 5,
5645 	AARCH64_INSN_HINT_WFI	= 0x3 << 5,
5746 	AARCH64_INSN_HINT_SEV	= 0x4 << 5,
5847 	AARCH64_INSN_HINT_SEVL	= 0x5 << 5,
48
+
49
+	AARCH64_INSN_HINT_XPACLRI    = 0x07 << 5,
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+	AARCH64_INSN_HINT_PACIA_1716 = 0x08 << 5,
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+	AARCH64_INSN_HINT_PACIB_1716 = 0x0A << 5,
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+	AARCH64_INSN_HINT_AUTIA_1716 = 0x0C << 5,
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+	AARCH64_INSN_HINT_AUTIB_1716 = 0x0E << 5,
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+	AARCH64_INSN_HINT_PACIAZ     = 0x18 << 5,
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+	AARCH64_INSN_HINT_PACIASP    = 0x19 << 5,
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+	AARCH64_INSN_HINT_PACIBZ     = 0x1A << 5,
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+	AARCH64_INSN_HINT_PACIBSP    = 0x1B << 5,
58
+	AARCH64_INSN_HINT_AUTIAZ     = 0x1C << 5,
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+	AARCH64_INSN_HINT_AUTIASP    = 0x1D << 5,
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+	AARCH64_INSN_HINT_AUTIBZ     = 0x1E << 5,
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+	AARCH64_INSN_HINT_AUTIBSP    = 0x1F << 5,
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+
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+	AARCH64_INSN_HINT_ESB  = 0x10 << 5,
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+	AARCH64_INSN_HINT_PSB  = 0x11 << 5,
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+	AARCH64_INSN_HINT_TSB  = 0x12 << 5,
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+	AARCH64_INSN_HINT_CSDB = 0x14 << 5,
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+	AARCH64_INSN_HINT_CLEARBHB = 0x16 << 5,
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+
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+	AARCH64_INSN_HINT_BTI   = 0x20 << 5,
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+	AARCH64_INSN_HINT_BTIC  = 0x22 << 5,
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+	AARCH64_INSN_HINT_BTIJ  = 0x24 << 5,
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+	AARCH64_INSN_HINT_BTIJC = 0x26 << 5,
5973 };
6074 
6175 enum aarch64_insn_imm_type {
....@@ -261,11 +275,21 @@
261275 	AARCH64_INSN_PRFM_POLICY_STRM,
262276 };
263277 
264
-#define	__AARCH64_INSN_FUNCS(abbr, mask, val)	\
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-static __always_inline bool aarch64_insn_is_##abbr(u32 code) \
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-{ return (code & (mask)) == (val); } \
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-static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \
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-{ return (val); }
278
+enum aarch64_insn_adr_type {
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+	AARCH64_INSN_ADR_TYPE_ADRP,
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+	AARCH64_INSN_ADR_TYPE_ADR,
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+};
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+
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+#define	__AARCH64_INSN_FUNCS(abbr, mask, val)				\
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+static __always_inline bool aarch64_insn_is_##abbr(u32 code)		\
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+{									\
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+	BUILD_BUG_ON(~(mask) & (val));					\
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+	return (code & (mask)) == (val);				\
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+}									\
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+static __always_inline u32 aarch64_insn_get_##abbr##_value(void)	\
290
+{									\
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+	return (val);							\
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+}
269293 
270294 __AARCH64_INSN_FUNCS(adr,	0x9F000000, 0x10000000)
271295 __AARCH64_INSN_FUNCS(adrp,	0x9F000000, 0x90000000)
....@@ -335,16 +359,20 @@
335359 __AARCH64_INSN_FUNCS(exception,	0xFF000000, 0xD4000000)
336360 __AARCH64_INSN_FUNCS(hint,	0xFFFFF01F, 0xD503201F)
337361 __AARCH64_INSN_FUNCS(br,	0xFFFFFC1F, 0xD61F0000)
362
+__AARCH64_INSN_FUNCS(br_auth,	0xFEFFF800, 0xD61F0800)
338363 __AARCH64_INSN_FUNCS(blr,	0xFFFFFC1F, 0xD63F0000)
364
+__AARCH64_INSN_FUNCS(blr_auth,	0xFEFFF800, 0xD63F0800)
339365 __AARCH64_INSN_FUNCS(ret,	0xFFFFFC1F, 0xD65F0000)
366
+__AARCH64_INSN_FUNCS(ret_auth,	0xFFFFFBFF, 0xD65F0BFF)
340367 __AARCH64_INSN_FUNCS(eret,	0xFFFFFFFF, 0xD69F03E0)
368
+__AARCH64_INSN_FUNCS(eret_auth,	0xFFFFFBFF, 0xD69F0BFF)
341369 __AARCH64_INSN_FUNCS(mrs,	0xFFF00000, 0xD5300000)
342370 __AARCH64_INSN_FUNCS(msr_imm,	0xFFF8F01F, 0xD500401F)
343371 __AARCH64_INSN_FUNCS(msr_reg,	0xFFF00000, 0xD5100000)
344372 
345373 #undef	__AARCH64_INSN_FUNCS
346374 
347
-bool aarch64_insn_is_nop(u32 insn);
375
+bool aarch64_insn_is_steppable_hint(u32 insn);
348376 bool aarch64_insn_is_branch_imm(u32 insn);
349377 
350378 static inline bool aarch64_insn_is_adr_adrp(u32 insn)
....@@ -370,7 +398,7 @@
370398 				     enum aarch64_insn_branch_type type);
371399 u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
372400 				     enum aarch64_insn_condition cond);
373
-u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_op op);
401
+u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_cr_op op);
374402 u32 aarch64_insn_gen_nop(void);
375403 u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
376404 				enum aarch64_insn_branch_type type);
....@@ -401,6 +429,9 @@
401429 				 enum aarch64_insn_register src,
402430 				 int imm, enum aarch64_insn_variant variant,
403431 				 enum aarch64_insn_adsb_type type);
432
+u32 aarch64_insn_gen_adr(unsigned long pc, unsigned long addr,
433
+			 enum aarch64_insn_register reg,
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+			 enum aarch64_insn_adr_type type);
404435 u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
405436 			      enum aarch64_insn_register src,
406437 			      int immr, int imms,
....@@ -437,6 +468,9 @@
437468 					 int shift,
438469 					 enum aarch64_insn_variant variant,
439470 					 enum aarch64_insn_logic_type type);
471
+u32 aarch64_insn_gen_move_reg(enum aarch64_insn_register dst,
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+			      enum aarch64_insn_register src,
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+			      enum aarch64_insn_variant variant);
440474 u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type,
441475 				       enum aarch64_insn_variant variant,
442476 				       enum aarch64_insn_register Rn,