forked from ~ljy/RK356X_SDK_RELEASE

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hc
2023-11-06 15ade055295d13f95d49e3d99b09f3bbfb4a43e7 
 kernel/drivers/video/rockchip/rga3/rga3_reg_info.c
....@@ -8,6 +8,8 @@
88 #define pr_fmt(fmt) "rga3_reg: " fmt
99 
1010 #include "rga3_reg_info.h"
11
+#include "rga_dma_buf.h"
12
+#include "rga_iommu.h"
1113 #include "rga_common.h"
1214 #include "rga_debugger.h"
1315 #include "rga_hw_config.h"
....@@ -91,14 +93,12 @@
9193 	dw = msg->win0.dst_act_w;
9294 	dh = msg->win0.dst_act_h;
9395 
94
-	if (msg->win0.rotate_mode != 0) {
95
-		if (rotate_mode) {
96
-			sh = msg->win0.src_act_w;
97
-			sw = msg->win0.src_act_h;
98
-		} else {
99
-			sw = msg->win0.src_act_w;
100
-			sh = msg->win0.src_act_h;
101
-		}
96
+	if (rotate_mode) {
97
+		sh = msg->win0.src_act_w;
98
+		sw = msg->win0.src_act_h;
99
+	} else {
100
+		sw = msg->win0.src_act_w;
101
+		sh = msg->win0.src_act_h;
102102 	}
103103 
104104 	if (sw > dw) {
....@@ -289,7 +289,7 @@
289289 	}
290290 
291291 	/* rotate & mirror */
292
-	if (msg->win1.yrgb_addr == 0) {
292
+	if (msg->win0.rotate_mode == 1) {
293293 		reg =
294294 			((reg & (~m_RGA3_WIN0_RD_CTRL_SW_WIN0_ROT)) |
295295 			 (s_RGA3_WIN0_RD_CTRL_SW_WIN0_ROT(rotate_mode)));
....@@ -299,36 +299,23 @@
299299 		reg =
300300 			((reg & (~m_RGA3_WIN0_RD_CTRL_SW_WIN0_YMIRROR)) |
301301 			 (s_RGA3_WIN0_RD_CTRL_SW_WIN0_YMIRROR(ymirror)));
302
-
303
-		/* scale */
304
-		*bRGA3_WIN0_SCL_FAC = param_x | param_y << 16;
305
-
306
-		reg =
307
-			((reg & (~m_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_BY)) |
308
-			 (s_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_BY(x_by)));
309
-		reg =
310
-			((reg & (~m_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_UP)) |
311
-			 (s_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_UP(x_up)));
312
-		reg =
313
-			((reg & (~m_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_BY)) |
314
-			 (s_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_BY(y_by)));
315
-		reg =
316
-			((reg & (~m_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_UP)) |
317
-			 (s_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_UP(y_up)));
318
-	} else {
319
-		reg =
320
-			((reg & (~m_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_BY)) |
321
-			 (s_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_BY(1)));
322
-		reg =
323
-			((reg & (~m_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_UP)) |
324
-			 (s_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_UP(0)));
325
-		reg =
326
-			((reg & (~m_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_BY)) |
327
-			 (s_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_BY(1)));
328
-		reg =
329
-			((reg & (~m_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_UP)) |
330
-			 (s_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_UP(0)));
331302 	}
303
+
304
+	/* scale */
305
+	*bRGA3_WIN0_SCL_FAC = param_x | param_y << 16;
306
+
307
+	reg =
308
+		((reg & (~m_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_BY)) |
309
+			(s_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_BY(x_by)));
310
+	reg =
311
+		((reg & (~m_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_UP)) |
312
+			(s_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_UP(x_up)));
313
+	reg =
314
+		((reg & (~m_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_BY)) |
315
+			(s_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_BY(y_by)));
316
+	reg =
317
+		((reg & (~m_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_UP)) |
318
+			(s_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_UP(y_up)));
332319 
333320 	/* rd_mode */
334321 	reg =
....@@ -357,19 +344,36 @@
357344 
358345 	*bRGA3_WIN0_RD_CTRL = reg;
359346 
360
-	/* stride need align to 16 */
361
-	if (msg->win0.rd_mode != 1)
347
+	switch (msg->win0.rd_mode) {
348
+	case 0: /* raster */
362349 		stride = (((msg->win0.vir_w * pixel_width) + 15) & ~15) >> 2;
363
-	else
364
-		stride = ((msg->win0.vir_w + 15) & ~15) >> 2;
350
+		if (rga_is_yuv420_semi_planar_format(msg->win0.format))
351
+			uv_stride = ((msg->win0.vir_w + 15) & ~15) >> 2;
352
+		else
353
+			uv_stride = stride;
354
+		break;
365355 
366
-	if (msg->win0.format == RGA_FORMAT_YCbCr_420_SP
367
-		|| msg->win0.format == RGA_FORMAT_YCrCb_420_SP
368
-		|| msg->win0.format == RGA_FORMAT_YCbCr_420_SP_10B
369
-		|| msg->win0.format == RGA_FORMAT_YCrCb_420_SP_10B)
370
-		uv_stride = ((msg->win0.vir_w + 15) & ~15) >> 2;
371
-	else
372
-		uv_stride = stride;
356
+	case 1: /* fbc */
357
+		stride = ((msg->win0.vir_w + 15) & ~15) >> 2;
358
+		if (rga_is_yuv420_semi_planar_format(msg->win0.format))
359
+			uv_stride = ((msg->win0.vir_w + 15) & ~15) >> 2;
360
+		else
361
+			uv_stride = stride;
362
+		break;
363
+
364
+	case 2: /* tile 8*8 */
365
+		/*
366
+		 * tile 8*8 mode 8 lines of data are read/written at one time,
367
+		 * so stride needs * 8. YUV420 only has 4 lines of UV data, so
368
+		 * it needs to >>1.
369
+		 */
370
+		stride = (((msg->win0.vir_w * pixel_width * 8) + 15) & ~15) >> 2;
371
+		if (rga_is_yuv420_semi_planar_format(msg->win0.format))
372
+			uv_stride = ((((msg->win0.vir_w * 8) + 15) & ~15) >> 1) >> 2;
373
+		else
374
+			uv_stride = stride;
375
+		break;
376
+	}
373377 
374378 	*bRGA3_WIN0_Y_BASE = (u32) msg->win0.yrgb_addr;
375379 	*bRGA3_WIN0_U_BASE = (u32) msg->win0.uv_addr;
....@@ -386,9 +390,9 @@
386390 	 */
387391 
388392 	/* do not use win0 src size except fbcd */
389
-	*bRGA3_WIN0_SRC_SIZE = (msg->win0.src_act_w +
390
-		msg->win0.x_offset) | ((msg->win0.y_offset +
391
-		msg->win0.src_act_h) << 16);
393
+	/* in FBCD, src_width needs to be aligned at 16 */
394
+	*bRGA3_WIN0_SRC_SIZE = ALIGN(msg->win0.src_act_w + msg->win0.x_offset, 16) |
395
+			       (ALIGN(msg->win0.y_offset + msg->win0.src_act_h, 16) << 16);
392396 	*bRGA3_WIN0_ACT_SIZE =
393397 		msg->win0.src_act_w | (msg->win0.src_act_h << 16);
394398 	*bRGA3_WIN0_DST_SIZE =
....@@ -721,19 +725,31 @@
721725 
722726 	*bRGA3_WIN1_RD_CTRL = reg;
723727 
724
-	/* stride need align to 16 */
725
-	if (msg->win1.rd_mode != 1)
728
+	switch (msg->win1.rd_mode) {
729
+	case 0: /* raster */
726730 		stride = (((msg->win1.vir_w * pixel_width) + 15) & ~15) >> 2;
727
-	else
728
-		stride = ((msg->win1.vir_w + 15) & ~15) >> 2;
731
+		if (rga_is_yuv420_semi_planar_format(msg->win1.format))
732
+			uv_stride = ((msg->win1.vir_w + 15) & ~15) >> 2;
733
+		else
734
+			uv_stride = stride;
735
+		break;
729736 
730
-	if (msg->win1.format == RGA_FORMAT_YCbCr_420_SP
731
-		|| msg->win1.format == RGA_FORMAT_YCrCb_420_SP
732
-		|| msg->win1.format == RGA_FORMAT_YCbCr_420_SP_10B
733
-		|| msg->win1.format == RGA_FORMAT_YCrCb_420_SP_10B)
734
-		uv_stride = ((msg->win1.vir_w + 15) & ~15) >> 2;
735
-	else
736
-		uv_stride = stride;
737
+	case 1: /* fbc */
738
+		stride = ((msg->win1.vir_w + 15) & ~15) >> 2;
739
+		if (rga_is_yuv420_semi_planar_format(msg->win1.format))
740
+			uv_stride = ((msg->win1.vir_w + 15) & ~15) >> 2;
741
+		else
742
+			uv_stride = stride;
743
+		break;
744
+
745
+	case 2: /* tile 8*8 */
746
+		stride = (((msg->win1.vir_w * pixel_width * 8) + 15) & ~15) >> 2;
747
+		if (rga_is_yuv420_semi_planar_format(msg->win1.format))
748
+			uv_stride = ((((msg->win1.vir_w * 8) + 15) & ~15) >> 1) >> 2;
749
+		else
750
+			uv_stride = stride;
751
+		break;
752
+	}
737753 
738754 	*bRGA3_WIN1_Y_BASE = (u32) msg->win1.yrgb_addr;
739755 	*bRGA3_WIN1_U_BASE = (u32) msg->win1.uv_addr;
....@@ -947,16 +963,20 @@
947963 	*bRGA3_WR_RD_CTRL = reg;
948964 	*bRGA3_WR_FBCD_CTRL = fbcd_reg;
949965 
950
-	/* stride need align to 16 */
951
-	if (msg->wr.rd_mode != 1) {
966
+	switch (msg->wr.rd_mode) {
967
+	case 0: /* raster */
952968 		stride = (((msg->wr.vir_w * pixel_width) + 15) & ~15) >> 2;
953
-		*bRGA3_WR_U_BASE = (u32) msg->wr.uv_addr;
954969 		uv_stride = ((msg->wr.vir_w + 15) & ~15) >> 2;
955
-	} else {
970
+
971
+		*bRGA3_WR_U_BASE = (u32) msg->wr.uv_addr;
972
+
973
+		break;
974
+
975
+	case 1: /* fbc */
956976 		stride = ((msg->wr.vir_w + 15) & ~15) >> 2;
957977 		/* need to calculate fbcd header size */
958978 		vir_h = ((msg->wr.vir_h + 15) & ~15);
959
-		*bRGA3_WR_U_BASE = (u32) (msg->wr.uv_addr + ((stride * vir_h)>>2));
979
+
960980 		/* RGBA8888 */
961981 		if (wr_format == 0x6)
962982 			uv_stride = ((msg->wr.vir_w + 15) & ~15);
....@@ -972,6 +992,20 @@
972992 		/* yuv422 10bit */
973993 		else if (wr_format == 0x3)
974994 			uv_stride = (((msg->wr.vir_w + 15) & ~15) >> 3) * 5;
995
+
996
+		*bRGA3_WR_U_BASE = (u32) (msg->wr.uv_addr + ((stride * vir_h)>>2));
997
+
998
+		break;
999
+
1000
+	case 2: /* tile 8*8 */
1001
+		stride = (((msg->wr.vir_w * pixel_width * 8) + 15) & ~15) >> 2;
1002
+		if (rga_is_yuv420_semi_planar_format(msg->win0.format))
1003
+			uv_stride = ((((msg->wr.vir_w * 8) + 15) & ~15) >> 1) >> 2;
1004
+		else
1005
+			uv_stride = stride;
1006
+
1007
+		*bRGA3_WR_U_BASE = (u32) msg->wr.uv_addr;
1008
+		break;
9751009 	}
9761010 
9771011 	*bRGA3_WR_Y_BASE = (u32) msg->wr.yrgb_addr;
....@@ -1141,7 +1175,7 @@
11411175 	*bRGA3_OVLP_OFF = msg->wr.x_offset | (msg->wr.y_offset << 16);
11421176 }
11431177 
1144
-int rga3_gen_reg_info(u8 *base, struct rga3_req *msg)
1178
+static int rga3_gen_reg_info(u8 *base, struct rga3_req *msg)
11451179 {
11461180 	switch (msg->render_mode) {
11471181 	case BITBLT_MODE:
....@@ -1225,7 +1259,7 @@
12251259 }
12261260 
12271261 /* TODO: common part */
1228
-void rga_cmd_to_rga3_cmd(struct rga_req *req_rga, struct rga3_req *req)
1262
+static void rga_cmd_to_rga3_cmd(struct rga_req *req_rga, struct rga3_req *req)
12291263 {
12301264 	u16 alpha_mode_0, alpha_mode_1;
12311265 	struct rga_img_info_t tmp;
....@@ -1385,18 +1419,18 @@
13851419 			if (req->win0.x_offset || req->win0.y_offset) {
13861420 				req->win0.src_act_w = req->win0.src_act_w + req->win0.x_offset;
13871421 				req->win0.src_act_h = req->win0.src_act_h + req->win0.y_offset;
1388
-				req->win0.dst_act_w = req_rga->pat.act_w + req->win0.x_offset;
1389
-				req->win0.dst_act_h = req_rga->pat.act_h + req->win0.y_offset;
1422
+				req->win0.dst_act_w = req_rga->dst.act_w + req->win0.x_offset;
1423
+				req->win0.dst_act_h = req_rga->dst.act_h + req->win0.y_offset;
13901424 
13911425 				req->win0.x_offset = 0;
13921426 				req->win0.y_offset = 0;
13931427 			} else {
1394
-				req->win0.dst_act_w = req_rga->pat.act_w;
1395
-				req->win0.dst_act_h = req_rga->pat.act_h;
1428
+				req->win0.dst_act_w = req_rga->dst.act_w;
1429
+				req->win0.dst_act_h = req_rga->dst.act_h;
13961430 			}
13971431 			/* set win1 dst size */
1398
-			req->win1.dst_act_w = req_rga->pat.act_w;
1399
-			req->win1.dst_act_h = req_rga->pat.act_h;
1432
+			req->win1.dst_act_w = req_rga->dst.act_w;
1433
+			req->win1.dst_act_h = req_rga->dst.act_h;
14001434 		} else {
14011435 			/* A+B->B mode */
14021436 			set_win_info(&req->win0, &req_rga->dst);
....@@ -1589,54 +1623,38 @@
15891623 	}
15901624 }
15911625 
1592
-void rga3_soft_reset(struct rga_scheduler_t *scheduler)
1626
+static void rga3_soft_reset(struct rga_scheduler_t *scheduler)
15931627 {
15941628 	u32 i;
1595
-	u32 reg;
1596
-	u32 mmu_addr;
1629
+	u32 iommu_dte_addr = 0;
15971630 
1598
-	mmu_addr = rga_read(0xf00, scheduler);
1631
+	if (scheduler->data->mmu == RGA_IOMMU)
1632
+		iommu_dte_addr = rga_read(RGA_IOMMU_DTE_ADDR, scheduler);
15991633 
1600
-	rga_write((1 << 3) | (1 << 4), RGA3_SYS_CTRL, scheduler);
1601
-
1602
-	pr_err("soft reset sys_ctrl = %x, ro_rest = %x",
1603
-		rga_read(RGA3_SYS_CTRL, scheduler),
1604
-		rga_read(RGA3_RO_SRST, scheduler));
1605
-
1606
-	mdelay(20);
1607
-
1608
-	pr_err("soft reset sys_ctrl = %x, ro_rest = %x",
1609
-		rga_read(RGA3_SYS_CTRL, scheduler),
1610
-		rga_read(RGA3_RO_SRST, scheduler));
1611
-
1612
-	rga_write((0 << 3) | (0 << 4), RGA3_SYS_CTRL, scheduler);
1613
-
1614
-	pr_err("soft after reset sys_ctrl = %x, ro_rest = %x",
1615
-		rga_read(RGA3_SYS_CTRL, scheduler),
1616
-		rga_read(RGA3_RO_SRST, scheduler));
1617
-
1618
-	rga_write(1, RGA3_INT_CLR, scheduler);
1619
-
1620
-	rga_write(mmu_addr, 0xf00, scheduler);
1621
-	rga_write(0, 0xf08, scheduler);
1622
-
1623
-	if (DEBUGGER_EN(INT_FLAG))
1624
-		pr_info("irq INT[%x], STATS0[%x], STATS1[%x]\n",
1625
-			rga_read(RGA3_INT_RAW, scheduler),
1626
-			rga_read(RGA3_STATUS0, scheduler),
1627
-			rga_read(RGA3_STATUS1, scheduler));
1634
+	rga_write(s_RGA3_SYS_CTRL_CCLK_SRESET(1) | s_RGA3_SYS_CTRL_ACLK_SRESET(1),
1635
+		  RGA3_SYS_CTRL, scheduler);
16281636 
16291637 	for (i = 0; i < RGA_RESET_TIMEOUT; i++) {
1630
-		reg = rga_read(RGA3_SYS_CTRL, scheduler) & 1;
1631
-
1632
-		if (reg == 0)
1638
+		if (rga_read(RGA3_RO_SRST, scheduler) & m_RGA3_RO_SRST_RO_RST_DONE)
16331639 			break;
16341640 
16351641 		udelay(1);
16361642 	}
16371643 
1644
+	rga_write(s_RGA3_SYS_CTRL_CCLK_SRESET(0) | s_RGA3_SYS_CTRL_ACLK_SRESET(0),
1645
+		  RGA3_SYS_CTRL, scheduler);
1646
+
1647
+	if (scheduler->data->mmu == RGA_IOMMU) {
1648
+		rga_write(iommu_dte_addr, RGA_IOMMU_DTE_ADDR, scheduler);
1649
+		/* enable iommu */
1650
+		rga_write(RGA_IOMMU_CMD_ENABLE_PAGING, RGA_IOMMU_COMMAND, scheduler);
1651
+	}
1652
+
16381653 	if (i == RGA_RESET_TIMEOUT)
1639
-		pr_err("soft reset timeout.\n");
1654
+		pr_err("RGA3 soft reset timeout. SYS_CTRL[0x%x], RO_SRST[0x%x]\n",
1655
+		       rga_read(RGA3_SYS_CTRL, scheduler), rga_read(RGA3_RO_SRST, scheduler));
1656
+	else
1657
+		pr_info("RGA3 soft reset complete.\n");
16401658 }
16411659 
16421660 static int rga3_scale_check(const struct rga3_req *req)
....@@ -1836,7 +1854,7 @@
18361854 	return 0;
18371855 }
18381856 
1839
-int rga3_init_reg(struct rga_job *job)
1857
+static int rga3_init_reg(struct rga_job *job)
18401858 {
18411859 	struct rga3_req req;
18421860 	int ret = 0;
....@@ -1893,29 +1911,24 @@
18931911 			cmd_reg[2 + i * 4], cmd_reg[3 + i * 4]);
18941912 }
18951913 
1896
-int rga3_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
1914
+static int rga3_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
18971915 {
1916
+	int i;
1917
+	bool master_mode_en;
1918
+	uint32_t sys_ctrl;
18981919 	ktime_t now = ktime_get();
18991920 
1900
-	//rga_dma_flush_range(&job->cmd_reg[0], &job->cmd_reg[50], scheduler);
1901
-
1902
-	rga_write(0x0, RGA3_SYS_CTRL, scheduler);
1903
-
1904
-#if 0
1905
-	/* CMD buff */
1906
-	rga_write(virt_to_phys(job->cmd_reg), RGA3_CMD_ADDR, scheduler);
1907
-#else
1908
-	{
1909
-		int32_t m, *cmd;
1910
-
1911
-		cmd = job->cmd_reg;
1912
-		for (m = 0; m <= 50; m++)
1913
-			rga_write(cmd[m], 0x100 + m * 4, scheduler);
1914
-	}
1915
-#endif
1921
+	/*
1922
+	 * Currently there is no iova allocated for storing cmd for the IOMMU device,
1923
+	 * so the iommu device needs to use the slave mode.
1924
+	 */
1925
+	if (scheduler->data->mmu != RGA_IOMMU)
1926
+		master_mode_en = true;
1927
+	else
1928
+		master_mode_en = false;
19161929 
19171930 	if (DEBUGGER_EN(REG)) {
1918
-		int32_t i, *p;
1931
+		uint32_t *p;
19191932 
19201933 		p = job->cmd_reg;
19211934 		pr_info("CMD_REG\n");
....@@ -1925,27 +1938,39 @@
19251938 				p[2 + i * 4], p[3 + i * 4]);
19261939 	}
19271940 
1928
-#if 0
1929
-	/* master mode */
1930
-	rga_write((0x1 << 1) | (0x1 << 2) | (0x1 << 5) | (0x1 << 6),
1931
-		 RGA3_SYS_CTRL, scheduler);
1932
-#else
1933
-	/* slave mode */
1934
-	//rga_write(1, 0xf08, scheduler);
1935
-#endif
1936
-
19371941 	/* All CMD finish int */
1938
-	rga_write(1, RGA3_INT_EN, scheduler);
1942
+	rga_write(m_RGA3_INT_FRM_DONE | m_RGA3_INT_CMD_LINE_FINISH | m_RGA3_INT_ERROR_MASK,
1943
+		  RGA3_INT_EN, scheduler);
19391944 
1940
-	if (DEBUGGER_EN(MSG)) {
1941
-		pr_info("sys_ctrl = %x, int_en = %x, int_raw = %x\n",
1945
+	if (master_mode_en) {
1946
+		/* master mode */
1947
+		sys_ctrl = s_RGA3_SYS_CTRL_CMD_MODE(1);
1948
+
1949
+		/* cmd buffer flush cache to ddr */
1950
+		rga_dma_sync_flush_range(&job->cmd_reg[0], &job->cmd_reg[50], scheduler);
1951
+
1952
+		rga_write(virt_to_phys(job->cmd_reg), RGA3_CMD_ADDR, scheduler);
1953
+		rga_write(sys_ctrl, RGA3_SYS_CTRL, scheduler);
1954
+		rga_write(m_RGA3_CMD_CTRL_CMD_LINE_ST_P, RGA3_CMD_CTRL, scheduler);
1955
+	} else {
1956
+		/* slave mode */
1957
+		sys_ctrl = s_RGA3_SYS_CTRL_CMD_MODE(0) | m_RGA3_SYS_CTRL_RGA_SART;
1958
+
1959
+		for (i = 0; i <= 50; i++)
1960
+			rga_write(job->cmd_reg[i], 0x100 + i * 4, scheduler);
1961
+
1962
+		rga_write(sys_ctrl, RGA3_SYS_CTRL, scheduler);
1963
+	}
1964
+
1965
+	if (DEBUGGER_EN(REG)) {
1966
+		pr_info("sys_ctrl = 0x%x, int_en = 0x%x, int_raw = 0x%x\n",
19421967 			rga_read(RGA3_SYS_CTRL, scheduler),
19431968 			rga_read(RGA3_INT_EN, scheduler),
19441969 			rga_read(RGA3_INT_RAW, scheduler));
19451970 
1946
-		pr_info("status0 = %x, status1 = %x\n",
1971
+		pr_info("hw_status = 0x%x, cmd_status = 0x%x\n",
19471972 			rga_read(RGA3_STATUS0, scheduler),
1948
-			rga_read(RGA3_STATUS1, scheduler));
1973
+			rga_read(RGA3_CMD_STATE, scheduler));
19491974 	}
19501975 
19511976 	if (DEBUGGER_EN(TIME))
....@@ -1954,15 +1979,13 @@
19541979 	job->hw_running_time = now;
19551980 	job->hw_recoder_time = now;
19561981 
1957
-	rga_write(1, RGA3_SYS_CTRL, scheduler);
1958
-
19591982 	if (DEBUGGER_EN(REG))
19601983 		rga3_dump_read_back_reg(scheduler);
19611984 
19621985 	return 0;
19631986 }
19641987 
1965
-int rga3_get_version(struct rga_scheduler_t *scheduler)
1988
+static int rga3_get_version(struct rga_scheduler_t *scheduler)
19661989 {
19671990 	u32 major_version, minor_version, svn_version;
19681991 	u32 reg_version;
....@@ -1987,3 +2010,80 @@
19872010 
19882011 	return 0;
19892012 }
2013
+
2014
+static int rga3_irq(struct rga_scheduler_t *scheduler)
2015
+{
2016
+	struct rga_job *job = scheduler->running_job;
2017
+
2018
+	if (job == NULL)
2019
+		return IRQ_HANDLED;
2020
+
2021
+	if (test_bit(RGA_JOB_STATE_INTR_ERR, &job->state))
2022
+		return IRQ_WAKE_THREAD;
2023
+
2024
+	job->intr_status = rga_read(RGA3_INT_RAW, scheduler);
2025
+	job->hw_status = rga_read(RGA3_STATUS0, scheduler);
2026
+	job->cmd_status = rga_read(RGA3_CMD_STATE, scheduler);
2027
+
2028
+	if (DEBUGGER_EN(INT_FLAG))
2029
+		pr_info("irq handler, INTR[0x%x], HW_STATUS[0x%x], CMD_STATUS[0x%x]\n",
2030
+			job->intr_status, job->hw_status, job->cmd_status);
2031
+
2032
+	if (job->intr_status & (m_RGA3_INT_FRM_DONE | m_RGA3_INT_CMD_LINE_FINISH)) {
2033
+		set_bit(RGA_JOB_STATE_FINISH, &job->state);
2034
+	} else if (job->intr_status & m_RGA3_INT_ERROR_MASK) {
2035
+		set_bit(RGA_JOB_STATE_INTR_ERR, &job->state);
2036
+
2037
+		pr_err("irq handler err! INTR[0x%x], HW_STATUS[0x%x], CMD_STATUS[0x%x]\n",
2038
+		       job->intr_status, job->hw_status, job->cmd_status);
2039
+		scheduler->ops->soft_reset(scheduler);
2040
+	}
2041
+
2042
+	/*clear INTR */
2043
+	rga_write(m_RGA3_INT_FRM_DONE | m_RGA3_INT_CMD_LINE_FINISH | m_RGA3_INT_ERROR_MASK,
2044
+		  RGA3_INT_CLR, scheduler);
2045
+
2046
+	return IRQ_WAKE_THREAD;
2047
+}
2048
+
2049
+static int rga3_isr_thread(struct rga_job *job, struct rga_scheduler_t *scheduler)
2050
+{
2051
+	if (DEBUGGER_EN(INT_FLAG))
2052
+		pr_info("isr thread, INTR[0x%x], HW_STATUS[0x%x], CMD_STATUS[0x%x]\n",
2053
+			rga_read(RGA3_INT_RAW, scheduler),
2054
+			rga_read(RGA3_STATUS0, scheduler),
2055
+			rga_read(RGA3_CMD_STATE, scheduler));
2056
+
2057
+	if (test_bit(RGA_JOB_STATE_INTR_ERR, &job->state)) {
2058
+		if (job->intr_status & m_RGA3_INT_RAG_MI_RD_BUS_ERR) {
2059
+			pr_err("DMA read bus error, please check size of the input_buffer or whether the buffer has been freed.\n");
2060
+			job->ret = -EFAULT;
2061
+		} else if (job->intr_status & m_RGA3_INT_WIN0_FBCD_DEC_ERR) {
2062
+			pr_err("win0 FBC decoder error, please check the fbc image of the source.\n");
2063
+			job->ret = -EFAULT;
2064
+		} else if (job->intr_status & m_RGA3_INT_WIN1_FBCD_DEC_ERR) {
2065
+			pr_err("win1 FBC decoder error, please check the fbc image of the source.\n");
2066
+			job->ret = -EFAULT;
2067
+		} else if (job->intr_status & m_RGA3_INT_RGA_MI_WR_BUS_ERR) {
2068
+			pr_err("wr buss error, please check size of the output_buffer or whether the buffer has been freed.\n");
2069
+			job->ret = -EFAULT;
2070
+		}
2071
+
2072
+		if (job->ret == 0) {
2073
+			pr_err("rga intr error[0x%x]!\n", job->intr_status);
2074
+			job->ret = -EFAULT;
2075
+		}
2076
+	}
2077
+
2078
+	return IRQ_HANDLED;
2079
+}
2080
+
2081
+const struct rga_backend_ops rga3_ops = {
2082
+	.get_version = rga3_get_version,
2083
+	.set_reg = rga3_set_reg,
2084
+	.init_reg = rga3_init_reg,
2085
+	.soft_reset = rga3_soft_reset,
2086
+	.read_back_reg = NULL,
2087
+	.irq = rga3_irq,
2088
+	.isr_thread = rga3_isr_thread,
2089
+};