| .. | .. |
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| 32 | 32 | sync_cache_w(&pen_release); |
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| 33 | 33 | } |
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| 34 | 34 | |
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| 35 | | -static DEFINE_SPINLOCK(boot_lock); |
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| 35 | +static DEFINE_RAW_SPINLOCK(boot_lock); |
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| 36 | 36 | |
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| 37 | 37 | void versatile_secondary_init(unsigned int cpu) |
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| 38 | 38 | { |
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| .. | .. |
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| 45 | 45 | /* |
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| 46 | 46 | * Synchronise with the boot thread. |
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| 47 | 47 | */ |
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| 48 | | - spin_lock(&boot_lock); |
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| 49 | | - spin_unlock(&boot_lock); |
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| 48 | + raw_spin_lock(&boot_lock); |
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| 49 | + raw_spin_unlock(&boot_lock); |
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| 50 | 50 | } |
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| 51 | 51 | |
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| 52 | 52 | int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle) |
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| .. | .. |
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| 57 | 57 | * Set synchronisation state between this boot processor |
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| 58 | 58 | * and the secondary one |
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| 59 | 59 | */ |
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| 60 | | - spin_lock(&boot_lock); |
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| 60 | + raw_spin_lock(&boot_lock); |
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| 61 | 61 | |
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| 62 | 62 | /* |
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| 63 | 63 | * This is really belt and braces; we hold unintended secondary |
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| .. | .. |
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| 87 | 87 | * now the secondary core is starting up let it run its |
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| 88 | 88 | * calibrations, then wait for it to finish |
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| 89 | 89 | */ |
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| 90 | | - spin_unlock(&boot_lock); |
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| 90 | + raw_spin_unlock(&boot_lock); |
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| 91 | 91 | |
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| 92 | 92 | return pen_release != -1 ? -ENOSYS : 0; |
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| 93 | 93 | } |
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