| .. | .. |
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| 239 | 239 | sync_cache_w(&pen_release); |
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| 240 | 240 | } |
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| 241 | 241 | |
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| 242 | | -static DEFINE_SPINLOCK(boot_lock); |
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| 242 | +static DEFINE_RAW_SPINLOCK(boot_lock); |
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| 243 | 243 | |
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| 244 | 244 | static void exynos_secondary_init(unsigned int cpu) |
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| 245 | 245 | { |
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| .. | .. |
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| 252 | 252 | /* |
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| 253 | 253 | * Synchronise with the boot thread. |
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| 254 | 254 | */ |
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| 255 | | - spin_lock(&boot_lock); |
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| 256 | | - spin_unlock(&boot_lock); |
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| 255 | + raw_spin_lock(&boot_lock); |
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| 256 | + raw_spin_unlock(&boot_lock); |
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| 257 | 257 | } |
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| 258 | 258 | |
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| 259 | 259 | int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr) |
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| .. | .. |
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| 317 | 317 | * Set synchronisation state between this boot processor |
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| 318 | 318 | * and the secondary one |
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| 319 | 319 | */ |
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| 320 | | - spin_lock(&boot_lock); |
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| 320 | + raw_spin_lock(&boot_lock); |
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| 321 | 321 | |
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| 322 | 322 | /* |
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| 323 | 323 | * The secondary processor is waiting to be released from |
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| .. | .. |
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| 344 | 344 | |
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| 345 | 345 | if (timeout == 0) { |
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| 346 | 346 | printk(KERN_ERR "cpu1 power enable failed"); |
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| 347 | | - spin_unlock(&boot_lock); |
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| 347 | + raw_spin_unlock(&boot_lock); |
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| 348 | 348 | return -ETIMEDOUT; |
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| 349 | 349 | } |
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| 350 | 350 | } |
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| .. | .. |
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| 390 | 390 | * calibrations, then wait for it to finish |
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| 391 | 391 | */ |
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| 392 | 392 | fail: |
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| 393 | | - spin_unlock(&boot_lock); |
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| 393 | + raw_spin_unlock(&boot_lock); |
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| 394 | 394 | |
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| 395 | 395 | return pen_release != -1 ? ret : 0; |
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| 396 | 396 | } |
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