~hc/RK356X_SDK_RELEASE.git

..	..	@@ -19,11 +19,20 @@
19	19	#include <sound/tlv.h>
20	20
21	21	#include "rockchip_sai.h"
	22	+#include "rockchip_dlp_pcm.h"
	23	+#include "rockchip_utils.h"
22	24
23	25	#define DRV_NAME "rockchip-sai"
24	26
	27	+#define CLK_SHIFT_RATE_HZ_MAX 5
25	28	#define FW_RATIO_MAX 8
26	29	#define FW_RATIO_MIN 1
	30	+#define MAXBURST_PER_FIFO 8
	31	+
	32	+#define DEFAULT_FS 48000
	33	+#define TIMEOUT_US 1000
	34	+#define WAIT_TIME_MS_MAX 10000
	35	+#define QUIRK_ALWAYS_ON BIT(0)
27	36
28	37	enum fpw_mode {
29	38	FPW_ONE_BCLK_WIDTH,
..	..	@@ -41,14 +50,30 @@
41	50	struct snd_dmaengine_dai_dma_data capture_dma_data;
42	51	struct snd_dmaengine_dai_dma_data playback_dma_data;
43	52	struct snd_pcm_substream *substreams[SNDRV_PCM_STREAM_LAST + 1];
	53	+ unsigned int wait_time[SNDRV_PCM_STREAM_LAST + 1];
	54	+ unsigned int tx_lanes;
	55	+ unsigned int rx_lanes;
	56	+ unsigned int quirks;
44	57	enum fpw_mode fpw;
45		- int fw_ratio;
	58	+ int fw_ratio;
46	59	bool has_capture;
47	60	bool has_playback;
48	61	bool is_master_mode;
	62	+ bool is_tdm;
	63	+ bool is_clk_auto;
49	64	};
50	65
51		-static int sai_runtime_suspend(struct device *dev)
	66	+static const struct sai_of_quirks {
	67	+ char *quirk;
	68	+ int id;
	69	+} of_quirks[] = {
	70	+ {
	71	+ .quirk = "rockchip,always-on",
	72	+ .id = QUIRK_ALWAYS_ON,
	73	+ },
	74	+};
	75	+
	76	+static int rockchip_sai_runtime_suspend(struct device *dev)
52	77	{
53	78	struct rk_sai_dev *sai = dev_get_drvdata(dev);
54	79	unsigned int val;
..	..	@@ -62,20 +87,40 @@
62	87	SAI_XFER_FSS_DIS);
63	88
64	89	ret = regmap_read_poll_timeout_atomic(sai->regmap, SAI_XFER, val,
65		- (val & SAI_XFER_FS_IDLE), 10, 100);
	90	+ (val & SAI_XFER_FS_IDLE), 10, TIMEOUT_US);
66	91	if (ret < 0)
67	92	dev_warn(sai->dev, "Failed to idle FS\n");
68	93
69	94	regcache_cache_only(sai->regmap, true);
	95	+ /*
	96	+ * After FS idle, should wait at least 2 BCLK cycle to make sure
	97	+ * the CLK gate operation done, and then disable mclk.
	98	+ *
	99	+ * Otherwise, the BCLK is still ungated. once the mclk is enabled,
	100	+ * there maybe a risk that a few BCLK cycle leak. especially for
	101	+ * low speed situation, such as 8k samplerate.
	102	+ *
	103	+ * The best way is to use delay per samplerate, but, the max time
	104	+ * is quite a tiny value, so, let's make it simple to use the max
	105	+ * time.
	106	+ *
	107	+ * The max BCLK cycle time is: 31us @ 8K-8Bit (64K BCLK)
	108	+ */
	109	+ udelay(40);
70	110	clk_disable_unprepare(sai->mclk);
	111	+ clk_disable_unprepare(sai->hclk);
71	112
72	113	return 0;
73	114	}
74	115
75		-static int sai_runtime_resume(struct device *dev)
	116	+static int rockchip_sai_runtime_resume(struct device *dev)
76	117	{
77	118	struct rk_sai_dev *sai = dev_get_drvdata(dev);
78	119	int ret;
	120	+
	121	+ ret = clk_prepare_enable(sai->hclk);
	122	+ if (ret)
	123	+ goto err_hclk;
79	124
80	125	ret = clk_prepare_enable(sai->mclk);
81	126	if (ret)
..	..	@@ -87,7 +132,7 @@
87	132	if (ret)
88	133	goto err_regmap;
89	134
90		- if (sai->is_master_mode)
	135	+ if (sai->quirks & QUIRK_ALWAYS_ON && sai->is_master_mode)
91	136	regmap_update_bits(sai->regmap, SAI_XFER,
92	137	SAI_XFER_CLK_MASK \|
93	138	SAI_XFER_FSS_MASK,
..	..	@@ -99,6 +144,8 @@
99	144	err_regmap:
100	145	clk_disable_unprepare(sai->mclk);
101	146	err_mclk:
	147	+ clk_disable_unprepare(sai->hclk);
	148	+err_hclk:
102	149	return ret;
103	150	}
104	151
..	..	@@ -178,7 +225,7 @@
178	225
179	226	regmap_update_bits(sai->regmap, SAI_CLR, clr, clr);
180	227	ret = regmap_read_poll_timeout_atomic(sai->regmap, SAI_CLR, val,
181		- !(val & clr), 10, 100);
	228	+ !(val & clr), 10, TIMEOUT_US);
182	229	if (ret < 0) {
183	230	dev_warn(sai->dev, "Failed to clear %u\n", clr);
184	231	goto reset;
..	..	@@ -224,7 +271,7 @@
224	271
225	272	regmap_update_bits(sai->regmap, SAI_XFER, msk, val);
226	273	ret = regmap_read_poll_timeout_atomic(sai->regmap, SAI_XFER, val,
227		- (val & idle), 10, 100);
	274	+ (val & idle), 10, TIMEOUT_US);
228	275	if (ret < 0)
229	276	dev_warn(sai->dev, "Failed to idle stream %d\n", stream);
230	277
..	..	@@ -359,19 +406,46 @@
359	406	return ret;
360	407	}
361	408
	409	+static unsigned int rockchip_sai_lanes_auto(struct snd_pcm_hw_params *params,
	410	+ struct snd_soc_dai *dai)
	411	+{
	412	+ struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
	413	+ unsigned int lanes = 1;
	414	+
	415	+ if (!sai->is_tdm)
	416	+ lanes = DIV_ROUND_UP(params_channels(params), 2);
	417	+
	418	+ return lanes;
	419	+}
	420	+
362	421	static int rockchip_sai_hw_params(struct snd_pcm_substream *substream,
363	422	struct snd_pcm_hw_params *params,
364	423	struct snd_soc_dai *dai)
365	424	{
366	425	struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
367		- unsigned int mclk_rate, bclk_rate, div_bclk;
	426	+ struct snd_dmaengine_dai_dma_data *dma_data;
	427	+ unsigned int mclk_rate, mclk_req_rate, bclk_rate, div_bclk;
368	428	unsigned int ch_per_lane, lanes, slot_width;
369		- unsigned int val, fscr, reg;
	429	+ unsigned int val, fscr, reg, fifo;
370	430
371		- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	431	+ dma_data = snd_soc_dai_get_dma_data(dai, substream);
	432	+ dma_data->maxburst = MAXBURST_PER_FIFO * params_channels(params) / 2;
	433	+
	434	+ lanes = rockchip_sai_lanes_auto(params, dai);
	435	+
	436	+ regmap_read(sai->regmap, SAI_DMACR, &val);
	437	+
	438	+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
372	439	reg = SAI_TXCR;
373		- else
	440	+ if (sai->tx_lanes)
	441	+ lanes = sai->tx_lanes;
	442	+ fifo = SAI_DMACR_TDL_V(val) * lanes;
	443	+ } else {
374	444	reg = SAI_RXCR;
	445	+ if (sai->rx_lanes)
	446	+ lanes = sai->rx_lanes;
	447	+ fifo = SAI_DMACR_TDL_V(val) * lanes;
	448	+ }
375	449
376	450	switch (params_format(params)) {
377	451	case SNDRV_PCM_FORMAT_S8:
..	..	@@ -385,18 +459,20 @@
385	459	val = SAI_XCR_VDW(24);
386	460	break;
387	461	case SNDRV_PCM_FORMAT_S32_LE:
	462	+ case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
388	463	val = SAI_XCR_VDW(32);
389	464	break;
390	465	default:
391	466	return -EINVAL;
392	467	}
393	468
394		- regmap_update_bits(sai->regmap, reg, SAI_XCR_VDW_MASK, val);
	469	+ val \|= SAI_XCR_CSR(lanes);
	470	+
	471	+ regmap_update_bits(sai->regmap, reg, SAI_XCR_VDW_MASK \| SAI_XCR_CSR_MASK, val);
395	472
396	473	regmap_read(sai->regmap, reg, &val);
397	474
398	475	slot_width = SAI_XCR_SBW_V(val);
399		- lanes = SAI_XCR_CSR_V(val);
400	476	ch_per_lane = params_channels(params) / lanes;
401	477
402	478	regmap_update_bits(sai->regmap, reg, SAI_XCR_SNB_MASK,
..	..	@@ -424,17 +500,58 @@
424	500
425	501	if (sai->is_master_mode) {
426	502	bclk_rate = sai->fw_ratio * slot_width * ch_per_lane * params_rate(params);
	503	+ if (sai->is_clk_auto)
	504	+ clk_set_rate(sai->mclk, bclk_rate);
427	505	mclk_rate = clk_get_rate(sai->mclk);
428		- if (mclk_rate < bclk_rate) {
429		- dev_err(sai->dev, "Mismatch mclk: %u, expected %u at least\n",
430		- mclk_rate, bclk_rate);
	506	+ div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
	507	+ mclk_req_rate = bclk_rate * div_bclk;
	508	+
	509	+ if (mclk_rate < mclk_req_rate - CLK_SHIFT_RATE_HZ_MAX \|\|
	510	+ mclk_rate > mclk_req_rate + CLK_SHIFT_RATE_HZ_MAX) {
	511	+ dev_err(sai->dev, "Mismatch mclk: %u, expected %u (+/- %dHz)\n",
	512	+ mclk_rate, mclk_req_rate, CLK_SHIFT_RATE_HZ_MAX);
431	513	return -EINVAL;
432	514	}
433	515
434		- div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
435		-
436	516	regmap_update_bits(sai->regmap, SAI_CKR, SAI_CKR_MDIV_MASK,
437	517	SAI_CKR_MDIV(div_bclk));
	518	+ }
	519	+
	520	+ rockchip_utils_get_performance(substream, params, dai, fifo);
	521	+
	522	+ return 0;
	523	+}
	524	+
	525	+static int rockchip_sai_hw_free(struct snd_pcm_substream *substream,
	526	+ struct snd_soc_dai *dai)
	527	+{
	528	+ rockchip_utils_put_performance(substream, dai);
	529	+
	530	+ return 0;
	531	+}
	532	+
	533	+static int rockchip_sai_prepare(struct snd_pcm_substream *substream,
	534	+ struct snd_soc_dai *dai)
	535	+{
	536	+ struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
	537	+
	538	+ if (sai->is_master_mode) {
	539	+ /*
	540	+ * Should wait for one BCLK ready after DIV and then ungate
	541	+ * output clk to achieve the clean clk.
	542	+ *
	543	+ * The best way is to use delay per samplerate, but, the max time
	544	+ * is quite a tiny value, so, let's make it simple to use the max
	545	+ * time.
	546	+ *
	547	+ * The max BCLK cycle time is: 15.6us @ 8K-8Bit (64K BCLK)
	548	+ */
	549	+ udelay(20);
	550	+ regmap_update_bits(sai->regmap, SAI_XFER,
	551	+ SAI_XFER_CLK_MASK \|
	552	+ SAI_XFER_FSS_MASK,
	553	+ SAI_XFER_CLK_EN \|
	554	+ SAI_XFER_FSS_EN);
438	555	}
439	556
440	557	return 0;
..	..	@@ -471,7 +588,7 @@
471	588	struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
472	589	int ret;
473	590
474		- if (!freq)
	591	+ if (!freq \|\| sai->is_clk_auto)
475	592	return 0;
476	593
477	594	ret = clk_set_rate(sai->mclk, freq);
..	..	@@ -496,11 +613,15 @@
496	613	struct snd_soc_dai *dai)
497	614	{
498	615	struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
	616	+ int stream = substream->stream;
499	617
500		- if (sai->substreams[substream->stream])
	618	+ if (sai->substreams[stream])
501	619	return -EBUSY;
502	620
503		- sai->substreams[substream->stream] = substream;
	621	+ if (sai->wait_time[stream])
	622	+ substream->wait_time = msecs_to_jiffies(sai->wait_time[stream]);
	623	+
	624	+ sai->substreams[stream] = substream;
504	625
505	626	return 0;
506	627	}
..	..	@@ -526,6 +647,8 @@
526	647	SAI_XCR_SBW(slot_width));
527	648	pm_runtime_put(dai->dev);
528	649
	650	+ sai->is_tdm = true;
	651	+
529	652	return 0;
530	653	}
531	654
..	..	@@ -533,8 +656,10 @@
533	656	.startup = rockchip_sai_startup,
534	657	.shutdown = rockchip_sai_shutdown,
535	658	.hw_params = rockchip_sai_hw_params,
	659	+ .hw_free = rockchip_sai_hw_free,
536	660	.set_sysclk = rockchip_sai_set_sysclk,
537	661	.set_fmt = rockchip_sai_set_fmt,
	662	+ .prepare = rockchip_sai_prepare,
538	663	.trigger = rockchip_sai_trigger,
539	664	.set_tdm_slot = rockchip_sai_set_tdm_slot,
540	665	};
..	..	@@ -690,31 +815,33 @@
690	815	if (sai->has_playback) {
691	816	dai->playback.stream_name = "Playback";
692	817	dai->playback.channels_min = 1;
693		- dai->playback.channels_max = 128;
694		- dai->playback.rates = SNDRV_PCM_RATE_8000_192000;
	818	+ dai->playback.channels_max = 512;
	819	+ dai->playback.rates = SNDRV_PCM_RATE_8000_384000;
695	820	dai->playback.formats = SNDRV_PCM_FMTBIT_S8 \|
696	821	SNDRV_PCM_FMTBIT_S16_LE \|
697	822	SNDRV_PCM_FMTBIT_S24_LE \|
698		- SNDRV_PCM_FMTBIT_S32_LE;
	823	+ SNDRV_PCM_FMTBIT_S32_LE \|
	824	+ SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
699	825
700	826	sai->playback_dma_data.addr = res->start + SAI_TXDR;
701	827	sai->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
702		- sai->playback_dma_data.maxburst = 8;
	828	+ sai->playback_dma_data.maxburst = MAXBURST_PER_FIFO;
703	829	}
704	830
705	831	if (sai->has_capture) {
706	832	dai->capture.stream_name = "Capture";
707	833	dai->capture.channels_min = 1;
708		- dai->capture.channels_max = 128;
709		- dai->capture.rates = SNDRV_PCM_RATE_8000_192000;
	834	+ dai->capture.channels_max = 512;
	835	+ dai->capture.rates = SNDRV_PCM_RATE_8000_384000;
710	836	dai->capture.formats = SNDRV_PCM_FMTBIT_S8 \|
711	837	SNDRV_PCM_FMTBIT_S16_LE \|
712	838	SNDRV_PCM_FMTBIT_S24_LE \|
713		- SNDRV_PCM_FMTBIT_S32_LE;
	839	+ SNDRV_PCM_FMTBIT_S32_LE \|
	840	+ SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
714	841
715	842	sai->capture_dma_data.addr = res->start + SAI_RXDR;
716	843	sai->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
717		- sai->capture_dma_data.maxburst = 8;
	844	+ sai->capture_dma_data.maxburst = MAXBURST_PER_FIFO;
718	845	}
719	846
720	847	regmap_update_bits(sai->regmap, SAI_DMACR, SAI_DMACR_TDL_MASK,
..	..	@@ -728,8 +855,8 @@
728	855	return 0;
729	856	}
730	857
731		-static const char * const tcsr_text[] = { "SDOx1", "SDOx2", "SDOx3", "SDOx4" };
732		-static const char * const rcsr_text[] = { "SDIx1", "SDIx2", "SDIx3", "SDIx4" };
	858	+static const char * const tx_lanes_text[] = { "Auto", "SDOx1", "SDOx2", "SDOx3", "SDOx4" };
	859	+static const char * const rx_lanes_text[] = { "Auto", "SDIx1", "SDIx2", "SDIx3", "SDIx4" };
733	860	static const char * const edge_text[] = { "Rising Edge", "Dual Edge" };
734	861	static const char * const edge_shift_text[] = { "Normal", "Shift 1 Edge" };
735	862
..	..	@@ -743,8 +870,8 @@
743	870	static const char * const vdj_text[] = { "Right J", "Left J" };
744	871
745	872	static const char * const sbw_text[] = {
746		- " 0", " 0", " 0", " 0", " 0", " 0", " 0", " 8",
747		- " 9", "10", "11", "12", "13", "14", "15", "16",
	873	+ "0", "0", "0", "0", "0", "0", "0", "8",
	874	+ "9", "10", "11", "12", "13", "14", "15", "16",
748	875	"17", "18", "19", "20", "21", "22", "23", "24",
749	876	"25", "26", "27", "28", "29", "30", "31", "32", };
750	877
..	..	@@ -752,7 +879,7 @@
752	879
753	880	static DECLARE_TLV_DB_SCALE(rmss_tlv, 0, 128, 0);
754	881
755		-static const char * const mss_text[] = { "Master", "Slave" };
	882	+static const char * const mss_text[] = { "Slave", "Master" };
756	883
757	884	static const char * const ckp_text[] = { "Normal", "Inverted" };
758	885
..	..	@@ -760,46 +887,49 @@
760	887	"From SDO0", "From SDO1", "From SDO2", "From SDO3" };
761	888
762	889	static const char * const lps_text[] = { "Disable", "Enable" };
763		-static const char * const sync_out_text[] = { "External", "Internal" };
764		-static const char * const sync_in_text[] = { "External", "Internal" };
	890	+static const char * const sync_out_text[] = { "From CRU", "From IO" };
	891	+static const char * const sync_in_text[] = { "From IO", "From Sync Port" };
765	892
766	893	static const char * const rpaths_text[] = {
767	894	"From SDI0", "From SDI1", "From SDI2", "From SDI3" };
768	895
769	896	static const char * const tpaths_text[] = {
770		- "To SDO0", "To SDO1", "To SDO2", "To SDO3" };
	897	+ "From PATH0", "From PATH1", "From PATH2", "From PATH3" };
771	898
772	899	/* TXCR */
773		-static SOC_ENUM_SINGLE_DECL(tsft_enum, SAI_TXCR, 22, edge_shift_text);
774		-static SOC_ENUM_SINGLE_DECL(tcsr_enum, SAI_TXCR, 20, tcsr_text);
775		-static SOC_ENUM_SINGLE_DECL(tsjm_enum, SAI_TXCR, 19, sjm_text);
776		-static SOC_ENUM_SINGLE_DECL(tfbm_enum, SAI_TXCR, 18, fbm_text);
777		-static SOC_ENUM_SINGLE_DECL(tvdj_enum, SAI_TXCR, 10, vdj_text);
778		-static SOC_ENUM_SINGLE_DECL(tsbw_enum, SAI_TXCR, 5, sbw_text);
	900	+static SOC_ENUM_SINGLE_DECL(__maybe_unused tsft_enum, SAI_TXCR, 22, edge_shift_text);
	901	+static const struct soc_enum tx_lanes_enum =
	902	+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_lanes_text), tx_lanes_text);
	903	+static SOC_ENUM_SINGLE_DECL(__maybe_unused tsjm_enum, SAI_TXCR, 19, sjm_text);
	904	+static SOC_ENUM_SINGLE_DECL(__maybe_unused tfbm_enum, SAI_TXCR, 18, fbm_text);
	905	+static SOC_ENUM_SINGLE_DECL(__maybe_unused tvdj_enum, SAI_TXCR, 10, vdj_text);
	906	+static SOC_ENUM_SINGLE_DECL(__maybe_unused tsbw_enum, SAI_TXCR, 5, sbw_text);
779	907
780	908	/* FSCR */
781		-static SOC_ENUM_SINGLE_DECL(edge_enum, SAI_FSCR, 24, edge_text);
782		-static const struct soc_enum fpw_enum =
	909	+static SOC_ENUM_SINGLE_DECL(__maybe_unused edge_enum, SAI_FSCR, 24, edge_text);
	910	+static const struct soc_enum __maybe_unused fpw_enum =
783	911	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fpw_text), fpw_text);
784		-static const struct soc_enum fw_ratio_enum =
	912	+static const struct soc_enum __maybe_unused fw_ratio_enum =
785	913	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fw_ratio_text), fw_ratio_text);
786	914
787	915	/* RXCR */
788		-static SOC_ENUM_SINGLE_DECL(rsft_enum, SAI_RXCR, 22, edge_shift_text);
789		-static SOC_ENUM_SINGLE_DECL(rcsr_enum, SAI_RXCR, 20, rcsr_text);
790		-static SOC_ENUM_SINGLE_DECL(rsjm_enum, SAI_RXCR, 19, sjm_text);
791		-static SOC_ENUM_SINGLE_DECL(rfbm_enum, SAI_RXCR, 18, fbm_text);
792		-static SOC_ENUM_SINGLE_DECL(rvdj_enum, SAI_RXCR, 10, vdj_text);
793		-static SOC_ENUM_SINGLE_DECL(rsbw_enum, SAI_RXCR, 5, sbw_text);
	916	+static SOC_ENUM_SINGLE_DECL(__maybe_unused rsft_enum, SAI_RXCR, 22, edge_shift_text);
	917	+static const struct soc_enum rx_lanes_enum =
	918	+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_lanes_text), rx_lanes_text);
	919	+static SOC_ENUM_SINGLE_DECL(__maybe_unused rsjm_enum, SAI_RXCR, 19, sjm_text);
	920	+static SOC_ENUM_SINGLE_DECL(__maybe_unused rfbm_enum, SAI_RXCR, 18, fbm_text);
	921	+static SOC_ENUM_SINGLE_DECL(__maybe_unused rvdj_enum, SAI_RXCR, 10, vdj_text);
	922	+static SOC_ENUM_SINGLE_DECL(__maybe_unused rsbw_enum, SAI_RXCR, 5, sbw_text);
794	923
795	924	/* MONO_CR */
796	925	static SOC_ENUM_SINGLE_DECL(rmono_switch, SAI_MONO_CR, 1, mono_text);
797	926	static SOC_ENUM_SINGLE_DECL(tmono_switch, SAI_MONO_CR, 0, mono_text);
798	927
799	928	/* CKR */
800		-static SOC_ENUM_SINGLE_DECL(mss_switch, SAI_CKR, 2, mss_text);
801		-static SOC_ENUM_SINGLE_DECL(sp_switch, SAI_CKR, 1, ckp_text);
802		-static SOC_ENUM_SINGLE_DECL(fp_switch, SAI_CKR, 0, ckp_text);
	929	+static const struct soc_enum __maybe_unused mss_switch =
	930	+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mss_text), mss_text);
	931	+static SOC_ENUM_SINGLE_DECL(__maybe_unused sp_switch, SAI_CKR, 1, ckp_text);
	932	+static SOC_ENUM_SINGLE_DECL(__maybe_unused fp_switch, SAI_CKR, 0, ckp_text);
803	933
804	934	/* PATH_SEL */
805	935	static SOC_ENUM_SINGLE_DECL(lp3_enum, SAI_PATH_SEL, 28, lpx_text);
..	..	@@ -821,8 +951,8 @@
821	951	static SOC_ENUM_SINGLE_DECL(tpath1_enum, SAI_PATH_SEL, 2, tpaths_text);
822	952	static SOC_ENUM_SINGLE_DECL(tpath0_enum, SAI_PATH_SEL, 0, tpaths_text);
823	953
824		-static int rockchip_sai_fpw_get(struct snd_kcontrol *kcontrol,
825		- struct snd_ctl_elem_value *ucontrol)
	954	+static int __maybe_unused rockchip_sai_fpw_get(struct snd_kcontrol *kcontrol,
	955	+ struct snd_ctl_elem_value *ucontrol)
826	956	{
827	957	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
828	958	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
..	..	@@ -832,8 +962,8 @@
832	962	return 0;
833	963	}
834	964
835		-static int rockchip_sai_fpw_put(struct snd_kcontrol *kcontrol,
836		- struct snd_ctl_elem_value *ucontrol)
	965	+static int __maybe_unused rockchip_sai_fpw_put(struct snd_kcontrol *kcontrol,
	966	+ struct snd_ctl_elem_value *ucontrol)
837	967	{
838	968	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
839	969	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
..	..	@@ -848,8 +978,8 @@
848	978	return 1;
849	979	}
850	980
851		-static int rockchip_sai_fw_ratio_get(struct snd_kcontrol *kcontrol,
852		- struct snd_ctl_elem_value *ucontrol)
	981	+static int __maybe_unused rockchip_sai_fw_ratio_get(struct snd_kcontrol *kcontrol,
	982	+ struct snd_ctl_elem_value *ucontrol)
853	983	{
854	984	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
855	985	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
..	..	@@ -859,8 +989,8 @@
859	989	return 0;
860	990	}
861	991
862		-static int rockchip_sai_fw_ratio_put(struct snd_kcontrol *kcontrol,
863		- struct snd_ctl_elem_value *ucontrol)
	992	+static int __maybe_unused rockchip_sai_fw_ratio_put(struct snd_kcontrol *kcontrol,
	993	+ struct snd_ctl_elem_value *ucontrol)
864	994	{
865	995	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
866	996	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
..	..	@@ -874,19 +1004,219 @@
874	1004	return 1;
875	1005	}
876	1006
877		-static DECLARE_TLV_DB_SCALE(fs_shift_tlv, 0, 8192, 0);
	1007	+static int rockchip_sai_tx_lanes_get(struct snd_kcontrol *kcontrol,
	1008	+ struct snd_ctl_elem_value *ucontrol)
	1009	+{
	1010	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1011	+ struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
	1012	+
	1013	+ ucontrol->value.enumerated.item[0] = sai->tx_lanes;
	1014	+
	1015	+ return 0;
	1016	+}
	1017	+
	1018	+static int rockchip_sai_tx_lanes_put(struct snd_kcontrol *kcontrol,
	1019	+ struct snd_ctl_elem_value *ucontrol)
	1020	+{
	1021	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1022	+ struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
	1023	+ int num;
	1024	+
	1025	+ num = ucontrol->value.enumerated.item[0];
	1026	+ if (num >= ARRAY_SIZE(tx_lanes_text))
	1027	+ return -EINVAL;
	1028	+
	1029	+ sai->tx_lanes = num;
	1030	+
	1031	+ return 1;
	1032	+}
	1033	+
	1034	+static int rockchip_sai_rx_lanes_get(struct snd_kcontrol *kcontrol,
	1035	+ struct snd_ctl_elem_value *ucontrol)
	1036	+{
	1037	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1038	+ struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
	1039	+
	1040	+ ucontrol->value.enumerated.item[0] = sai->rx_lanes;
	1041	+
	1042	+ return 0;
	1043	+}
	1044	+
	1045	+static int rockchip_sai_rx_lanes_put(struct snd_kcontrol *kcontrol,
	1046	+ struct snd_ctl_elem_value *ucontrol)
	1047	+{
	1048	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1049	+ struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
	1050	+ int num;
	1051	+
	1052	+ num = ucontrol->value.enumerated.item[0];
	1053	+ if (num >= ARRAY_SIZE(rx_lanes_text))
	1054	+ return -EINVAL;
	1055	+
	1056	+ sai->rx_lanes = num;
	1057	+
	1058	+ return 1;
	1059	+}
	1060	+
	1061	+static int __maybe_unused rockchip_sai_mss_get(struct snd_kcontrol *kcontrol,
	1062	+ struct snd_ctl_elem_value *ucontrol)
	1063	+{
	1064	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1065	+ struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
	1066	+
	1067	+ ucontrol->value.enumerated.item[0] = sai->is_master_mode;
	1068	+
	1069	+ return 0;
	1070	+}
	1071	+
	1072	+static int __maybe_unused rockchip_sai_mss_put(struct snd_kcontrol *kcontrol,
	1073	+ struct snd_ctl_elem_value *ucontrol)
	1074	+{
	1075	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1076	+ struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
	1077	+ bool mss;
	1078	+
	1079	+ /* MUST: do not update mode while stream is running */
	1080	+ if (snd_soc_component_active(component))
	1081	+ return -EPERM;
	1082	+
	1083	+ mss = !!ucontrol->value.enumerated.item[0];
	1084	+ if (mss == sai->is_master_mode)
	1085	+ return 0;
	1086	+
	1087	+ sai->is_master_mode = mss;
	1088	+
	1089	+ pm_runtime_get_sync(sai->dev);
	1090	+ if (sai->is_master_mode) {
	1091	+ /* Switch from Slave to Master */
	1092	+ regmap_update_bits(sai->regmap, SAI_CKR,
	1093	+ SAI_CKR_MSS_MASK,
	1094	+ SAI_CKR_MSS_MASTER);
	1095	+ regmap_update_bits(sai->regmap, SAI_XFER,
	1096	+ SAI_XFER_CLK_MASK \|
	1097	+ SAI_XFER_FSS_MASK,
	1098	+ SAI_XFER_CLK_EN \|
	1099	+ SAI_XFER_FSS_EN);
	1100	+ } else {
	1101	+ /* Switch from Master to Slave */
	1102	+ regmap_update_bits(sai->regmap, SAI_CKR,
	1103	+ SAI_CKR_MSS_MASK,
	1104	+ SAI_CKR_MSS_SLAVE);
	1105	+ regmap_update_bits(sai->regmap, SAI_XFER,
	1106	+ SAI_XFER_CLK_MASK \|
	1107	+ SAI_XFER_FSS_MASK,
	1108	+ SAI_XFER_CLK_DIS \|
	1109	+ SAI_XFER_FSS_DIS);
	1110	+ }
	1111	+ pm_runtime_put(sai->dev);
	1112	+
	1113	+ return 1;
	1114	+}
	1115	+
	1116	+static int rockchip_sai_clk_auto_get(struct snd_kcontrol *kcontrol,
	1117	+ struct snd_ctl_elem_value *ucontrol)
	1118	+{
	1119	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1120	+ struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
	1121	+
	1122	+ ucontrol->value.integer.value[0] = sai->is_clk_auto;
	1123	+
	1124	+ return 0;
	1125	+}
	1126	+
	1127	+static int rockchip_sai_clk_auto_put(struct snd_kcontrol *kcontrol,
	1128	+ struct snd_ctl_elem_value *ucontrol)
	1129	+{
	1130	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1131	+ struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
	1132	+ bool clk_auto = ucontrol->value.integer.value[0];
	1133	+
	1134	+ if (clk_auto == sai->is_clk_auto)
	1135	+ return 0;
	1136	+
	1137	+ sai->is_clk_auto = clk_auto;
	1138	+
	1139	+ return 1;
	1140	+}
	1141	+
	1142	+static int rockchip_sai_wait_time_info(struct snd_kcontrol *kcontrol,
	1143	+ struct snd_ctl_elem_info *uinfo)
	1144	+{
	1145	+ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
	1146	+ uinfo->count = 1;
	1147	+ uinfo->value.integer.min = 0;
	1148	+ uinfo->value.integer.max = WAIT_TIME_MS_MAX;
	1149	+ uinfo->value.integer.step = 1;
	1150	+
	1151	+ return 0;
	1152	+}
	1153	+
	1154	+static int rockchip_sai_rd_wait_time_get(struct snd_kcontrol *kcontrol,
	1155	+ struct snd_ctl_elem_value *ucontrol)
	1156	+{
	1157	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1158	+ struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
	1159	+
	1160	+ ucontrol->value.integer.value[0] = sai->wait_time[SNDRV_PCM_STREAM_CAPTURE];
	1161	+
	1162	+ return 0;
	1163	+}
	1164	+
	1165	+static int rockchip_sai_rd_wait_time_put(struct snd_kcontrol *kcontrol,
	1166	+ struct snd_ctl_elem_value *ucontrol)
	1167	+{
	1168	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1169	+ struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
	1170	+
	1171	+ if (ucontrol->value.integer.value[0] > WAIT_TIME_MS_MAX)
	1172	+ return -EINVAL;
	1173	+
	1174	+ sai->wait_time[SNDRV_PCM_STREAM_CAPTURE] = ucontrol->value.integer.value[0];
	1175	+
	1176	+ return 1;
	1177	+}
	1178	+
	1179	+static int rockchip_sai_wr_wait_time_get(struct snd_kcontrol *kcontrol,
	1180	+ struct snd_ctl_elem_value *ucontrol)
	1181	+{
	1182	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1183	+ struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
	1184	+
	1185	+ ucontrol->value.integer.value[0] = sai->wait_time[SNDRV_PCM_STREAM_PLAYBACK];
	1186	+
	1187	+ return 0;
	1188	+}
	1189	+
	1190	+static int rockchip_sai_wr_wait_time_put(struct snd_kcontrol *kcontrol,
	1191	+ struct snd_ctl_elem_value *ucontrol)
	1192	+{
	1193	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1194	+ struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
	1195	+
	1196	+ if (ucontrol->value.integer.value[0] > WAIT_TIME_MS_MAX)
	1197	+ return -EINVAL;
	1198	+
	1199	+ sai->wait_time[SNDRV_PCM_STREAM_PLAYBACK] = ucontrol->value.integer.value[0];
	1200	+
	1201	+ return 1;
	1202	+}
	1203	+
	1204	+#define SAI_PCM_WAIT_TIME(xname, xhandler_get, xhandler_put) \
	1205	+{ .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname, \
	1206	+ .info = rockchip_sai_wait_time_info, \
	1207	+ .get = xhandler_get, .put = xhandler_put }
	1208	+
	1209	+static __maybe_unused DECLARE_TLV_DB_SCALE(fs_shift_tlv, 0, 8192, 0);
878	1210
879	1211	static const struct snd_kcontrol_new rockchip_sai_controls[] = {
880		-
	1212	+#ifdef CONFIG_SND_SOC_ROCKCHIP_SAI_VERBOSE
881	1213	SOC_ENUM("Transmit Edge Shift", tsft_enum),
882		- SOC_ENUM("Transmit SDOx Select", tcsr_enum),
883	1214	SOC_ENUM("Transmit Store Justified Mode", tsjm_enum),
884	1215	SOC_ENUM("Transmit First Bit Mode", tfbm_enum),
885	1216	SOC_ENUM("Transmit Valid Data Justified", tvdj_enum),
886	1217	SOC_ENUM("Transmit Slot Bit Width", tsbw_enum),
887	1218
888	1219	SOC_ENUM("Receive Edge Shift", rsft_enum),
889		- SOC_ENUM("Receive SDIx Select", rcsr_enum),
890	1220	SOC_ENUM("Receive Store Justified Mode", rsjm_enum),
891	1221	SOC_ENUM("Receive First Bit Mode", rfbm_enum),
892	1222	SOC_ENUM("Receive Valid Data Justified", rvdj_enum),
..	..	@@ -898,14 +1228,24 @@
898	1228	SOC_ENUM_EXT("Frame Width Ratio", fw_ratio_enum,
899	1229	rockchip_sai_fw_ratio_get, rockchip_sai_fw_ratio_put),
900	1230
	1231	+ SOC_ENUM_EXT("Master Slave Mode Select", mss_switch,
	1232	+ rockchip_sai_mss_get, rockchip_sai_mss_put),
	1233	+ SOC_ENUM("Sclk Polarity", sp_switch),
	1234	+ SOC_ENUM("Frame Sync Polarity", fp_switch),
	1235	+
	1236	+ SOC_SINGLE_TLV("Transmit Frame Shift Select", SAI_TX_SHIFT,
	1237	+ 0, 8192, 0, fs_shift_tlv),
	1238	+ SOC_SINGLE_TLV("Receive Frame Shift Select", SAI_RX_SHIFT,
	1239	+ 0, 8192, 0, fs_shift_tlv),
	1240	+#endif
	1241	+ SOC_ENUM_EXT("Transmit SDOx Select", tx_lanes_enum,
	1242	+ rockchip_sai_tx_lanes_get, rockchip_sai_tx_lanes_put),
	1243	+ SOC_ENUM_EXT("Receive SDIx Select", rx_lanes_enum,
	1244	+ rockchip_sai_rx_lanes_get, rockchip_sai_rx_lanes_put),
901	1245	SOC_SINGLE_TLV("Receive Mono Slot Select", SAI_MONO_CR,
902	1246	2, 128, 0, rmss_tlv),
903	1247	SOC_ENUM("Receive Mono Switch", rmono_switch),
904	1248	SOC_ENUM("Transmit Mono Switch", tmono_switch),
905		-
906		- SOC_ENUM("Master / Slave Mode Select", mss_switch),
907		- SOC_ENUM("Sclk Polarity", sp_switch),
908		- SOC_ENUM("Frame Sync Polarity", fp_switch),
909	1249
910	1250	SOC_ENUM("SDI3 Loopback Src Select", lp3_enum),
911	1251	SOC_ENUM("SDI2 Loopback Src Select", lp2_enum),
..	..	@@ -921,15 +1261,21 @@
921	1261	SOC_ENUM("Receive PATH2 Source Select", rpath2_enum),
922	1262	SOC_ENUM("Receive PATH1 Source Select", rpath1_enum),
923	1263	SOC_ENUM("Receive PATH0 Source Select", rpath0_enum),
924		- SOC_ENUM("Transmit PATH3 Sink Select", tpath3_enum),
925		- SOC_ENUM("Transmit PATH2 Sink Select", tpath2_enum),
926		- SOC_ENUM("Transmit PATH1 Sink Select", tpath1_enum),
927		- SOC_ENUM("Transmit PATH0 Sink Select", tpath0_enum),
	1264	+ SOC_ENUM("Transmit SDO3 Source Select", tpath3_enum),
	1265	+ SOC_ENUM("Transmit SDO2 Source Select", tpath2_enum),
	1266	+ SOC_ENUM("Transmit SDO1 Source Select", tpath1_enum),
	1267	+ SOC_ENUM("Transmit SDO0 Source Select", tpath0_enum),
928	1268
929		- SOC_SINGLE_TLV("Transmit Frame Shift Select", SAI_TX_SHIFT,
930		- 0, 8192, 0, fs_shift_tlv),
931		- SOC_SINGLE_TLV("Receive Frame Shift Select", SAI_RX_SHIFT,
932		- 0, 8192, 0, fs_shift_tlv),
	1269	+ SOC_SINGLE_BOOL_EXT("Clk Auto Switch", 0,
	1270	+ rockchip_sai_clk_auto_get,
	1271	+ rockchip_sai_clk_auto_put),
	1272	+
	1273	+ SAI_PCM_WAIT_TIME("PCM Read Wait Time MS",
	1274	+ rockchip_sai_rd_wait_time_get,
	1275	+ rockchip_sai_rd_wait_time_put),
	1276	+ SAI_PCM_WAIT_TIME("PCM Write Wait Time MS",
	1277	+ rockchip_sai_wr_wait_time_get,
	1278	+ rockchip_sai_wr_wait_time_put),
933	1279	};
934	1280
935	1281	static const struct snd_soc_component_driver rockchip_sai_component = {
..	..	@@ -949,6 +1295,9 @@
949	1295	dev_warn_ratelimited(sai->dev, "TX FIFO Underrun\n");
950	1296	regmap_update_bits(sai->regmap, SAI_INTCR,
951	1297	SAI_INTCR_TXUIC, SAI_INTCR_TXUIC);
	1298	+ regmap_update_bits(sai->regmap, SAI_INTCR,
	1299	+ SAI_INTCR_TXUIE_MASK,
	1300	+ SAI_INTCR_TXUIE(0));
952	1301	substream = sai->substreams[SNDRV_PCM_STREAM_PLAYBACK];
953	1302	if (substream)
954	1303	snd_pcm_stop_xrun(substream);
..	..	@@ -958,6 +1307,9 @@
958	1307	dev_warn_ratelimited(sai->dev, "RX FIFO Overrun\n");
959	1308	regmap_update_bits(sai->regmap, SAI_INTCR,
960	1309	SAI_INTCR_RXOIC, SAI_INTCR_RXOIC);
	1310	+ regmap_update_bits(sai->regmap, SAI_INTCR,
	1311	+ SAI_INTCR_RXOIE_MASK,
	1312	+ SAI_INTCR_RXOIE(0));
961	1313	substream = sai->substreams[SNDRV_PCM_STREAM_CAPTURE];
962	1314	if (substream)
963	1315	snd_pcm_stop_xrun(substream);
..	..	@@ -965,6 +1317,73 @@
965	1317
966	1318	return IRQ_HANDLED;
967	1319	}
	1320	+
	1321	+static int rockchip_sai_keep_clk_always_on(struct rk_sai_dev *sai)
	1322	+{
	1323	+ unsigned int mclk_rate, bclk_rate, div_bclk;
	1324	+
	1325	+ sai->is_master_mode = true;
	1326	+
	1327	+ /* init I2S fmt default */
	1328	+ rockchip_sai_fmt_create(sai, SND_SOC_DAIFMT_I2S);
	1329	+
	1330	+ regmap_update_bits(sai->regmap, SAI_FSCR,
	1331	+ SAI_FSCR_FW_MASK \|
	1332	+ SAI_FSCR_FPW_MASK,
	1333	+ SAI_FSCR_FW(64) \|
	1334	+ SAI_FSCR_FPW(32));
	1335	+
	1336	+ mclk_rate = clk_get_rate(sai->mclk);
	1337	+ bclk_rate = DEFAULT_FS * 64;
	1338	+ div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
	1339	+
	1340	+ regmap_update_bits(sai->regmap, SAI_CKR, SAI_CKR_MDIV_MASK,
	1341	+ SAI_CKR_MDIV(div_bclk));
	1342	+
	1343	+ pm_runtime_forbid(sai->dev);
	1344	+
	1345	+ dev_info(sai->dev, "CLK-ALWAYS-ON: mclk: %d, bclk: %d, fsync: %d\n",
	1346	+ mclk_rate, bclk_rate, DEFAULT_FS);
	1347	+
	1348	+ return 0;
	1349	+}
	1350	+
	1351	+static int rockchip_sai_parse_quirks(struct rk_sai_dev *sai)
	1352	+{
	1353	+ int ret = 0, i = 0;
	1354	+
	1355	+ for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
	1356	+ if (device_property_read_bool(sai->dev, of_quirks[i].quirk))
	1357	+ sai->quirks \|= of_quirks[i].id;
	1358	+
	1359	+ if (sai->quirks & QUIRK_ALWAYS_ON)
	1360	+ ret = rockchip_sai_keep_clk_always_on(sai);
	1361	+
	1362	+ return ret;
	1363	+}
	1364	+
	1365	+static int rockchip_sai_get_fifo_count(struct device *dev,
	1366	+ struct snd_pcm_substream *substream)
	1367	+{
	1368	+ struct rk_sai_dev *sai = dev_get_drvdata(dev);
	1369	+ int val = 0;
	1370	+
	1371	+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	1372	+ regmap_read(sai->regmap, SAI_TXFIFOLR, &val);
	1373	+ else
	1374	+ regmap_read(sai->regmap, SAI_RXFIFOLR, &val);
	1375	+
	1376	+ val = ((val & SAI_FIFOLR_XFL3_MASK) >> SAI_FIFOLR_XFL3_SHIFT) +
	1377	+ ((val & SAI_FIFOLR_XFL2_MASK) >> SAI_FIFOLR_XFL2_SHIFT) +
	1378	+ ((val & SAI_FIFOLR_XFL1_MASK) >> SAI_FIFOLR_XFL1_SHIFT) +
	1379	+ ((val & SAI_FIFOLR_XFL0_MASK) >> SAI_FIFOLR_XFL0_SHIFT);
	1380	+
	1381	+ return val;
	1382	+}
	1383	+
	1384	+static const struct snd_dlp_config dconfig = {
	1385	+ .get_fifo_count = rockchip_sai_get_fifo_count,
	1386	+};
968	1387
969	1388	static int rockchip_sai_probe(struct platform_device *pdev)
970	1389	{
..	..	@@ -981,6 +1400,8 @@
981	1400
982	1401	sai->dev = &pdev->dev;
983	1402	sai->fw_ratio = 1;
	1403	+ /* match to register default */
	1404	+ sai->is_master_mode = true;
984	1405	dev_set_drvdata(&pdev->dev, sai);
985	1406
986	1407	sai->rst_h = devm_reset_control_get_optional_exclusive(&pdev->dev, "h");
..	..	@@ -1000,7 +1421,7 @@
1000	1421	if (IS_ERR(sai->regmap))
1001	1422	return PTR_ERR(sai->regmap);
1002	1423
1003		- irq = platform_get_irq(pdev, 0);
	1424	+ irq = platform_get_irq_optional(pdev, 0);
1004	1425	if (irq > 0) {
1005	1426	ret = devm_request_irq(&pdev->dev, irq, rockchip_sai_isr,
1006	1427	IRQF_SHARED, node->name, sai);
..	..	@@ -1022,20 +1443,30 @@
1022	1443	return PTR_ERR(sai->hclk);
1023	1444	}
1024	1445
1025		- ret = clk_prepare_enable(sai->hclk);
	1446	+ ret = rockchip_sai_parse_quirks(sai);
1026	1447	if (ret)
1027	1448	return ret;
1028	1449
	1450	+ ret = rockchip_sai_init_dai(sai, res, &dai);
	1451	+ if (ret)
	1452	+ return ret;
	1453	+
	1454	+ /*
	1455	+ * MUST: after pm_runtime_enable step, any register R/W
	1456	+ * should be wrapped with pm_runtime_get_sync/put.
	1457	+ *
	1458	+ * Another approach is to enable the regcache true to
	1459	+ * avoid access HW registers.
	1460	+ *
	1461	+ * Alternatively, performing the registers R/W before
	1462	+ * pm_runtime_enable is also a good option.
	1463	+ */
1029	1464	pm_runtime_enable(&pdev->dev);
1030	1465	if (!pm_runtime_enabled(&pdev->dev)) {
1031		- ret = sai_runtime_resume(&pdev->dev);
	1466	+ ret = rockchip_sai_runtime_resume(&pdev->dev);
1032	1467	if (ret)
1033	1468	goto err_runtime_disable;
1034	1469	}
1035		-
1036		- ret = rockchip_sai_init_dai(sai, res, &dai);
1037		- if (ret)
1038		- goto err_runtime_suspend;
1039	1470
1040	1471	ret = devm_snd_soc_register_component(&pdev->dev,
1041	1472	&rockchip_sai_component,
..	..	@@ -1043,7 +1474,16 @@
1043	1474	if (ret)
1044	1475	goto err_runtime_suspend;
1045	1476
1046		- ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
	1477	+ if (device_property_read_bool(&pdev->dev, "rockchip,no-dmaengine")) {
	1478	+ dev_info(&pdev->dev, "Used for Multi-DAI\n");
	1479	+ return 0;
	1480	+ }
	1481	+
	1482	+ if (device_property_read_bool(&pdev->dev, "rockchip,digital-loopback"))
	1483	+ ret = devm_snd_dmaengine_dlp_register(&pdev->dev, &dconfig);
	1484	+ else
	1485	+ ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
	1486	+
1047	1487	if (ret)
1048	1488	goto err_runtime_suspend;
1049	1489
..	..	@@ -1051,29 +1491,25 @@
1051	1491
1052	1492	err_runtime_suspend:
1053	1493	if (!pm_runtime_status_suspended(&pdev->dev))
1054		- sai_runtime_suspend(&pdev->dev);
	1494	+ rockchip_sai_runtime_suspend(&pdev->dev);
1055	1495	err_runtime_disable:
1056	1496	pm_runtime_disable(&pdev->dev);
1057		- clk_disable_unprepare(sai->hclk);
1058	1497
1059	1498	return ret;
1060	1499	}
1061	1500
1062	1501	static int rockchip_sai_remove(struct platform_device *pdev)
1063	1502	{
1064		- struct rk_sai_dev *sai = dev_get_drvdata(&pdev->dev);
1065		-
1066	1503	pm_runtime_disable(&pdev->dev);
1067	1504	if (!pm_runtime_status_suspended(&pdev->dev))
1068		- sai_runtime_suspend(&pdev->dev);
1069		-
1070		- clk_disable_unprepare(sai->hclk);
	1505	+ rockchip_sai_runtime_suspend(&pdev->dev);
1071	1506
1072	1507	return 0;
1073	1508	}
1074	1509
1075	1510	static const struct dev_pm_ops rockchip_sai_pm_ops = {
1076		- SET_RUNTIME_PM_OPS(sai_runtime_suspend, sai_runtime_resume, NULL)
	1511	+ SET_RUNTIME_PM_OPS(rockchip_sai_runtime_suspend, rockchip_sai_runtime_resume, NULL)
	1512	+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1077	1513	};
1078	1514
1079	1515	static struct platform_driver rockchip_sai_driver = {