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1 | 1 | // SPDX-License-Identifier: GPL-2.0 |
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2 | | -/** |
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| 2 | +/* |
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3 | 3 | * ulpi.c - DesignWare USB3 Controller's ULPI PHY interface |
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4 | 4 | * |
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5 | 5 | * Copyright (C) 2015 Intel Corporation |
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.. | .. |
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24 | 24 | static int dwc3_ulpi_busyloop(struct dwc3 *dwc, u8 addr, bool read) |
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25 | 25 | { |
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26 | 26 | unsigned long ns = 5L * DWC3_ULPI_BASE_DELAY; |
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27 | | - unsigned int count = 1000; |
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| 27 | + unsigned int count = 10000; |
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28 | 28 | u32 reg; |
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29 | 29 | |
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30 | 30 | if (addr >= ULPI_EXT_VENDOR_SPECIFIC) |
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.. | .. |
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32 | 32 | |
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33 | 33 | if (read) |
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34 | 34 | ns += DWC3_ULPI_BASE_DELAY; |
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| 35 | + |
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| 36 | + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); |
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| 37 | + if (reg & DWC3_GUSB2PHYCFG_SUSPHY) |
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| 38 | + usleep_range(1000, 1200); |
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35 | 39 | |
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36 | 40 | while (count--) { |
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37 | 41 | ndelay(ns); |
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.. | .. |
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50 | 54 | u32 reg; |
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51 | 55 | int ret; |
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52 | 56 | |
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53 | | - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); |
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54 | | - if (reg & DWC3_GUSB2PHYCFG_SUSPHY) { |
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55 | | - reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; |
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56 | | - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); |
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57 | | - } |
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58 | | - |
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59 | 57 | reg = DWC3_GUSB2PHYACC_NEWREGREQ | DWC3_ULPI_ADDR(addr); |
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60 | 58 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg); |
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61 | 59 | |
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.. | .. |
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72 | 70 | { |
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73 | 71 | struct dwc3 *dwc = dev_get_drvdata(dev); |
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74 | 72 | u32 reg; |
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75 | | - |
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76 | | - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); |
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77 | | - if (reg & DWC3_GUSB2PHYCFG_SUSPHY) { |
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78 | | - reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; |
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79 | | - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); |
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80 | | - } |
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81 | 73 | |
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82 | 74 | reg = DWC3_GUSB2PHYACC_NEWREGREQ | DWC3_ULPI_ADDR(addr); |
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83 | 75 | reg |= DWC3_GUSB2PHYACC_WRITE | val; |
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