.. | .. |
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13 | 13 | #include <linux/usb/hcd.h> |
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14 | 14 | #include <linux/usb/chipidea.h> |
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15 | 15 | #include <linux/regulator/consumer.h> |
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| 16 | +#include <linux/pinctrl/consumer.h> |
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16 | 17 | |
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17 | 18 | #include "../host/ehci.h" |
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18 | 19 | |
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.. | .. |
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155 | 156 | } |
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156 | 157 | } |
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157 | 158 | |
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| 159 | + if (ci->platdata->pins_host) |
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| 160 | + pinctrl_select_state(ci->platdata->pctl, |
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| 161 | + ci->platdata->pins_host); |
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| 162 | + |
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158 | 163 | ret = usb_add_hcd(hcd, 0, 0); |
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159 | 164 | if (ret) { |
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160 | 165 | goto disable_reg; |
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.. | .. |
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167 | 172 | otg->host = &hcd->self; |
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168 | 173 | hcd->self.otg_port = 1; |
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169 | 174 | } |
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| 175 | + |
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| 176 | + if (ci->platdata->notify_event && |
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| 177 | + (ci->platdata->flags & CI_HDRC_IMX_IS_HSIC)) |
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| 178 | + ci->platdata->notify_event |
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| 179 | + (ci, CI_HDRC_IMX_HSIC_ACTIVE_EVENT); |
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170 | 180 | } |
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171 | 181 | |
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172 | 182 | return ret; |
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.. | .. |
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199 | 209 | } |
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200 | 210 | ci->hcd = NULL; |
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201 | 211 | ci->otg.host = NULL; |
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| 212 | + |
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| 213 | + if (ci->platdata->pins_host && ci->platdata->pins_default) |
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| 214 | + pinctrl_select_state(ci->platdata->pctl, |
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| 215 | + ci->platdata->pins_default); |
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202 | 216 | } |
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203 | 217 | |
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204 | 218 | |
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.. | .. |
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208 | 222 | host_stop(ci); |
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209 | 223 | } |
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210 | 224 | |
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| 225 | +/* The below code is based on tegra ehci driver */ |
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| 226 | +static int ci_ehci_hub_control( |
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| 227 | + struct usb_hcd *hcd, |
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| 228 | + u16 typeReq, |
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| 229 | + u16 wValue, |
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| 230 | + u16 wIndex, |
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| 231 | + char *buf, |
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| 232 | + u16 wLength |
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| 233 | +) |
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| 234 | +{ |
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| 235 | + struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
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| 236 | + unsigned int ports = HCS_N_PORTS(ehci->hcs_params); |
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| 237 | + u32 __iomem *status_reg; |
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| 238 | + u32 temp, port_index; |
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| 239 | + unsigned long flags; |
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| 240 | + int retval = 0; |
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| 241 | + struct device *dev = hcd->self.controller; |
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| 242 | + struct ci_hdrc *ci = dev_get_drvdata(dev); |
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| 243 | + |
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| 244 | + port_index = wIndex & 0xff; |
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| 245 | + port_index -= (port_index > 0); |
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| 246 | + status_reg = &ehci->regs->port_status[port_index]; |
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| 247 | + |
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| 248 | + spin_lock_irqsave(&ehci->lock, flags); |
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| 249 | + |
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| 250 | + if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) { |
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| 251 | + if (!wIndex || wIndex > ports) { |
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| 252 | + retval = -EPIPE; |
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| 253 | + goto done; |
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| 254 | + } |
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| 255 | + |
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| 256 | + temp = ehci_readl(ehci, status_reg); |
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| 257 | + if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) { |
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| 258 | + retval = -EPIPE; |
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| 259 | + goto done; |
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| 260 | + } |
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| 261 | + |
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| 262 | + temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E); |
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| 263 | + temp |= PORT_WKDISC_E | PORT_WKOC_E; |
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| 264 | + ehci_writel(ehci, temp | PORT_SUSPEND, status_reg); |
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| 265 | + |
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| 266 | + /* |
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| 267 | + * If a transaction is in progress, there may be a delay in |
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| 268 | + * suspending the port. Poll until the port is suspended. |
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| 269 | + */ |
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| 270 | + if (ehci_handshake(ehci, status_reg, PORT_SUSPEND, |
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| 271 | + PORT_SUSPEND, 5000)) |
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| 272 | + ehci_err(ehci, "timeout waiting for SUSPEND\n"); |
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| 273 | + |
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| 274 | + if (ci->platdata->flags & CI_HDRC_IMX_IS_HSIC) { |
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| 275 | + if (ci->platdata->notify_event) |
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| 276 | + ci->platdata->notify_event(ci, |
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| 277 | + CI_HDRC_IMX_HSIC_SUSPEND_EVENT); |
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| 278 | + |
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| 279 | + temp = ehci_readl(ehci, status_reg); |
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| 280 | + temp &= ~(PORT_WKDISC_E | PORT_WKCONN_E); |
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| 281 | + ehci_writel(ehci, temp, status_reg); |
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| 282 | + } |
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| 283 | + |
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| 284 | + set_bit(port_index, &ehci->suspended_ports); |
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| 285 | + goto done; |
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| 286 | + } |
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| 287 | + |
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| 288 | + /* |
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| 289 | + * After resume has finished, it needs do some post resume |
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| 290 | + * operation for some SoCs. |
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| 291 | + */ |
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| 292 | + else if (typeReq == ClearPortFeature && |
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| 293 | + wValue == USB_PORT_FEAT_C_SUSPEND) { |
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| 294 | + /* Make sure the resume has finished, it should be finished */ |
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| 295 | + if (ehci_handshake(ehci, status_reg, PORT_RESUME, 0, 25000)) |
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| 296 | + ehci_err(ehci, "timeout waiting for resume\n"); |
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| 297 | + } |
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| 298 | + |
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| 299 | + spin_unlock_irqrestore(&ehci->lock, flags); |
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| 300 | + |
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| 301 | + /* Handle the hub control events here */ |
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| 302 | + return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength); |
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| 303 | +done: |
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| 304 | + spin_unlock_irqrestore(&ehci->lock, flags); |
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| 305 | + return retval; |
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| 306 | +} |
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211 | 307 | static int ci_ehci_bus_suspend(struct usb_hcd *hcd) |
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212 | 308 | { |
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213 | 309 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
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| 310 | + struct device *dev = hcd->self.controller; |
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| 311 | + struct ci_hdrc *ci = dev_get_drvdata(dev); |
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214 | 312 | int port; |
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215 | 313 | u32 tmp; |
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216 | 314 | |
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.. | .. |
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242 | 340 | * It needs a short delay between set RS bit and PHCD. |
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243 | 341 | */ |
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244 | 342 | usleep_range(150, 200); |
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| 343 | + /* |
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| 344 | + * Need to clear WKCN and WKOC for imx HSIC, |
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| 345 | + * otherwise, there will be wakeup event. |
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| 346 | + */ |
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| 347 | + if (ci->platdata->flags & CI_HDRC_IMX_IS_HSIC) { |
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| 348 | + tmp = ehci_readl(ehci, reg); |
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| 349 | + tmp &= ~(PORT_WKDISC_E | PORT_WKCONN_E); |
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| 350 | + ehci_writel(ehci, tmp, reg); |
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| 351 | + } |
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| 352 | + |
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245 | 353 | break; |
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246 | 354 | } |
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247 | 355 | } |
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.. | .. |
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274 | 382 | ehci_init_driver(&ci_ehci_hc_driver, &ehci_ci_overrides); |
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275 | 383 | orig_bus_suspend = ci_ehci_hc_driver.bus_suspend; |
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276 | 384 | ci_ehci_hc_driver.bus_suspend = ci_ehci_bus_suspend; |
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| 385 | + ci_ehci_hc_driver.hub_control = ci_ehci_hub_control; |
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277 | 386 | } |
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