| .. | .. |
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| 125 | 125 | u32 tx_fifo_width; |
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| 126 | 126 | u32 rx_fifo_depth; |
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| 127 | 127 | bool setup; |
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| 128 | + unsigned long clk_rate; |
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| 128 | 129 | int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop); |
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| 129 | 130 | unsigned int baud; |
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| 130 | 131 | void *rx_fifo; |
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| .. | .. |
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| 866 | 867 | return IRQ_HANDLED; |
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| 867 | 868 | } |
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| 868 | 869 | |
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| 869 | | -static void get_tx_fifo_size(struct qcom_geni_serial_port *port) |
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| 870 | +static int setup_fifos(struct qcom_geni_serial_port *port) |
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| 870 | 871 | { |
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| 871 | 872 | struct uart_port *uport; |
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| 873 | + u32 old_rx_fifo_depth = port->rx_fifo_depth; |
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| 872 | 874 | |
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| 873 | 875 | uport = &port->uport; |
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| 874 | 876 | port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se); |
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| .. | .. |
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| 876 | 878 | port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se); |
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| 877 | 879 | uport->fifosize = |
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| 878 | 880 | (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE; |
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| 881 | + |
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| 882 | + if (port->rx_fifo && (old_rx_fifo_depth != port->rx_fifo_depth) && port->rx_fifo_depth) { |
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| 883 | + port->rx_fifo = devm_krealloc(uport->dev, port->rx_fifo, |
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| 884 | + port->rx_fifo_depth * sizeof(u32), |
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| 885 | + GFP_KERNEL); |
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| 886 | + if (!port->rx_fifo) |
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| 887 | + return -ENOMEM; |
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| 888 | + } |
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| 889 | + |
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| 890 | + return 0; |
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| 879 | 891 | } |
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| 880 | 892 | |
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| 881 | 893 | |
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| .. | .. |
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| 890 | 902 | u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT; |
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| 891 | 903 | u32 proto; |
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| 892 | 904 | u32 pin_swap; |
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| 905 | + int ret; |
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| 893 | 906 | |
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| 894 | 907 | proto = geni_se_read_proto(&port->se); |
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| 895 | 908 | if (proto != GENI_SE_UART) { |
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| .. | .. |
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| 899 | 912 | |
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| 900 | 913 | qcom_geni_serial_stop_rx(uport); |
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| 901 | 914 | |
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| 902 | | - get_tx_fifo_size(port); |
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| 915 | + ret = setup_fifos(port); |
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| 916 | + if (ret) |
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| 917 | + return ret; |
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| 903 | 918 | |
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| 904 | 919 | writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT); |
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| 905 | 920 | |
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| .. | .. |
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| 1008 | 1023 | goto out_restart_rx; |
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| 1009 | 1024 | |
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| 1010 | 1025 | uport->uartclk = clk_rate; |
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| 1026 | + port->clk_rate = clk_rate; |
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| 1011 | 1027 | dev_pm_opp_set_rate(uport->dev, clk_rate); |
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| 1012 | 1028 | ser_clk_cfg = SER_CLK_EN; |
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| 1013 | 1029 | ser_clk_cfg |= clk_div << CLK_DIV_SHFT; |
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| .. | .. |
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| 1291 | 1307 | |
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| 1292 | 1308 | if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) { |
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| 1293 | 1309 | geni_icc_enable(&port->se); |
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| 1310 | + if (port->clk_rate) |
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| 1311 | + dev_pm_opp_set_rate(uport->dev, port->clk_rate); |
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| 1294 | 1312 | geni_se_resources_on(&port->se); |
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| 1295 | 1313 | } else if (new_state == UART_PM_STATE_OFF && |
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| 1296 | 1314 | old_state == UART_PM_STATE_ON) { |
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| 1297 | 1315 | geni_se_resources_off(&port->se); |
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| 1316 | + dev_pm_opp_set_rate(uport->dev, 0); |
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| 1298 | 1317 | geni_icc_disable(&port->se); |
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| 1299 | 1318 | } |
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| 1300 | 1319 | } |
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| .. | .. |
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| 1453 | 1472 | uart_remove_one_port(drv, uport); |
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| 1454 | 1473 | goto err; |
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| 1455 | 1474 | } |
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| 1456 | | - |
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| 1457 | | - /* |
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| 1458 | | - * Set pm_runtime status as ACTIVE so that wakeup_irq gets |
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| 1459 | | - * enabled/disabled from dev_pm_arm_wake_irq during system |
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| 1460 | | - * suspend/resume respectively. |
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| 1461 | | - */ |
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| 1462 | | - pm_runtime_set_active(&pdev->dev); |
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| 1463 | 1475 | |
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| 1464 | 1476 | if (port->wakeup_irq > 0) { |
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| 1465 | 1477 | device_init_wakeup(&pdev->dev, true); |
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