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2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/tty/serial/max310x.c
....@@ -248,6 +248,7 @@
248248 struct max310x_devtype {
249249 	char	name[9];
250250 	int	nr;
251
+	u8	mode1;
251252 	int	(*detect)(struct device *);
252253 	void	(*power)(struct uart_port *, int);
253254 };
....@@ -257,12 +258,17 @@
257258 	struct work_struct	tx_work;
258259 	struct work_struct	md_work;
259260 	struct work_struct	rs_work;
261
+
262
+	u8 wr_header;
263
+	u8 rd_header;
264
+	u8 rx_buf[MAX310X_FIFO_SIZE];
260265 };
266
+#define to_max310x_port(_port) \
267
+	container_of(_port, struct max310x_one, port)
261268 
262269 struct max310x_port {
263270 	struct max310x_devtype	*devtype;
264271 	struct regmap		*regmap;
265
-	struct mutex		mutex;
266272 	struct clk		*clk;
267273 #ifdef CONFIG_GPIOLIB
268274 	struct gpio_chip	gpio;
....@@ -410,6 +416,7 @@
410416 static const struct max310x_devtype max3107_devtype = {
411417 	.name	= "MAX3107",
412418 	.nr	= 1,
419
+	.mode1	= MAX310X_MODE1_AUTOSLEEP_BIT | MAX310X_MODE1_IRQSEL_BIT,
413420 	.detect	= max3107_detect,
414421 	.power	= max310x_power,
415422 };
....@@ -417,6 +424,7 @@
417424 static const struct max310x_devtype max3108_devtype = {
418425 	.name	= "MAX3108",
419426 	.nr	= 1,
427
+	.mode1	= MAX310X_MODE1_AUTOSLEEP_BIT,
420428 	.detect	= max3108_detect,
421429 	.power	= max310x_power,
422430 };
....@@ -424,6 +432,7 @@
424432 static const struct max310x_devtype max3109_devtype = {
425433 	.name	= "MAX3109",
426434 	.nr	= 2,
435
+	.mode1	= MAX310X_MODE1_AUTOSLEEP_BIT,
427436 	.detect	= max3109_detect,
428437 	.power	= max310x_power,
429438 };
....@@ -431,6 +440,7 @@
431440 static const struct max310x_devtype max14830_devtype = {
432441 	.name	= "MAX14830",
433442 	.nr	= 4,
443
+	.mode1	= MAX310X_MODE1_IRQSEL_BIT,
434444 	.detect	= max14830_detect,
435445 	.power	= max14830_power,
436446 };
....@@ -613,11 +623,11 @@
613623 
614624 static void max310x_batch_write(struct uart_port *port, u8 *txbuf, unsigned int len)
615625 {
616
-	u8 header[] = { (port->iobase + MAX310X_THR_REG) | MAX310X_WRITE_BIT };
626
+	struct max310x_one *one = to_max310x_port(port);
617627 	struct spi_transfer xfer[] = {
618628 		{
619
-			.tx_buf = &header,
620
-			.len = sizeof(header),
629
+			.tx_buf = &one->wr_header,
630
+			.len = sizeof(one->wr_header),
621631 		}, {
622632 			.tx_buf = txbuf,
623633 			.len = len,
....@@ -628,11 +638,11 @@
628638 
629639 static void max310x_batch_read(struct uart_port *port, u8 *rxbuf, unsigned int len)
630640 {
631
-	u8 header[] = { port->iobase + MAX310X_RHR_REG };
641
+	struct max310x_one *one = to_max310x_port(port);
632642 	struct spi_transfer xfer[] = {
633643 		{
634
-			.tx_buf = &header,
635
-			.len = sizeof(header),
644
+			.tx_buf = &one->rd_header,
645
+			.len = sizeof(one->rd_header),
636646 		}, {
637647 			.rx_buf = rxbuf,
638648 			.len = len,
....@@ -643,8 +653,8 @@
643653 
644654 static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen)
645655 {
656
+	struct max310x_one *one = to_max310x_port(port);
646657 	unsigned int sts, ch, flag, i;
647
-	u8 buf[MAX310X_FIFO_SIZE];
648658 
649659 	if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) {
650660 		/* We are just reading, happily ignoring any error conditions.
....@@ -659,7 +669,7 @@
659669 		 * */
660670 
661671 		sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
662
-		max310x_batch_read(port, buf, rxlen);
672
+		max310x_batch_read(port, one->rx_buf, rxlen);
663673 
664674 		port->icount.rx += rxlen;
665675 		flag = TTY_NORMAL;
....@@ -670,9 +680,16 @@
670680 			port->icount.overrun++;
671681 		}
672682 
673
-		for (i = 0; i < rxlen; ++i) {
674
-			uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, buf[i], flag);
675
-		}
683
+		for (i = 0; i < (rxlen - 1); ++i)
684
+			uart_insert_char(port, sts, 0, one->rx_buf[i], flag);
685
+
686
+		/*
687
+		 * Handle the overrun case for the last character only, since
688
+		 * the RxFIFO overflow happens after it is pushed to the FIFO
689
+		 * tail.
690
+		 */
691
+		uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT,
692
+				 one->rx_buf[rxlen-1], flag);
676693 
677694 	} else {
678695 		if (unlikely(rxlen >= port->fifosize)) {
....@@ -772,10 +789,9 @@
772789 
773790 static void max310x_start_tx(struct uart_port *port)
774791 {
775
-	struct max310x_one *one = container_of(port, struct max310x_one, port);
792
+	struct max310x_one *one = to_max310x_port(port);
776793 
777
-	if (!work_pending(&one->tx_work))
778
-		schedule_work(&one->tx_work);
794
+	schedule_work(&one->tx_work);
779795 }
780796 
781797 static irqreturn_t max310x_port_irq(struct max310x_port *s, int portno)
....@@ -832,14 +848,11 @@
832848 	return IRQ_RETVAL(handled);
833849 }
834850 
835
-static void max310x_wq_proc(struct work_struct *ws)
851
+static void max310x_tx_proc(struct work_struct *ws)
836852 {
837853 	struct max310x_one *one = container_of(ws, struct max310x_one, tx_work);
838
-	struct max310x_port *s = dev_get_drvdata(one->port.dev);
839854 
840
-	mutex_lock(&s->mutex);
841855 	max310x_handle_tx(&one->port);
842
-	mutex_unlock(&s->mutex);
843856 }
844857 
845858 static unsigned int max310x_tx_empty(struct uart_port *port)
....@@ -869,7 +882,7 @@
869882 
870883 static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl)
871884 {
872
-	struct max310x_one *one = container_of(port, struct max310x_one, port);
885
+	struct max310x_one *one = to_max310x_port(port);
873886 
874887 	schedule_work(&one->md_work);
875888 }
....@@ -942,16 +955,42 @@
942955 	/* Configure flow control */
943956 	max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]);
944957 	max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]);
945
-	if (termios->c_cflag & CRTSCTS)
958
+
959
+	/* Disable transmitter before enabling AutoCTS or auto transmitter
960
+	 * flow control
961
+	 */
962
+	if (termios->c_cflag & CRTSCTS || termios->c_iflag & IXOFF) {
963
+		max310x_port_update(port, MAX310X_MODE1_REG,
964
+				    MAX310X_MODE1_TXDIS_BIT,
965
+				    MAX310X_MODE1_TXDIS_BIT);
966
+	}
967
+
968
+	port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
969
+
970
+	if (termios->c_cflag & CRTSCTS) {
971
+		/* Enable AUTORTS and AUTOCTS */
972
+		port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
946973 		flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT |
947974 			MAX310X_FLOWCTRL_AUTORTS_BIT;
975
+	}
948976 	if (termios->c_iflag & IXON)
949977 		flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT |
950978 			MAX310X_FLOWCTRL_SWFLOWEN_BIT;
951
-	if (termios->c_iflag & IXOFF)
979
+	if (termios->c_iflag & IXOFF) {
980
+		port->status |= UPSTAT_AUTOXOFF;
952981 		flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT |
953982 			MAX310X_FLOWCTRL_SWFLOWEN_BIT;
983
+	}
954984 	max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow);
985
+
986
+	/* Enable transmitter after disabling AutoCTS and auto transmitter
987
+	 * flow control
988
+	 */
989
+	if (!(termios->c_cflag & CRTSCTS) && !(termios->c_iflag & IXOFF)) {
990
+		max310x_port_update(port, MAX310X_MODE1_REG,
991
+				    MAX310X_MODE1_TXDIS_BIT,
992
+				    0);
993
+	}
955994 
956995 	/* Get baud rate generator configuration */
957996 	baud = uart_get_baud_rate(port, termios, old,
....@@ -968,37 +1007,36 @@
9681007 static void max310x_rs_proc(struct work_struct *ws)
9691008 {
9701009 	struct max310x_one *one = container_of(ws, struct max310x_one, rs_work);
971
-	unsigned int val;
1010
+	unsigned int delay, mode1 = 0, mode2 = 0;
9721011 
973
-	val = (one->port.rs485.delay_rts_before_send << 4) |
1012
+	delay = (one->port.rs485.delay_rts_before_send << 4) |
9741013 		one->port.rs485.delay_rts_after_send;
975
-	max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, val);
1014
+	max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, delay);
9761015 
9771016 	if (one->port.rs485.flags & SER_RS485_ENABLED) {
978
-		max310x_port_update(&one->port, MAX310X_MODE1_REG,
979
-				MAX310X_MODE1_TRNSCVCTRL_BIT,
980
-				MAX310X_MODE1_TRNSCVCTRL_BIT);
981
-		max310x_port_update(&one->port, MAX310X_MODE2_REG,
982
-				MAX310X_MODE2_ECHOSUPR_BIT,
983
-				MAX310X_MODE2_ECHOSUPR_BIT);
984
-	} else {
985
-		max310x_port_update(&one->port, MAX310X_MODE1_REG,
986
-				MAX310X_MODE1_TRNSCVCTRL_BIT, 0);
987
-		max310x_port_update(&one->port, MAX310X_MODE2_REG,
988
-				MAX310X_MODE2_ECHOSUPR_BIT, 0);
1017
+		mode1 = MAX310X_MODE1_TRNSCVCTRL_BIT;
1018
+
1019
+		if (!(one->port.rs485.flags & SER_RS485_RX_DURING_TX))
1020
+			mode2 = MAX310X_MODE2_ECHOSUPR_BIT;
9891021 	}
1022
+
1023
+	max310x_port_update(&one->port, MAX310X_MODE1_REG,
1024
+			MAX310X_MODE1_TRNSCVCTRL_BIT, mode1);
1025
+	max310x_port_update(&one->port, MAX310X_MODE2_REG,
1026
+			MAX310X_MODE2_ECHOSUPR_BIT, mode2);
9901027 }
9911028 
9921029 static int max310x_rs485_config(struct uart_port *port,
9931030 				struct serial_rs485 *rs485)
9941031 {
995
-	struct max310x_one *one = container_of(port, struct max310x_one, port);
1032
+	struct max310x_one *one = to_max310x_port(port);
9961033 
9971034 	if ((rs485->delay_rts_before_send > 0x0f) ||
9981035 	    (rs485->delay_rts_after_send > 0x0f))
9991036 		return -ERANGE;
10001037 
1001
-	rs485->flags &= SER_RS485_RTS_ON_SEND | SER_RS485_ENABLED;
1038
+	rs485->flags &= SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX |
1039
+			SER_RS485_ENABLED;
10021040 	memset(rs485->padding, 0, sizeof(rs485->padding));
10031041 	port->rs485 = *rs485;
10041042 
....@@ -1023,6 +1061,22 @@
10231061 	max310x_port_write(port, MAX310X_MODE2_REG, val);
10241062 	max310x_port_update(port, MAX310X_MODE2_REG,
10251063 			    MAX310X_MODE2_FIFORST_BIT, 0);
1064
+
1065
+	/* Configure mode1/mode2 to have rs485/rs232 enabled at startup */
1066
+	val = (clamp(port->rs485.delay_rts_before_send, 0U, 15U) << 4) |
1067
+		clamp(port->rs485.delay_rts_after_send, 0U, 15U);
1068
+	max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val);
1069
+
1070
+	if (port->rs485.flags & SER_RS485_ENABLED) {
1071
+		max310x_port_update(port, MAX310X_MODE1_REG,
1072
+				    MAX310X_MODE1_TRNSCVCTRL_BIT,
1073
+				    MAX310X_MODE1_TRNSCVCTRL_BIT);
1074
+
1075
+		if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
1076
+			max310x_port_update(port, MAX310X_MODE2_REG,
1077
+					    MAX310X_MODE2_ECHOSUPR_BIT,
1078
+					    MAX310X_MODE2_ECHOSUPR_BIT);
1079
+	}
10261080 
10271081 	/* Configure flow control levels */
10281082 	/* Flow control halt level 96, resume level 48 */
....@@ -1208,8 +1262,7 @@
12081262 		return PTR_ERR(regmap);
12091263 
12101264 	/* Alloc port structure */
1211
-	s = devm_kzalloc(dev, sizeof(*s) +
1212
-			 sizeof(struct max310x_one) * devtype->nr, GFP_KERNEL);
1265
+	s = devm_kzalloc(dev, struct_size(s, p, devtype->nr), GFP_KERNEL);
12131266 	if (!s) {
12141267 		dev_err(dev, "Error allocating port structure\n");
12151268 		return -ENOMEM;
....@@ -1269,15 +1322,12 @@
12691322 				    MAX310X_BRGDIVLSB_REG + offs, &ret);
12701323 		} while (ret != 0x01);
12711324 
1272
-		regmap_update_bits(s->regmap, MAX310X_MODE1_REG + offs,
1273
-				   MAX310X_MODE1_AUTOSLEEP_BIT,
1274
-				   MAX310X_MODE1_AUTOSLEEP_BIT);
1325
+		regmap_write(s->regmap, MAX310X_MODE1_REG + offs,
1326
+			     devtype->mode1);
12751327 	}
12761328 
12771329 	uartclk = max310x_set_ref_clk(dev, s, freq, xtal);
12781330 	dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk);
1279
-
1280
-	mutex_init(&s->mutex);
12811331 
12821332 	for (i = 0; i < devtype->nr; i++) {
12831333 		unsigned int line;
....@@ -1305,16 +1355,16 @@
13051355 		max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0);
13061356 		/* Clear IRQ status register */
13071357 		max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG);
1308
-		/* Enable IRQ pin */
1309
-		max310x_port_update(&s->p[i].port, MAX310X_MODE1_REG,
1310
-				    MAX310X_MODE1_IRQSEL_BIT,
1311
-				    MAX310X_MODE1_IRQSEL_BIT);
13121358 		/* Initialize queue for start TX */
1313
-		INIT_WORK(&s->p[i].tx_work, max310x_wq_proc);
1359
+		INIT_WORK(&s->p[i].tx_work, max310x_tx_proc);
13141360 		/* Initialize queue for changing LOOPBACK mode */
13151361 		INIT_WORK(&s->p[i].md_work, max310x_md_proc);
13161362 		/* Initialize queue for changing RS485 mode */
13171363 		INIT_WORK(&s->p[i].rs_work, max310x_rs_proc);
1364
+		/* Initialize SPI-transfer buffers */
1365
+		s->p[i].wr_header = (s->p[i].port.iobase + MAX310X_THR_REG) |
1366
+				    MAX310X_WRITE_BIT;
1367
+		s->p[i].rd_header = (s->p[i].port.iobase + MAX310X_RHR_REG);
13181368 
13191369 		/* Register port */
13201370 		ret = uart_add_one_port(&max310x_uart, &s->p[i].port);
....@@ -1362,8 +1412,6 @@
13621412 		}
13631413 	}
13641414 
1365
-	mutex_destroy(&s->mutex);
1366
-
13671415 out_clk:
13681416 	clk_disable_unprepare(s->clk);
13691417 
....@@ -1384,7 +1432,6 @@
13841432 		s->devtype->power(&s->p[i].port, 0);
13851433 	}
13861434 
1387
-	mutex_destroy(&s->mutex);
13881435 	clk_disable_unprepare(s->clk);
13891436 
13901437 	return 0;