disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/tty/serial/8250/8250_fintek.c
..
..
@@ -19,6 +19,7 @@
19
19
 #define CHIP_ID2  0x21
20
20
 #define CHIP_ID_F81865 0x0407
21
21
 #define CHIP_ID_F81866 0x1010
22
+#define CHIP_ID_F81966 0x0215
22
23
 #define CHIP_ID_F81216AD 0x1602
23
24
 #define CHIP_ID_F81216H 0x0501
24
25
 #define CHIP_ID_F81216 0x0802
..
..
@@ -62,9 +63,9 @@
62
63
 #define F81216_LDN_HIGH	0x4
63
64
 
64
65
 /*
65
- * F81866 registers
66
+ * F81866/966 registers
66
67
  *
67
- * The IRQ setting mode of F81866 is not the same with F81216 series.
68
+ * The IRQ setting mode of F81866/966 is not the same with F81216 series.
68
69
  *	Level/Low: IRQ_MODE0:0, IRQ_MODE1:0
69
70
  *	Edge/High: IRQ_MODE0:1, IRQ_MODE1:0
70
71
  *
..
..
@@ -155,6 +156,7 @@
155
156
 	switch (chip) {
156
157
 	case CHIP_ID_F81865:
157
158
 	case CHIP_ID_F81866:
159
+	case CHIP_ID_F81966:
158
160
 	case CHIP_ID_F81216AD:
159
161
 	case CHIP_ID_F81216H:
160
162
 	case CHIP_ID_F81216:
..
..
@@ -171,6 +173,7 @@
171
173
 				     int *max)
172
174
 {
173
175
 	switch (pdata->pid) {
176
+	case CHIP_ID_F81966:
174
177
 	case CHIP_ID_F81865:
175
178
 	case CHIP_ID_F81866:
176
179
 		*min = F81866_LDN_LOW;
..
..
@@ -197,12 +200,12 @@
197
200
 	if (!pdata)
198
201
 		return -EINVAL;
199
202
 
200
-	/* Hardware do not support same RTS level on send and receive */
201
-	if (!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
202
-			!(rs485->flags & SER_RS485_RTS_AFTER_SEND))
203
-		return -EINVAL;
204
203
 
205
204
 	if (rs485->flags & SER_RS485_ENABLED) {
205
+		/* Hardware do not support same RTS level on send and receive */
206
+		if (!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
207
+		    !(rs485->flags & SER_RS485_RTS_AFTER_SEND))
208
+			return -EINVAL;
206
209
 		memset(rs485->padding, 0, sizeof(rs485->padding));
207
210
 		config |= RS485_URA;
208
211
 	} else {
..
..
@@ -248,10 +251,11 @@
248
251
 	sio_write_reg(pdata, LDN, pdata->index);
249
252
 
250
253
 	switch (pdata->pid) {
254
+	case CHIP_ID_F81966:
251
255
 	case CHIP_ID_F81866:
252
256
 		sio_write_mask_reg(pdata, F81866_FIFO_CTRL, F81866_IRQ_MODE1,
253
257
 				   0);
254
-		/* fall through */
258
+		fallthrough;
255
259
 	case CHIP_ID_F81865:
256
260
 		sio_write_mask_reg(pdata, F81866_IRQ_MODE, F81866_IRQ_SHARE,
257
261
 				   F81866_IRQ_SHARE);
..
..
@@ -274,6 +278,7 @@
274
278
 {
275
279
 	switch (pdata->pid) {
276
280
 	case CHIP_ID_F81216H: /* 128Bytes FIFO */
281
+	case CHIP_ID_F81966:
277
282
 	case CHIP_ID_F81866:
278
283
 		sio_write_mask_reg(pdata, FIFO_CTRL,
279
284
 				   FIFO_MODE_MASK | RXFTHR_MODE_MASK,
..
..
@@ -285,26 +290,9 @@
285
290
 	}
286
291
 }
287
292
 
288
-static void fintek_8250_goto_highspeed(struct uart_8250_port *uart,
289
-			      struct fintek_8250 *pdata)
290
-{
291
-	sio_write_reg(pdata, LDN, pdata->index);
292
-
293
-	switch (pdata->pid) {
294
-	case CHIP_ID_F81866: /* set uart clock for high speed serial mode */
295
-		sio_write_mask_reg(pdata, F81866_UART_CLK,
296
-			F81866_UART_CLK_MASK,
297
-			F81866_UART_CLK_14_769MHZ);
298
-
299
-		uart->port.uartclk = 921600 * 16;
300
-		break;
301
-	default: /* leave clock speed untouched */
302
-		break;
303
-	}
304
-}
305
-
306
-void fintek_8250_set_termios(struct uart_port *port, struct ktermios *termios,
307
-			struct ktermios *old)
293
+static void fintek_8250_set_termios(struct uart_port *port,
294
+				    struct ktermios *termios,
295
+				    struct ktermios *old)
308
296
 {
309
297
 	struct fintek_8250 *pdata = port->private_data;
310
298
 	unsigned int baud = tty_termios_baud_rate(termios);
..
..
@@ -326,6 +314,7 @@
326
314
 	case CHIP_ID_F81216H:
327
315
 		reg = RS485;
328
316
 		break;
317
+	case CHIP_ID_F81966:
329
318
 	case CHIP_ID_F81866:
330
319
 		reg = F81866_UART_CLK;
331
320
 		break;
..
..
@@ -372,6 +361,7 @@
372
361
 
373
362
 	switch (pdata->pid) {
374
363
 	case CHIP_ID_F81216H:
364
+	case CHIP_ID_F81966:
375
365
 	case CHIP_ID_F81866:
376
366
 		uart->port.set_termios = fintek_8250_set_termios;
377
367
 		break;
..
..
@@ -421,7 +411,6 @@
421
411
 
422
412
 				fintek_8250_set_irq_mode(pdata, level_mode);
423
413
 				fintek_8250_set_max_fifo(pdata);
424
-				fintek_8250_goto_highspeed(uart, pdata);
425
414
 
426
415
 				fintek_8250_exit_key(addr[i]);
427
416
 
..
..
@@ -442,6 +431,7 @@
442
431
 	switch (pdata->pid) {
443
432
 	case CHIP_ID_F81216AD:
444
433
 	case CHIP_ID_F81216H:
434
+	case CHIP_ID_F81966:
445
435
 	case CHIP_ID_F81866:
446
436
 	case CHIP_ID_F81865:
447
437
 		uart->port.rs485_config = fintek_8250_rs485_config;