disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/staging/rtl8188eu/hal/rf.c
..
..
@@ -49,9 +49,9 @@
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 		tx_agc[RF_PATH_B] = 0x3f3f3f3f;
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 		for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
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 			tx_agc[idx1] = powerlevel[idx1] |
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-				      (powerlevel[idx1]<<8) |
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-				      (powerlevel[idx1]<<16) |
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-				      (powerlevel[idx1]<<24);
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+				      (powerlevel[idx1] << 8) |
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+				      (powerlevel[idx1] << 16) |
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+				      (powerlevel[idx1] << 24);
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 		}
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 	} else {
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 		if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) {
..
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@@ -63,23 +63,23 @@
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 		} else {
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 			for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
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 				tx_agc[idx1] = powerlevel[idx1] |
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-					       (powerlevel[idx1]<<8) |
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-					       (powerlevel[idx1]<<16) |
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-					       (powerlevel[idx1]<<24);
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+					       (powerlevel[idx1] << 8) |
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+					       (powerlevel[idx1] << 16) |
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+					       (powerlevel[idx1] << 24);
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 			}
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 			if (hal_data->EEPROMRegulatory == 0) {
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 				tmpval = hal_data->MCSTxPowerLevelOriginalOffset[0][6] +
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-					 (hal_data->MCSTxPowerLevelOriginalOffset[0][7]<<8);
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+					 (hal_data->MCSTxPowerLevelOriginalOffset[0][7] << 8);
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 				tx_agc[RF_PATH_A] += tmpval;
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 				tmpval = hal_data->MCSTxPowerLevelOriginalOffset[0][14] +
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-					 (hal_data->MCSTxPowerLevelOriginalOffset[0][15]<<24);
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+					 (hal_data->MCSTxPowerLevelOriginalOffset[0][15] << 24);
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 				tx_agc[RF_PATH_B] += tmpval;
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 			}
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 		}
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 	}
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 	for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
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-		ptr = (u8 *)(&(tx_agc[idx1]));
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+		ptr = (u8 *)(&tx_agc[idx1]);
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 		for (idx2 = 0; idx2 < 4; idx2++) {
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 			if (*ptr > RF6052_MAX_TX_PWR)
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 				*ptr = RF6052_MAX_TX_PWR;
..
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@@ -100,15 +100,15 @@
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 	}
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 	/*  rf-A cck tx power */
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-	tmpval = tx_agc[RF_PATH_A]&0xff;
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+	tmpval = tx_agc[RF_PATH_A] & 0xff;
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 	phy_set_bb_reg(adapt, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval);
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-	tmpval = tx_agc[RF_PATH_A]>>8;
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+	tmpval = tx_agc[RF_PATH_A] >> 8;
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 	phy_set_bb_reg(adapt, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
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 	/*  rf-B cck tx power */
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-	tmpval = tx_agc[RF_PATH_B]>>24;
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+	tmpval = tx_agc[RF_PATH_B] >> 24;
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 	phy_set_bb_reg(adapt, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval);
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-	tmpval = tx_agc[RF_PATH_B]&0x00ffffff;
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+	tmpval = tx_agc[RF_PATH_B] & 0x00ffffff;
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 	phy_set_bb_reg(adapt, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
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 }
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..
..
@@ -124,9 +124,9 @@
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 	for (i = 0; i < 2; i++) {
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 		powerbase0 = pwr_level_ofdm[i];
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-		powerbase0 = (powerbase0<<24) | (powerbase0<<16) |
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-			     (powerbase0<<8) | powerbase0;
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-		*(ofdmbase+i) = powerbase0;
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+		powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) |
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+			     (powerbase0 << 8) | powerbase0;
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+		*(ofdmbase + i) = powerbase0;
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 	}
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 	/* Check HT20 to HT40 diff */
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 	if (adapt->HalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
..
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@@ -134,10 +134,11 @@
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 	else
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 		powerlevel[0] = pwr_level_bw40[0];
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 	powerbase1 = powerlevel[0];
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-	powerbase1 = (powerbase1<<24) | (powerbase1<<16) |
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-		     (powerbase1<<8) | powerbase1;
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+	powerbase1 = (powerbase1 << 24) | (powerbase1 << 16) |
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+		     (powerbase1 << 8) | powerbase1;
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 	*mcs_base = powerbase1;
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 }
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+
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 static void get_rx_power_val_by_reg(struct adapter *adapt, u8 channel,
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 				    u8 index, u32 *powerbase0, u32 *powerbase1,
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 				    u32 *out_val)
..
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@@ -157,28 +158,17 @@
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 		switch (regulatory) {
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 		case 0:
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 			chnlGroup = 0;
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-			write_val = hal_data->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)] +
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+			write_val = hal_data->MCSTxPowerLevelOriginalOffset[chnlGroup][index + (rf ? 8 : 0)] +
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 				((index < 2) ? powerbase0[rf] : powerbase1[rf]);
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 			break;
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 		case 1: /*  Realtek regulatory */
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 			/*  increase power diff defined by Realtek for regulatory */
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 			if (hal_data->pwrGroupCnt == 1)
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 				chnlGroup = 0;
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-			if (hal_data->pwrGroupCnt >= hal_data->PGMaxGroup) {
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-				if (channel < 3)
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-					chnlGroup = 0;
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-				else if (channel < 6)
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-					chnlGroup = 1;
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-				else if (channel < 9)
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-					chnlGroup = 2;
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-				else if (channel < 12)
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-					chnlGroup = 3;
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-				else if (channel < 14)
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-					chnlGroup = 4;
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-				else if (channel == 14)
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-					chnlGroup = 5;
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-			}
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-			write_val = hal_data->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)] +
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+			if (hal_data->pwrGroupCnt >= hal_data->PGMaxGroup)
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+				Hal_GetChnlGroup88E(channel, &chnlGroup);
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+
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+			write_val = hal_data->MCSTxPowerLevelOriginalOffset[chnlGroup][index + (rf ? 8 : 0)] +
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 					((index < 2) ? powerbase0[rf] : powerbase1[rf]);
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 			break;
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 		case 2:	/*  Better regulatory */
..
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@@ -190,14 +180,14 @@
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 			chnlGroup = 0;
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 			if (index < 2)
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-				pwr_diff = hal_data->TxPwrLegacyHtDiff[rf][channel-1];
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+				pwr_diff = hal_data->TxPwrLegacyHtDiff[rf][channel - 1];
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 			else if (hal_data->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
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-				pwr_diff = hal_data->TxPwrHt20Diff[rf][channel-1];
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+				pwr_diff = hal_data->TxPwrHt20Diff[rf][channel - 1];
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 			if (hal_data->CurrentChannelBW == HT_CHANNEL_WIDTH_40)
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-				customer_pwr_limit = hal_data->PwrGroupHT40[rf][channel-1];
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+				customer_pwr_limit = hal_data->PwrGroupHT40[rf][channel - 1];
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 			else
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-				customer_pwr_limit = hal_data->PwrGroupHT20[rf][channel-1];
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+				customer_pwr_limit = hal_data->PwrGroupHT20[rf][channel - 1];
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 			if (pwr_diff >= customer_pwr_limit)
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 				pwr_diff = 0;
..
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@@ -211,9 +201,9 @@
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 				if (pwr_diff_limit[i] > pwr_diff)
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 					pwr_diff_limit[i] = pwr_diff;
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 			}
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-			customer_limit = (pwr_diff_limit[3]<<24) |
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-					 (pwr_diff_limit[2]<<16) |
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-					 (pwr_diff_limit[1]<<8) |
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+			customer_limit = (pwr_diff_limit[3] << 24) |
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+					 (pwr_diff_limit[2] << 16) |
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+					 (pwr_diff_limit[1] << 8) |
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 					 (pwr_diff_limit[0]);
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 			write_val = customer_limit + ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
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 			break;
..
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@@ -232,7 +222,7 @@
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 		else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
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 			write_val = 0x00000000;
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-		*(out_val+rf) = write_val;
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+		*(out_val + rf) = write_val;
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 	}
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 }
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..
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@@ -251,12 +241,12 @@
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 	for (rf = 0; rf < 2; rf++) {
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 		write_val = pvalue[rf];
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 		for (i = 0; i < 4; i++) {
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-			pwr_val[i] = (u8)((write_val & (0x7f<<(i*8)))>>(i*8));
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+			pwr_val[i] = (u8)((write_val & (0x7f << (i * 8))) >> (i * 8));
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 			if (pwr_val[i]  > RF6052_MAX_TX_PWR)
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 				pwr_val[i]  = RF6052_MAX_TX_PWR;
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 		}
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-		write_val = (pwr_val[3]<<24) | (pwr_val[2]<<16) |
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-			    (pwr_val[1]<<8) | pwr_val[0];
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+		write_val = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
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+			    (pwr_val[1] << 8) | pwr_val[0];
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 		if (rf == 0)
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 			regoffset = regoffset_a[index];