disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/soc/fsl/qe/ucc_slow.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
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  *
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@@ -6,11 +7,6 @@
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  *
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  * Description:
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  * QE UCC Slow API Set - UCC Slow specific routines implementations.
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- *
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- * This program is free software; you can redistribute  it and/or modify it
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- * under  the terms of  the GNU General  Public License as published by the
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- * Free Software Foundation;  either version 2 of the  License, or (at your
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- * option) any later version.
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  */
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 #include <linux/kernel.h>
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 #include <linux/errno.h>
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@@ -76,13 +72,13 @@
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 void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)
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 {
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-	struct ucc_slow *us_regs;
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+	struct ucc_slow __iomem *us_regs;
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 	u32 gumr_l;
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 	us_regs = uccs->us_regs;
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 	/* Enable reception and/or transmission on this UCC. */
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-	gumr_l = in_be32(&us_regs->gumr_l);
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+	gumr_l = qe_ioread32be(&us_regs->gumr_l);
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 	if (mode & COMM_DIR_TX) {
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 		gumr_l |= UCC_SLOW_GUMR_L_ENT;
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 		uccs->enabled_tx = 1;
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@@ -91,19 +87,19 @@
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 		gumr_l |= UCC_SLOW_GUMR_L_ENR;
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 		uccs->enabled_rx = 1;
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 	}
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-	out_be32(&us_regs->gumr_l, gumr_l);
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+	qe_iowrite32be(gumr_l, &us_regs->gumr_l);
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 }
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 EXPORT_SYMBOL(ucc_slow_enable);
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 void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
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 {
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-	struct ucc_slow *us_regs;
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+	struct ucc_slow __iomem *us_regs;
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 	u32 gumr_l;
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 	us_regs = uccs->us_regs;
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 	/* Disable reception and/or transmission on this UCC. */
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-	gumr_l = in_be32(&us_regs->gumr_l);
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+	gumr_l = qe_ioread32be(&us_regs->gumr_l);
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 	if (mode & COMM_DIR_TX) {
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 		gumr_l &= ~UCC_SLOW_GUMR_L_ENT;
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 		uccs->enabled_tx = 0;
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@@ -112,7 +108,7 @@
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 		gumr_l &= ~UCC_SLOW_GUMR_L_ENR;
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 		uccs->enabled_rx = 0;
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 	}
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-	out_be32(&us_regs->gumr_l, gumr_l);
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+	qe_iowrite32be(gumr_l, &us_regs->gumr_l);
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 }
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 EXPORT_SYMBOL(ucc_slow_disable);
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@@ -126,7 +122,7 @@
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 	u32 i;
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 	struct ucc_slow __iomem *us_regs;
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 	u32 gumr;
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-	struct qe_bd *bd;
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+	struct qe_bd __iomem *bd;
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 	u32 id;
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 	u32 command;
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 	int ret = 0;
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@@ -158,6 +154,9 @@
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 			__func__);
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 		return -ENOMEM;
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 	}
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+	uccs->rx_base_offset = -1;
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+	uccs->tx_base_offset = -1;
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+	uccs->us_pram_offset = -1;
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 	/* Fill slow UCC structure */
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 	uccs->us_info = us_info;
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@@ -169,21 +168,14 @@
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 		return -ENOMEM;
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 	}
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-	uccs->saved_uccm = 0;
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-	uccs->p_rx_frame = 0;
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 	us_regs = uccs->us_regs;
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-	uccs->p_ucce = (u16 *) & (us_regs->ucce);
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-	uccs->p_uccm = (u16 *) & (us_regs->uccm);
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-#ifdef STATISTICS
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-	uccs->rx_frames = 0;
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-	uccs->tx_frames = 0;
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-	uccs->rx_discarded = 0;
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-#endif				/* STATISTICS */
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+	uccs->p_ucce = &us_regs->ucce;
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+	uccs->p_uccm = &us_regs->uccm;
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 	/* Get PRAM base */
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 	uccs->us_pram_offset =
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 		qe_muram_alloc(UCC_SLOW_PRAM_SIZE, ALIGNMENT_OF_UCC_SLOW_PRAM);
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-	if (IS_ERR_VALUE(uccs->us_pram_offset)) {
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+	if (uccs->us_pram_offset < 0) {
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 		printk(KERN_ERR "%s: cannot allocate MURAM for PRAM", __func__);
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 		ucc_slow_free(uccs);
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 		return -ENOMEM;
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@@ -202,7 +194,7 @@
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 		return ret;
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 	}
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-	out_be16(&uccs->us_pram->mrblr, us_info->max_rx_buf_length);
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+	qe_iowrite16be(us_info->max_rx_buf_length, &uccs->us_pram->mrblr);
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 	INIT_LIST_HEAD(&uccs->confQ);
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@@ -210,10 +202,9 @@
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 	uccs->rx_base_offset =
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 		qe_muram_alloc(us_info->rx_bd_ring_len * sizeof(struct qe_bd),
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 				QE_ALIGNMENT_OF_BD);
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-	if (IS_ERR_VALUE(uccs->rx_base_offset)) {
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+	if (uccs->rx_base_offset < 0) {
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 		printk(KERN_ERR "%s: cannot allocate %u RX BDs\n", __func__,
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 			us_info->rx_bd_ring_len);
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-		uccs->rx_base_offset = 0;
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 		ucc_slow_free(uccs);
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 		return -ENOMEM;
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 	}
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@@ -221,9 +212,8 @@
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 	uccs->tx_base_offset =
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 		qe_muram_alloc(us_info->tx_bd_ring_len * sizeof(struct qe_bd),
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 			QE_ALIGNMENT_OF_BD);
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-	if (IS_ERR_VALUE(uccs->tx_base_offset)) {
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+	if (uccs->tx_base_offset < 0) {
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 		printk(KERN_ERR "%s: cannot allocate TX BDs", __func__);
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-		uccs->tx_base_offset = 0;
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 		ucc_slow_free(uccs);
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 		return -ENOMEM;
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 	}
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@@ -232,27 +222,27 @@
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 	bd = uccs->confBd = uccs->tx_bd = qe_muram_addr(uccs->tx_base_offset);
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 	for (i = 0; i < us_info->tx_bd_ring_len - 1; i++) {
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 		/* clear bd buffer */
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-		out_be32(&bd->buf, 0);
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+		qe_iowrite32be(0, &bd->buf);
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 		/* set bd status and length */
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-		out_be32((u32 *) bd, 0);
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+		qe_iowrite32be(0, (u32 __iomem *)bd);
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 		bd++;
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 	}
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 	/* for last BD set Wrap bit */
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-	out_be32(&bd->buf, 0);
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-	out_be32((u32 *) bd, cpu_to_be32(T_W));
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+	qe_iowrite32be(0, &bd->buf);
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+	qe_iowrite32be(T_W, (u32 __iomem *)bd);
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 	/* Init Rx bds */
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 	bd = uccs->rx_bd = qe_muram_addr(uccs->rx_base_offset);
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 	for (i = 0; i < us_info->rx_bd_ring_len - 1; i++) {
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 		/* set bd status and length */
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-		out_be32((u32*)bd, 0);
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+		qe_iowrite32be(0, (u32 __iomem *)bd);
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 		/* clear bd buffer */
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-		out_be32(&bd->buf, 0);
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+		qe_iowrite32be(0, &bd->buf);
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 		bd++;
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 	}
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 	/* for last BD set Wrap bit */
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-	out_be32((u32*)bd, cpu_to_be32(R_W));
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-	out_be32(&bd->buf, 0);
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+	qe_iowrite32be(R_W, (u32 __iomem *)bd);
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+	qe_iowrite32be(0, &bd->buf);
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 	/* Set GUMR (For more details see the hardware spec.). */
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 	/* gumr_h */
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@@ -273,11 +263,11 @@
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 		gumr |= UCC_SLOW_GUMR_H_TXSY;
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 	if (us_info->rtsm)
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 		gumr |= UCC_SLOW_GUMR_H_RTSM;
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-	out_be32(&us_regs->gumr_h, gumr);
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+	qe_iowrite32be(gumr, &us_regs->gumr_h);
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 	/* gumr_l */
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-	gumr = us_info->tdcr | us_info->rdcr | us_info->tenc | us_info->renc |
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-		us_info->diag | us_info->mode;
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+	gumr = (u32)us_info->tdcr | (u32)us_info->rdcr | (u32)us_info->tenc |
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+	       (u32)us_info->renc | (u32)us_info->diag | (u32)us_info->mode;
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 	if (us_info->tci)
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 		gumr |= UCC_SLOW_GUMR_L_TCI;
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 	if (us_info->rinv)
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@@ -286,18 +276,18 @@
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 		gumr |= UCC_SLOW_GUMR_L_TINV;
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 	if (us_info->tend)
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 		gumr |= UCC_SLOW_GUMR_L_TEND;
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-	out_be32(&us_regs->gumr_l, gumr);
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+	qe_iowrite32be(gumr, &us_regs->gumr_l);
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 	/* Function code registers */
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 	/* if the data is in cachable memory, the 'global' */
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 	/* in the function code should be set. */
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-	uccs->us_pram->tbmr = UCC_BMR_BO_BE;
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-	uccs->us_pram->rbmr = UCC_BMR_BO_BE;
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+	qe_iowrite8(UCC_BMR_BO_BE, &uccs->us_pram->tbmr);
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+	qe_iowrite8(UCC_BMR_BO_BE, &uccs->us_pram->rbmr);
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 	/* rbase, tbase are offsets from MURAM base */
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-	out_be16(&uccs->us_pram->rbase, uccs->rx_base_offset);
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-	out_be16(&uccs->us_pram->tbase, uccs->tx_base_offset);
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+	qe_iowrite16be(uccs->rx_base_offset, &uccs->us_pram->rbase);
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+	qe_iowrite16be(uccs->tx_base_offset, &uccs->us_pram->tbase);
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 	/* Mux clocking */
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 	/* Grant Support */
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@@ -327,14 +317,14 @@
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 	}
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 	/* Set interrupt mask register at UCC level. */
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-	out_be16(&us_regs->uccm, us_info->uccm_mask);
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+	qe_iowrite16be(us_info->uccm_mask, &us_regs->uccm);
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 	/* First, clear anything pending at UCC level,
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 	 * otherwise, old garbage may come through
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 	 * as soon as the dam is opened. */
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 	/* Writing '1' clears */
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-	out_be16(&us_regs->ucce, 0xffff);
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+	qe_iowrite16be(0xffff, &us_regs->ucce);
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 	/* Issue QE Init command */
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 	if (us_info->init_tx && us_info->init_rx)
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@@ -356,14 +346,9 @@
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 	if (!uccs)
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 		return;
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-	if (uccs->rx_base_offset)
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-		qe_muram_free(uccs->rx_base_offset);
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-
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-	if (uccs->tx_base_offset)
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-		qe_muram_free(uccs->tx_base_offset);
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-
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-	if (uccs->us_pram)
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-		qe_muram_free(uccs->us_pram_offset);
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+	qe_muram_free(uccs->rx_base_offset);
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+	qe_muram_free(uccs->tx_base_offset);
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+	qe_muram_free(uccs->us_pram_offset);
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 	if (uccs->us_regs)
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 		iounmap(uccs->us_regs);