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2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/soc/fsl/qe/qe_io.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * arch/powerpc/sysdev/qe_lib/qe_io.c
34  *
....@@ -7,11 +8,6 @@
78  *
89  * Author: Li Yang <LeoLi@freescale.com>
910  * Based on code from Shlomi Gridish <gridish@freescale.com>
10
- *
11
- * This program is free software; you can redistribute  it and/or modify it
12
- * under  the terms of  the GNU General  Public License as published by the
13
- * Free Software Foundation;  either version 2 of the  License, or (at your
14
- * option) any later version.
1511  */
1612 
1713 #include <linux/stddef.h>
....@@ -22,8 +18,6 @@
2218 
2319 #include <asm/io.h>
2420 #include <soc/fsl/qe/qe.h>
25
-#include <asm/prom.h>
26
-#include <sysdev/fsl_soc.h>
2721 
2822 #undef DEBUG
2923 
....@@ -34,17 +28,18 @@
3428 {
3529 	struct resource res;
3630 	int ret;
37
-	const u32 *num_ports;
31
+	u32 num_ports;
3832 
3933 	/* Map Parallel I/O ports registers */
4034 	ret = of_address_to_resource(np, 0, &res);
4135 	if (ret)
4236 		return ret;
4337 	par_io = ioremap(res.start, resource_size(&res));
38
+	if (!par_io)
39
+		return -ENOMEM;
4440 
45
-	num_ports = of_get_property(np, "num-ports", NULL);
46
-	if (num_ports)
47
-		num_par_io_ports = *num_ports;
41
+	if (!of_property_read_u32(np, "num-ports", &num_ports))
42
+		num_par_io_ports = num_ports;
4843 
4944 	return 0;
5045 }
....@@ -61,16 +56,16 @@
6156 	pin_mask1bit = (u32) (1 << (QE_PIO_PINS - (pin + 1)));
6257 
6358 	/* Set open drain, if required */
64
-	tmp_val = in_be32(&par_io->cpodr);
59
+	tmp_val = qe_ioread32be(&par_io->cpodr);
6560 	if (open_drain)
66
-		out_be32(&par_io->cpodr, pin_mask1bit | tmp_val);
61
+		qe_iowrite32be(pin_mask1bit | tmp_val, &par_io->cpodr);
6762 	else
68
-		out_be32(&par_io->cpodr, ~pin_mask1bit & tmp_val);
63
+		qe_iowrite32be(~pin_mask1bit & tmp_val, &par_io->cpodr);
6964 
7065 	/* define direction */
7166 	tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
72
-		in_be32(&par_io->cpdir2) :
73
-		in_be32(&par_io->cpdir1);
67
+		qe_ioread32be(&par_io->cpdir2) :
68
+		qe_ioread32be(&par_io->cpdir1);
7469 
7570 	/* get all bits mask for 2 bit per port */
7671 	pin_mask2bits = (u32) (0x3 << (QE_PIO_PINS -
....@@ -82,34 +77,30 @@
8277 
8378 	/* clear and set 2 bits mask */
8479 	if (pin > (QE_PIO_PINS / 2) - 1) {
85
-		out_be32(&par_io->cpdir2,
86
-			 ~pin_mask2bits & tmp_val);
80
+		qe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir2);
8781 		tmp_val &= ~pin_mask2bits;
88
-		out_be32(&par_io->cpdir2, new_mask2bits | tmp_val);
82
+		qe_iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir2);
8983 	} else {
90
-		out_be32(&par_io->cpdir1,
91
-			 ~pin_mask2bits & tmp_val);
84
+		qe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir1);
9285 		tmp_val &= ~pin_mask2bits;
93
-		out_be32(&par_io->cpdir1, new_mask2bits | tmp_val);
86
+		qe_iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir1);
9487 	}
9588 	/* define pin assignment */
9689 	tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
97
-		in_be32(&par_io->cppar2) :
98
-		in_be32(&par_io->cppar1);
90
+		qe_ioread32be(&par_io->cppar2) :
91
+		qe_ioread32be(&par_io->cppar1);
9992 
10093 	new_mask2bits = (u32) (assignment << (QE_PIO_PINS -
10194 			(pin % (QE_PIO_PINS / 2) + 1) * 2));
10295 	/* clear and set 2 bits mask */
10396 	if (pin > (QE_PIO_PINS / 2) - 1) {
104
-		out_be32(&par_io->cppar2,
105
-			 ~pin_mask2bits & tmp_val);
97
+		qe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar2);
10698 		tmp_val &= ~pin_mask2bits;
107
-		out_be32(&par_io->cppar2, new_mask2bits | tmp_val);
99
+		qe_iowrite32be(new_mask2bits | tmp_val, &par_io->cppar2);
108100 	} else {
109
-		out_be32(&par_io->cppar1,
110
-			 ~pin_mask2bits & tmp_val);
101
+		qe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar1);
111102 		tmp_val &= ~pin_mask2bits;
112
-		out_be32(&par_io->cppar1, new_mask2bits | tmp_val);
103
+		qe_iowrite32be(new_mask2bits | tmp_val, &par_io->cppar1);
113104 	}
114105 }
115106 EXPORT_SYMBOL(__par_io_config_pin);
....@@ -137,12 +128,12 @@
137128 	/* calculate pin location */
138129 	pin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin));
139130 
140
-	tmp_val = in_be32(&par_io[port].cpdata);
131
+	tmp_val = qe_ioread32be(&par_io[port].cpdata);
141132 
142133 	if (val == 0)		/* clear */
143
-		out_be32(&par_io[port].cpdata, ~pin_mask & tmp_val);
134
+		qe_iowrite32be(~pin_mask & tmp_val, &par_io[port].cpdata);
144135 	else			/* set */
145
-		out_be32(&par_io[port].cpdata, pin_mask | tmp_val);
136
+		qe_iowrite32be(pin_mask | tmp_val, &par_io[port].cpdata);
146137 
147138 	return 0;
148139 }
....@@ -151,22 +142,19 @@
151142 int par_io_of_config(struct device_node *np)
152143 {
153144 	struct device_node *pio;
154
-	const phandle *ph;
155145 	int pio_map_len;
156
-	const unsigned int *pio_map;
146
+	const __be32 *pio_map;
157147 
158148 	if (par_io == NULL) {
159149 		printk(KERN_ERR "par_io not initialized\n");
160150 		return -1;
161151 	}
162152 
163
-	ph = of_get_property(np, "pio-handle", NULL);
164
-	if (ph == NULL) {
153
+	pio = of_parse_phandle(np, "pio-handle", 0);
154
+	if (pio == NULL) {
165155 		printk(KERN_ERR "pio-handle not available\n");
166156 		return -1;
167157 	}
168
-
169
-	pio = of_find_node_by_phandle(*ph);
170158 
171159 	pio_map = of_get_property(pio, "pio-map", &pio_map_len);
172160 	if (pio_map == NULL) {
....@@ -180,9 +168,15 @@
180168 	}
181169 
182170 	while (pio_map_len > 0) {
183
-		par_io_config_pin((u8) pio_map[0], (u8) pio_map[1],
184
-				(int) pio_map[2], (int) pio_map[3],
185
-				(int) pio_map[4], (int) pio_map[5]);
171
+		u8 port        = be32_to_cpu(pio_map[0]);
172
+		u8 pin         = be32_to_cpu(pio_map[1]);
173
+		int dir        = be32_to_cpu(pio_map[2]);
174
+		int open_drain = be32_to_cpu(pio_map[3]);
175
+		int assignment = be32_to_cpu(pio_map[4]);
176
+		int has_irq    = be32_to_cpu(pio_map[5]);
177
+
178
+		par_io_config_pin(port, pin, dir, open_drain,
179
+				  assignment, has_irq);
186180 		pio_map += 6;
187181 		pio_map_len -= 6;
188182 	}