disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/soc/fsl/qe/gpio.c
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@@ -1,14 +1,10 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  * QUICC Engine GPIOs
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  *
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  * Copyright (c) MontaVista Software, Inc. 2008.
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  *
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  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
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- *
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- * This program is free software; you can redistribute  it and/or modify it
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- * under  the terms of  the GNU General  Public License as published by the
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- * Free Software Foundation;  either version 2 of the  License, or (at your
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- * option) any later version.
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  */
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 #include <linux/kernel.h>
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@@ -45,13 +41,13 @@
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 		container_of(mm_gc, struct qe_gpio_chip, mm_gc);
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 	struct qe_pio_regs __iomem *regs = mm_gc->regs;
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-	qe_gc->cpdata = in_be32(&regs->cpdata);
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+	qe_gc->cpdata = qe_ioread32be(&regs->cpdata);
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 	qe_gc->saved_regs.cpdata = qe_gc->cpdata;
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-	qe_gc->saved_regs.cpdir1 = in_be32(&regs->cpdir1);
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-	qe_gc->saved_regs.cpdir2 = in_be32(&regs->cpdir2);
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-	qe_gc->saved_regs.cppar1 = in_be32(&regs->cppar1);
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-	qe_gc->saved_regs.cppar2 = in_be32(&regs->cppar2);
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-	qe_gc->saved_regs.cpodr = in_be32(&regs->cpodr);
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+	qe_gc->saved_regs.cpdir1 = qe_ioread32be(&regs->cpdir1);
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+	qe_gc->saved_regs.cpdir2 = qe_ioread32be(&regs->cpdir2);
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+	qe_gc->saved_regs.cppar1 = qe_ioread32be(&regs->cppar1);
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+	qe_gc->saved_regs.cppar2 = qe_ioread32be(&regs->cppar2);
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+	qe_gc->saved_regs.cpodr = qe_ioread32be(&regs->cpodr);
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 }
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 static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
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@@ -60,7 +56,7 @@
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 	struct qe_pio_regs __iomem *regs = mm_gc->regs;
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 	u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
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-	return !!(in_be32(&regs->cpdata) & pin_mask);
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+	return !!(qe_ioread32be(&regs->cpdata) & pin_mask);
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 }
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 static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
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@@ -78,7 +74,7 @@
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 	else
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 		qe_gc->cpdata &= ~pin_mask;
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-	out_be32(&regs->cpdata, qe_gc->cpdata);
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+	qe_iowrite32be(qe_gc->cpdata, &regs->cpdata);
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 	spin_unlock_irqrestore(&qe_gc->lock, flags);
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 }
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@@ -105,7 +101,7 @@
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 		}
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 	}
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-	out_be32(&regs->cpdata, qe_gc->cpdata);
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+	qe_iowrite32be(qe_gc->cpdata, &regs->cpdata);
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 	spin_unlock_irqrestore(&qe_gc->lock, flags);
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 }
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@@ -164,7 +160,6 @@
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 {
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 	struct qe_pin *qe_pin;
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 	struct gpio_chip *gc;
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-	struct of_mm_gpio_chip *mm_gc;
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 	struct qe_gpio_chip *qe_gc;
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 	int err;
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 	unsigned long flags;
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@@ -190,7 +185,6 @@
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 		goto err0;
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 	}
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-	mm_gc = to_of_mm_gpio_chip(gc);
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 	qe_gc = gpiochip_get_data(gc);
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 	spin_lock_irqsave(&qe_gc->lock, flags);
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@@ -259,11 +253,15 @@
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 	spin_lock_irqsave(&qe_gc->lock, flags);
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 	if (second_reg) {
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-		clrsetbits_be32(&regs->cpdir2, mask2, sregs->cpdir2 & mask2);
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-		clrsetbits_be32(&regs->cppar2, mask2, sregs->cppar2 & mask2);
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+		qe_clrsetbits_be32(&regs->cpdir2, mask2,
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+				   sregs->cpdir2 & mask2);
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+		qe_clrsetbits_be32(&regs->cppar2, mask2,
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+				   sregs->cppar2 & mask2);
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 	} else {
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-		clrsetbits_be32(&regs->cpdir1, mask2, sregs->cpdir1 & mask2);
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-		clrsetbits_be32(&regs->cppar1, mask2, sregs->cppar1 & mask2);
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+		qe_clrsetbits_be32(&regs->cpdir1, mask2,
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+				   sregs->cpdir1 & mask2);
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+		qe_clrsetbits_be32(&regs->cppar1, mask2,
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+				   sregs->cppar1 & mask2);
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 	}
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 	if (sregs->cpdata & mask1)
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@@ -271,8 +269,8 @@
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 	else
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 		qe_gc->cpdata &= ~mask1;
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-	out_be32(&regs->cpdata, qe_gc->cpdata);
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-	clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1);
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+	qe_iowrite32be(qe_gc->cpdata, &regs->cpdata);
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+	qe_clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1);
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 	spin_unlock_irqrestore(&qe_gc->lock, flags);
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 }