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2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
....@@ -1,12 +1,7 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Copyright (c) 2016 Linaro Ltd.
34  * Copyright (c) 2016 Hisilicon Limited.
4
- *
5
- * This program is free software; you can redistribute it and/or modify
6
- * it under the terms of the GNU General Public License as published by
7
- * the Free Software Foundation; either version 2 of the License, or
8
- * (at your option) any later version.
9
- *
105  */
116 
127 #include "hisi_sas.h"
....@@ -427,70 +422,70 @@
427422 		.irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF),
428423 		.msk = HGC_DQE_ECC_1B_ADDR_MSK,
429424 		.shift = HGC_DQE_ECC_1B_ADDR_OFF,
430
-		.msg = "hgc_dqe_acc1b_intr found: Ram address is 0x%08X\n",
425
+		.msg = "hgc_dqe_ecc1b_intr",
431426 		.reg = HGC_DQE_ECC_ADDR,
432427 	},
433428 	{
434429 		.irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF),
435430 		.msk = HGC_IOST_ECC_1B_ADDR_MSK,
436431 		.shift = HGC_IOST_ECC_1B_ADDR_OFF,
437
-		.msg = "hgc_iost_acc1b_intr found: Ram address is 0x%08X\n",
432
+		.msg = "hgc_iost_ecc1b_intr",
438433 		.reg = HGC_IOST_ECC_ADDR,
439434 	},
440435 	{
441436 		.irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF),
442437 		.msk = HGC_ITCT_ECC_1B_ADDR_MSK,
443438 		.shift = HGC_ITCT_ECC_1B_ADDR_OFF,
444
-		.msg = "hgc_itct_acc1b_intr found: am address is 0x%08X\n",
439
+		.msg = "hgc_itct_ecc1b_intr",
445440 		.reg = HGC_ITCT_ECC_ADDR,
446441 	},
447442 	{
448443 		.irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF),
449444 		.msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
450445 		.shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
451
-		.msg = "hgc_iostl_acc1b_intr found: memory address is 0x%08X\n",
446
+		.msg = "hgc_iostl_ecc1b_intr",
452447 		.reg = HGC_LM_DFX_STATUS2,
453448 	},
454449 	{
455450 		.irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF),
456451 		.msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
457452 		.shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
458
-		.msg = "hgc_itctl_acc1b_intr found: memory address is 0x%08X\n",
453
+		.msg = "hgc_itctl_ecc1b_intr",
459454 		.reg = HGC_LM_DFX_STATUS2,
460455 	},
461456 	{
462457 		.irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF),
463458 		.msk = HGC_CQE_ECC_1B_ADDR_MSK,
464459 		.shift = HGC_CQE_ECC_1B_ADDR_OFF,
465
-		.msg = "hgc_cqe_acc1b_intr found: Ram address is 0x%08X\n",
460
+		.msg = "hgc_cqe_ecc1b_intr",
466461 		.reg = HGC_CQE_ECC_ADDR,
467462 	},
468463 	{
469464 		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF),
470465 		.msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
471466 		.shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
472
-		.msg = "rxm_mem0_acc1b_intr found: memory address is 0x%08X\n",
467
+		.msg = "rxm_mem0_ecc1b_intr",
473468 		.reg = HGC_RXM_DFX_STATUS14,
474469 	},
475470 	{
476471 		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF),
477472 		.msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
478473 		.shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
479
-		.msg = "rxm_mem1_acc1b_intr found: memory address is 0x%08X\n",
474
+		.msg = "rxm_mem1_ecc1b_intr",
480475 		.reg = HGC_RXM_DFX_STATUS14,
481476 	},
482477 	{
483478 		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF),
484479 		.msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
485480 		.shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
486
-		.msg = "rxm_mem2_acc1b_intr found: memory address is 0x%08X\n",
481
+		.msg = "rxm_mem2_ecc1b_intr",
487482 		.reg = HGC_RXM_DFX_STATUS14,
488483 	},
489484 	{
490485 		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF),
491486 		.msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
492487 		.shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
493
-		.msg = "rxm_mem3_acc1b_intr found: memory address is 0x%08X\n",
488
+		.msg = "rxm_mem3_ecc1b_intr",
494489 		.reg = HGC_RXM_DFX_STATUS15,
495490 	},
496491 };
....@@ -500,70 +495,70 @@
500495 		.irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
501496 		.msk = HGC_DQE_ECC_MB_ADDR_MSK,
502497 		.shift = HGC_DQE_ECC_MB_ADDR_OFF,
503
-		.msg = "hgc_dqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
498
+		.msg = "hgc_dqe_eccbad_intr",
504499 		.reg = HGC_DQE_ECC_ADDR,
505500 	},
506501 	{
507502 		.irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
508503 		.msk = HGC_IOST_ECC_MB_ADDR_MSK,
509504 		.shift = HGC_IOST_ECC_MB_ADDR_OFF,
510
-		.msg = "hgc_iost_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
505
+		.msg = "hgc_iost_eccbad_intr",
511506 		.reg = HGC_IOST_ECC_ADDR,
512507 	},
513508 	{
514509 		.irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
515510 		.msk = HGC_ITCT_ECC_MB_ADDR_MSK,
516511 		.shift = HGC_ITCT_ECC_MB_ADDR_OFF,
517
-		.msg = "hgc_itct_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
512
+		.msg = "hgc_itct_eccbad_intr",
518513 		.reg = HGC_ITCT_ECC_ADDR,
519514 	},
520515 	{
521516 		.irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
522517 		.msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
523518 		.shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
524
-		.msg = "hgc_iostl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
519
+		.msg = "hgc_iostl_eccbad_intr",
525520 		.reg = HGC_LM_DFX_STATUS2,
526521 	},
527522 	{
528523 		.irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
529524 		.msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
530525 		.shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
531
-		.msg = "hgc_itctl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
526
+		.msg = "hgc_itctl_eccbad_intr",
532527 		.reg = HGC_LM_DFX_STATUS2,
533528 	},
534529 	{
535530 		.irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
536531 		.msk = HGC_CQE_ECC_MB_ADDR_MSK,
537532 		.shift = HGC_CQE_ECC_MB_ADDR_OFF,
538
-		.msg = "hgc_cqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
533
+		.msg = "hgc_cqe_eccbad_intr",
539534 		.reg = HGC_CQE_ECC_ADDR,
540535 	},
541536 	{
542537 		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
543538 		.msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
544539 		.shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
545
-		.msg = "rxm_mem0_accbad_intr (0x%x) found: memory address is 0x%08X\n",
540
+		.msg = "rxm_mem0_eccbad_intr",
546541 		.reg = HGC_RXM_DFX_STATUS14,
547542 	},
548543 	{
549544 		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
550545 		.msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
551546 		.shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
552
-		.msg = "rxm_mem1_accbad_intr (0x%x) found: memory address is 0x%08X\n",
547
+		.msg = "rxm_mem1_eccbad_intr",
553548 		.reg = HGC_RXM_DFX_STATUS14,
554549 	},
555550 	{
556551 		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
557552 		.msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
558553 		.shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
559
-		.msg = "rxm_mem2_accbad_intr (0x%x) found: memory address is 0x%08X\n",
554
+		.msg = "rxm_mem2_eccbad_intr",
560555 		.reg = HGC_RXM_DFX_STATUS14,
561556 	},
562557 	{
563558 		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
564559 		.msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
565560 		.shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
566
-		.msg = "rxm_mem3_accbad_intr (0x%x) found: memory address is 0x%08X\n",
561
+		.msg = "rxm_mem3_eccbad_intr",
567562 		.reg = HGC_RXM_DFX_STATUS15,
568563 	},
569564 };
....@@ -770,7 +765,7 @@
770765 
771766 /* This function needs to be protected from pre-emption. */
772767 static int
773
-slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba, int *slot_idx,
768
+slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba,
774769 			     struct domain_device *device)
775770 {
776771 	int sata_dev = dev_is_sata(device);
....@@ -801,11 +796,14 @@
801796 		end = 64 * (sata_idx + 2);
802797 	}
803798 
799
+	spin_lock(&hisi_hba->lock);
804800 	while (1) {
805801 		start = find_next_zero_bit(bitmap,
806802 					hisi_hba->slot_index_count, start);
807
-		if (start >= end)
803
+		if (start >= end) {
804
+			spin_unlock(&hisi_hba->lock);
808805 			return -SAS_QUEUE_FULL;
806
+		}
809807 		/*
810808 		  * SAS IPTT bit0 should be 1, and SATA IPTT bit0 should be 0.
811809 		  */
....@@ -815,8 +813,8 @@
815813 	}
816814 
817815 	set_bit(start, bitmap);
818
-	*slot_idx = start;
819
-	return 0;
816
+	spin_unlock(&hisi_hba->lock);
817
+	return start;
820818 }
821819 
822820 static bool sata_index_alloc_v2_hw(struct hisi_hba *hisi_hba, int *idx)
....@@ -844,9 +842,8 @@
844842 	struct hisi_sas_device *sas_dev = NULL;
845843 	int i, sata_dev = dev_is_sata(device);
846844 	int sata_idx = -1;
847
-	unsigned long flags;
848845 
849
-	spin_lock_irqsave(&hisi_hba->lock, flags);
846
+	spin_lock(&hisi_hba->lock);
850847 
851848 	if (sata_dev)
852849 		if (!sata_index_alloc_v2_hw(hisi_hba, &sata_idx))
....@@ -864,19 +861,20 @@
864861 
865862 			hisi_hba->devices[i].device_id = i;
866863 			sas_dev = &hisi_hba->devices[i];
867
-			sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
864
+			sas_dev->dev_status = HISI_SAS_DEV_INIT;
868865 			sas_dev->dev_type = device->dev_type;
869866 			sas_dev->hisi_hba = hisi_hba;
870867 			sas_dev->sas_device = device;
871868 			sas_dev->sata_idx = sata_idx;
872869 			sas_dev->dq = dq;
870
+			spin_lock_init(&sas_dev->lock);
873871 			INIT_LIST_HEAD(&hisi_hba->devices[i].list);
874872 			break;
875873 		}
876874 	}
877875 
878876 out:
879
-	spin_unlock_irqrestore(&hisi_hba->lock, flags);
877
+	spin_unlock(&hisi_hba->lock);
880878 
881879 	return sas_dev;
882880 }
....@@ -930,6 +928,7 @@
930928 	struct domain_device *parent_dev = device->parent;
931929 	struct asd_sas_port *sas_port = device->port;
932930 	struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
931
+	u64 sas_addr;
933932 
934933 	memset(itct, 0, sizeof(*itct));
935934 
....@@ -943,7 +942,7 @@
943942 		break;
944943 	case SAS_SATA_DEV:
945944 	case SAS_SATA_PENDING:
946
-		if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
945
+		if (parent_dev && dev_is_expander(parent_dev->dev_type))
947946 			qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
948947 		else
949948 			qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
....@@ -962,8 +961,8 @@
962961 	itct->qw0 = cpu_to_le64(qw0);
963962 
964963 	/* qw1 */
965
-	memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
966
-	itct->sas_addr = __swab64(itct->sas_addr);
964
+	memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE);
965
+	itct->sas_addr = cpu_to_le64(__swab64(sas_addr));
967966 
968967 	/* qw2 */
969968 	if (!dev_is_sata(device))
....@@ -973,13 +972,14 @@
973972 					(0x1ULL << ITCT_HDR_RTOLT_OFF));
974973 }
975974 
976
-static void clear_itct_v2_hw(struct hisi_hba *hisi_hba,
977
-			      struct hisi_sas_device *sas_dev)
975
+static int clear_itct_v2_hw(struct hisi_hba *hisi_hba,
976
+			    struct hisi_sas_device *sas_dev)
978977 {
979978 	DECLARE_COMPLETION_ONSTACK(completion);
980979 	u64 dev_id = sas_dev->device_id;
981980 	struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
982981 	u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
982
+	struct device *dev = hisi_hba->dev;
983983 	int i;
984984 
985985 	sas_dev->completion = &completion;
....@@ -989,13 +989,19 @@
989989 		hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
990990 				 ENT_INT_SRC3_ITC_INT_MSK);
991991 
992
+	/* need to set register twice to clear ITCT for v2 hw */
992993 	for (i = 0; i < 2; i++) {
993994 		reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
994995 		hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
995
-		wait_for_completion(sas_dev->completion);
996
+		if (!wait_for_completion_timeout(sas_dev->completion,
997
+						 CLEAR_ITCT_TIMEOUT * HZ)) {
998
+			dev_warn(dev, "failed to clear ITCT\n");
999
+			return -ETIMEDOUT;
1000
+		}
9961001 
9971002 		memset(itct, 0, sizeof(struct hisi_sas_itct));
9981003 	}
1004
+	return 0;
9991005 }
10001006 
10011007 static void free_device_v2_hw(struct hisi_sas_device *sas_dev)
....@@ -1196,7 +1202,7 @@
11961202 	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffe20fe);
11971203 	hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfff00c30);
11981204 	for (i = 0; i < hisi_hba->queue_count; i++)
1199
-		hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
1205
+		hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0);
12001206 
12011207 	hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
12021208 	hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
....@@ -1376,7 +1382,7 @@
13761382 
13771383 	rc = reset_hw_v2_hw(hisi_hba);
13781384 	if (rc) {
1379
-		dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
1385
+		dev_err(dev, "hisi_sas_reset_hw failed, rc=%d\n", rc);
13801386 		return rc;
13811387 	}
13821388 
....@@ -1540,14 +1546,14 @@
15401546 	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
15411547 	u32 txid_auto;
15421548 
1543
-	disable_phy_v2_hw(hisi_hba, phy_no);
1549
+	hisi_sas_phy_enable(hisi_hba, phy_no, 0);
15441550 	if (phy->identify.device_type == SAS_END_DEVICE) {
15451551 		txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
15461552 		hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
15471553 					txid_auto | TX_HARDRST_MSK);
15481554 	}
15491555 	msleep(100);
1550
-	start_phy_v2_hw(hisi_hba, phy_no);
1556
+	hisi_sas_phy_enable(hisi_hba, phy_no, 1);
15511557 }
15521558 
15531559 static void phy_get_events_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
....@@ -1580,7 +1586,7 @@
15801586 		if (!sas_phy->phy->enabled)
15811587 			continue;
15821588 
1583
-		start_phy_v2_hw(hisi_hba, i);
1589
+		hisi_sas_phy_enable(hisi_hba, i, 1);
15841590 	}
15851591 }
15861592 
....@@ -1634,31 +1640,6 @@
16341640 	}
16351641 
16361642 	return bitmap;
1637
-}
1638
-
1639
-/*
1640
- * The callpath to this function and upto writing the write
1641
- * queue pointer should be safe from interruption.
1642
- */
1643
-static int
1644
-get_free_slot_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
1645
-{
1646
-	struct device *dev = hisi_hba->dev;
1647
-	int queue = dq->id;
1648
-	u32 r, w;
1649
-
1650
-	w = dq->wr_point;
1651
-	r = hisi_sas_read32_relaxed(hisi_hba,
1652
-				DLVRY_Q_0_RD_PTR + (queue * 0x14));
1653
-	if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
1654
-		dev_warn(dev, "full queue=%d r=%d w=%d\n",
1655
-				queue, r, w);
1656
-		return -EAGAIN;
1657
-	}
1658
-
1659
-	dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS;
1660
-
1661
-	return w;
16621643 }
16631644 
16641645 /* DQ lock must be taken here */
....@@ -2040,11 +2021,16 @@
20402021 	struct task_status_struct *ts = &task->task_status;
20412022 	struct hisi_sas_err_record_v2 *err_record =
20422023 			hisi_sas_status_buf_addr_mem(slot);
2043
-	u32 trans_tx_fail_type = cpu_to_le32(err_record->trans_tx_fail_type);
2044
-	u32 trans_rx_fail_type = cpu_to_le32(err_record->trans_rx_fail_type);
2045
-	u16 dma_tx_err_type = cpu_to_le16(err_record->dma_tx_err_type);
2046
-	u16 sipc_rx_err_type = cpu_to_le16(err_record->sipc_rx_err_type);
2047
-	u32 dma_rx_err_type = cpu_to_le32(err_record->dma_rx_err_type);
2024
+	u32 trans_tx_fail_type = le32_to_cpu(err_record->trans_tx_fail_type);
2025
+	u32 trans_rx_fail_type = le32_to_cpu(err_record->trans_rx_fail_type);
2026
+	u16 dma_tx_err_type = le16_to_cpu(err_record->dma_tx_err_type);
2027
+	u16 sipc_rx_err_type = le16_to_cpu(err_record->sipc_rx_err_type);
2028
+	u32 dma_rx_err_type = le32_to_cpu(err_record->dma_rx_err_type);
2029
+	struct hisi_sas_complete_v2_hdr *complete_queue =
2030
+			hisi_hba->complete_hdr[slot->cmplt_queue];
2031
+	struct hisi_sas_complete_v2_hdr *complete_hdr =
2032
+			&complete_queue[slot->cmplt_queue_slot];
2033
+	u32 dw0 = le32_to_cpu(complete_hdr->dw0);
20482034 	int error = -1;
20492035 
20502036 	if (err_phase == 1) {
....@@ -2055,8 +2041,7 @@
20552041 					trans_tx_fail_type);
20562042 	} else if (err_phase == 2) {
20572043 		/* error in RX phase, the priority is: DW1 > DW3 > DW2 */
2058
-		error = parse_trans_rx_err_code_v2_hw(
2059
-					trans_rx_fail_type);
2044
+		error = parse_trans_rx_err_code_v2_hw(trans_rx_fail_type);
20602045 		if (error == -1) {
20612046 			error = parse_dma_rx_err_code_v2_hw(
20622047 					dma_rx_err_type);
....@@ -2188,7 +2173,7 @@
21882173 	}
21892174 		break;
21902175 	case SAS_PROTOCOL_SMP:
2191
-		ts->stat = SAM_STAT_CHECK_CONDITION;
2176
+		ts->stat = SAS_SAM_STAT_CHECK_CONDITION;
21922177 		break;
21932178 
21942179 	case SAS_PROTOCOL_SATA:
....@@ -2330,7 +2315,8 @@
23302315 			break;
23312316 		}
23322317 		}
2333
-		hisi_sas_sata_done(task, slot);
2318
+		if (dw0 & CMPLT_HDR_RSPNS_XFRD_MSK)
2319
+			hisi_sas_sata_done(task, slot);
23342320 	}
23352321 		break;
23362322 	default:
....@@ -2338,8 +2324,8 @@
23382324 	}
23392325 }
23402326 
2341
-static int
2342
-slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
2327
+static void slot_complete_v2_hw(struct hisi_hba *hisi_hba,
2328
+				struct hisi_sas_slot *slot)
23432329 {
23442330 	struct sas_task *task = slot->task;
23452331 	struct hisi_sas_device *sas_dev;
....@@ -2347,16 +2333,16 @@
23472333 	struct task_status_struct *ts;
23482334 	struct domain_device *device;
23492335 	struct sas_ha_struct *ha;
2350
-	enum exec_status sts;
23512336 	struct hisi_sas_complete_v2_hdr *complete_queue =
23522337 			hisi_hba->complete_hdr[slot->cmplt_queue];
23532338 	struct hisi_sas_complete_v2_hdr *complete_hdr =
23542339 			&complete_queue[slot->cmplt_queue_slot];
23552340 	unsigned long flags;
23562341 	bool is_internal = slot->is_internal;
2342
+	u32 dw0;
23572343 
23582344 	if (unlikely(!task || !task->lldd_task || !task->dev))
2359
-		return -EINVAL;
2345
+		return;
23602346 
23612347 	ts = &task->task_status;
23622348 	device = task->dev;
....@@ -2378,8 +2364,9 @@
23782364 	}
23792365 
23802366 	/* Use SAS+TMF status codes */
2381
-	switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
2382
-			>> CMPLT_HDR_ABORT_STAT_OFF) {
2367
+	dw0 = le32_to_cpu(complete_hdr->dw0);
2368
+	switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >>
2369
+		CMPLT_HDR_ABORT_STAT_OFF) {
23832370 	case STAT_IO_ABORTED:
23842371 		/* this io has been aborted by abort command */
23852372 		ts->stat = SAS_ABORTED_TASK;
....@@ -2404,9 +2391,8 @@
24042391 		break;
24052392 	}
24062393 
2407
-	if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) &&
2408
-		(!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
2409
-		u32 err_phase = (complete_hdr->dw0 & CMPLT_HDR_ERR_PHASE_MSK)
2394
+	if ((dw0 & CMPLT_HDR_ERX_MSK) && (!(dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
2395
+		u32 err_phase = (dw0 & CMPLT_HDR_ERR_PHASE_MSK)
24102396 				>> CMPLT_HDR_ERR_PHASE_OFF;
24112397 		u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
24122398 
....@@ -2417,17 +2403,17 @@
24172403 			slot_err_v2_hw(hisi_hba, task, slot, 2);
24182404 
24192405 		if (ts->stat != SAS_DATA_UNDERRUN)
2420
-			dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d "
2421
-				"CQ hdr: 0x%x 0x%x 0x%x 0x%x "
2422
-				"Error info: 0x%x 0x%x 0x%x 0x%x\n",
2423
-				slot->idx, task, sas_dev->device_id,
2424
-				complete_hdr->dw0, complete_hdr->dw1,
2425
-				complete_hdr->act, complete_hdr->dw3,
2426
-				error_info[0], error_info[1],
2427
-				error_info[2], error_info[3]);
2406
+			dev_info(dev, "erroneous completion iptt=%d task=%pK dev id=%d CQ hdr: 0x%x 0x%x 0x%x 0x%x Error info: 0x%x 0x%x 0x%x 0x%x\n",
2407
+				 slot->idx, task, sas_dev->device_id,
2408
+				 complete_hdr->dw0, complete_hdr->dw1,
2409
+				 complete_hdr->act, complete_hdr->dw3,
2410
+				 error_info[0], error_info[1],
2411
+				 error_info[2], error_info[3]);
24282412 
2429
-		if (unlikely(slot->abort))
2430
-			return ts->stat;
2413
+		if (unlikely(slot->abort)) {
2414
+			sas_task_abort(task);
2415
+			return;
2416
+		}
24312417 		goto out;
24322418 	}
24332419 
....@@ -2445,32 +2431,29 @@
24452431 	case SAS_PROTOCOL_SMP:
24462432 	{
24472433 		struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2448
-		void *to;
2434
+		void *to = page_address(sg_page(sg_resp));
24492435 
2450
-		ts->stat = SAM_STAT_GOOD;
2451
-		to = kmap_atomic(sg_page(sg_resp));
2436
+		ts->stat = SAS_SAM_STAT_GOOD;
24522437 
2453
-		dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
2454
-			     DMA_FROM_DEVICE);
24552438 		dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
24562439 			     DMA_TO_DEVICE);
24572440 		memcpy(to + sg_resp->offset,
24582441 		       hisi_sas_status_buf_addr_mem(slot) +
24592442 		       sizeof(struct hisi_sas_err_record),
2460
-		       sg_dma_len(sg_resp));
2461
-		kunmap_atomic(to);
2443
+		       sg_resp->length);
24622444 		break;
24632445 	}
24642446 	case SAS_PROTOCOL_SATA:
24652447 	case SAS_PROTOCOL_STP:
24662448 	case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
24672449 	{
2468
-		ts->stat = SAM_STAT_GOOD;
2469
-		hisi_sas_sata_done(task, slot);
2450
+		ts->stat = SAS_SAM_STAT_GOOD;
2451
+		if (dw0 & CMPLT_HDR_RSPNS_XFRD_MSK)
2452
+			hisi_sas_sata_done(task, slot);
24702453 		break;
24712454 	}
24722455 	default:
2473
-		ts->stat = SAM_STAT_CHECK_CONDITION;
2456
+		ts->stat = SAS_SAM_STAT_CHECK_CONDITION;
24742457 		break;
24752458 	}
24762459 
....@@ -2481,12 +2464,11 @@
24812464 	}
24822465 
24832466 out:
2484
-	sts = ts->stat;
24852467 	spin_lock_irqsave(&task->task_state_lock, flags);
24862468 	if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
24872469 		spin_unlock_irqrestore(&task->task_state_lock, flags);
2488
-		dev_info(dev, "slot complete: task(%p) aborted\n", task);
2489
-		return SAS_ABORTED_TASK;
2470
+		dev_info(dev, "slot complete: task(%pK) aborted\n", task);
2471
+		return;
24902472 	}
24912473 	task->task_state_flags |= SAS_TASK_STATE_DONE;
24922474 	spin_unlock_irqrestore(&task->task_state_lock, flags);
....@@ -2496,17 +2478,15 @@
24962478 		spin_lock_irqsave(&device->done_lock, flags);
24972479 		if (test_bit(SAS_HA_FROZEN, &ha->state)) {
24982480 			spin_unlock_irqrestore(&device->done_lock, flags);
2499
-			dev_info(dev, "slot complete: task(%p) ignored\n ",
2481
+			dev_info(dev, "slot complete: task(%pK) ignored\n",
25002482 				 task);
2501
-			return sts;
2483
+			return;
25022484 		}
25032485 		spin_unlock_irqrestore(&device->done_lock, flags);
25042486 	}
25052487 
25062488 	if (task->task_done)
25072489 		task->task_done(task);
2508
-
2509
-	return sts;
25102490 }
25112491 
25122492 static void prep_ata_v2_hw(struct hisi_hba *hisi_hba,
....@@ -2522,21 +2502,22 @@
25222502 	struct hisi_sas_tmf_task *tmf = slot->tmf;
25232503 	u8 *buf_cmd;
25242504 	int has_data = 0, hdr_tag = 0;
2525
-	u32 dw1 = 0, dw2 = 0;
2505
+	u32 dw0, dw1 = 0, dw2 = 0;
25262506 
25272507 	/* create header */
25282508 	/* dw0 */
2529
-	hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
2530
-	if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
2531
-		hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
2509
+	dw0 = port->id << CMD_HDR_PORT_OFF;
2510
+	if (parent_dev && dev_is_expander(parent_dev->dev_type))
2511
+		dw0 |= 3 << CMD_HDR_CMD_OFF;
25322512 	else
2533
-		hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
2513
+		dw0 |= 4 << CMD_HDR_CMD_OFF;
25342514 
25352515 	if (tmf && tmf->force_phy) {
2536
-		hdr->dw0 |= CMD_HDR_FORCE_PHY_MSK;
2537
-		hdr->dw0 |= cpu_to_le32((1 << tmf->phy_id)
2538
-				<< CMD_HDR_PHY_ID_OFF);
2516
+		dw0 |= CMD_HDR_FORCE_PHY_MSK;
2517
+		dw0 |= (1 << tmf->phy_id) << CMD_HDR_PHY_ID_OFF;
25392518 	}
2519
+
2520
+	hdr->dw0 = cpu_to_le32(dw0);
25402521 
25412522 	/* dw1 */
25422523 	switch (task->data_dir) {
....@@ -2563,7 +2544,10 @@
25632544 	hdr->dw1 = cpu_to_le32(dw1);
25642545 
25652546 	/* dw2 */
2566
-	if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
2547
+	if (task->ata_task.use_ncq) {
2548
+		struct ata_queued_cmd *qc = task->uldd_task;
2549
+
2550
+		hdr_tag = qc->tag;
25672551 		task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
25682552 		dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
25692553 	}
....@@ -2671,6 +2655,8 @@
26712655 	if (is_sata_phy_v2_hw(hisi_hba, phy_no))
26722656 		goto end;
26732657 
2658
+	del_timer(&phy->timer);
2659
+
26742660 	if (phy_no == 8) {
26752661 		u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
26762662 
....@@ -2750,6 +2736,7 @@
27502736 	struct hisi_sas_port *port = phy->port;
27512737 	struct device *dev = hisi_hba->dev;
27522738 
2739
+	del_timer(&phy->timer);
27532740 	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
27542741 
27552742 	phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
....@@ -2838,14 +2825,13 @@
28382825 {
28392826 	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
28402827 	struct asd_sas_phy *sas_phy = &phy->sas_phy;
2841
-	struct sas_ha_struct *sas_ha = &hisi_hba->sha;
28422828 	u32 bcast_status;
28432829 
28442830 	hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
28452831 	bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
28462832 	if ((bcast_status & RX_BCAST_CHG_MSK) &&
28472833 	    !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
2848
-		sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2834
+		sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
28492835 	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
28502836 			     CHL_INT0_SL_RX_BCST_ACK_MSK);
28512837 	hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
....@@ -2925,7 +2911,7 @@
29252911 
29262912 			if (irq_value2 & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
29272913 				dev_warn(dev, "phy%d identify timeout\n",
2928
-						phy_no);
2914
+					 phy_no);
29292915 				hisi_sas_notify_phy_event(phy,
29302916 						HISI_PHYE_LINK_RESET);
29312917 			}
....@@ -2937,6 +2923,9 @@
29372923 		if ((irq_msk & (1 << phy_no)) && irq_value0) {
29382924 			if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
29392925 				phy_bcast_v2_hw(phy_no, hisi_hba);
2926
+
2927
+			if (irq_value0 & CHL_INT0_PHY_RDY_MSK)
2928
+				hisi_sas_phy_oob_ready(hisi_hba, phy_no);
29402929 
29412930 			hisi_sas_phy_write32(hisi_hba, phy_no,
29422931 					CHL_INT0, irq_value0
....@@ -2967,7 +2956,8 @@
29672956 			val = hisi_sas_read32(hisi_hba, ecc_error->reg);
29682957 			val &= ecc_error->msk;
29692958 			val >>= ecc_error->shift;
2970
-			dev_warn(dev, ecc_error->msg, val);
2959
+			dev_warn(dev, "%s found: mem addr is 0x%08X\n",
2960
+				 ecc_error->msg, val);
29712961 		}
29722962 	}
29732963 }
....@@ -2986,7 +2976,8 @@
29862976 			val = hisi_sas_read32(hisi_hba, ecc_error->reg);
29872977 			val &= ecc_error->msk;
29882978 			val >>= ecc_error->shift;
2989
-			dev_err(dev, ecc_error->msg, irq_value, val);
2979
+			dev_err(dev, "%s (0x%x) found: mem addr is 0x%08X\n",
2980
+				ecc_error->msg, irq_value, val);
29902981 			queue_work(hisi_hba->wq, &hisi_hba->rst_work);
29912982 		}
29922983 	}
....@@ -3023,7 +3014,7 @@
30233014 	{ .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
30243015 	{ .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
30253016 	{ .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
3026
-	{},
3017
+	{}
30273018 };
30283019 
30293020 static const struct hisi_sas_hw_error fifo_error[] = {
....@@ -3032,7 +3023,7 @@
30323023 	{ .msk = BIT(10), .msg = "GETDQE_FIFO" },
30333024 	{ .msk = BIT(11), .msg = "CMDP_FIFO" },
30343025 	{ .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
3035
-	{},
3026
+	{}
30363027 };
30373028 
30383029 static const struct hisi_sas_hw_error fatal_axi_errors[] = {
....@@ -3096,12 +3087,12 @@
30963087 				if (!(err_value & sub->msk))
30973088 					continue;
30983089 				dev_err(dev, "%s (0x%x) found!\n",
3099
-					 sub->msg, irq_value);
3090
+					sub->msg, irq_value);
31003091 				queue_work(hisi_hba->wq, &hisi_hba->rst_work);
31013092 			}
31023093 		} else {
31033094 			dev_err(dev, "%s (0x%x) found!\n",
3104
-				 axi_error->msg, irq_value);
3095
+				axi_error->msg, irq_value);
31053096 			queue_work(hisi_hba->wq, &hisi_hba->rst_work);
31063097 		}
31073098 	}
....@@ -3122,9 +3113,9 @@
31223113 	return IRQ_HANDLED;
31233114 }
31243115 
3125
-static void cq_tasklet_v2_hw(unsigned long val)
3116
+static irqreturn_t  cq_thread_v2_hw(int irq_no, void *p)
31263117 {
3127
-	struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
3118
+	struct hisi_sas_cq *cq = p;
31283119 	struct hisi_hba *hisi_hba = cq->hisi_hba;
31293120 	struct hisi_sas_slot *slot;
31303121 	struct hisi_sas_itct *itct;
....@@ -3148,20 +3139,24 @@
31483139 
31493140 		/* Check for NCQ completion */
31503141 		if (complete_hdr->act) {
3151
-			u32 act_tmp = complete_hdr->act;
3142
+			u32 act_tmp = le32_to_cpu(complete_hdr->act);
31523143 			int ncq_tag_count = ffs(act_tmp);
3144
+			u32 dw1 = le32_to_cpu(complete_hdr->dw1);
31533145 
3154
-			dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
3146
+			dev_id = (dw1 & CMPLT_HDR_DEV_ID_MSK) >>
31553147 				 CMPLT_HDR_DEV_ID_OFF;
31563148 			itct = &hisi_hba->itct[dev_id];
31573149 
31583150 			/* The NCQ tags are held in the itct header */
31593151 			while (ncq_tag_count) {
3160
-				__le64 *ncq_tag = &itct->qw4_15[0];
3152
+				__le64 *_ncq_tag = &itct->qw4_15[0], __ncq_tag;
3153
+				u64 ncq_tag;
31613154 
3162
-				ncq_tag_count -= 1;
3163
-				iptt = (ncq_tag[ncq_tag_count / 5]
3164
-					>> (ncq_tag_count % 5) * 12) & 0xfff;
3155
+				ncq_tag_count--;
3156
+				__ncq_tag = _ncq_tag[ncq_tag_count / 5];
3157
+				ncq_tag = le64_to_cpu(__ncq_tag);
3158
+				iptt = (ncq_tag >> (ncq_tag_count % 5) * 12) &
3159
+				       0xfff;
31653160 
31663161 				slot = &hisi_hba->slot_info[iptt];
31673162 				slot->cmplt_queue_slot = rd_point;
....@@ -3172,7 +3167,9 @@
31723167 				ncq_tag_count = ffs(act_tmp);
31733168 			}
31743169 		} else {
3175
-			iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
3170
+			u32 dw1 = le32_to_cpu(complete_hdr->dw1);
3171
+
3172
+			iptt = dw1 & CMPLT_HDR_IPTT_MSK;
31763173 			slot = &hisi_hba->slot_info[iptt];
31773174 			slot->cmplt_queue_slot = rd_point;
31783175 			slot->cmplt_queue = queue;
....@@ -3186,6 +3183,8 @@
31863183 	/* update rd_point */
31873184 	cq->rd_point = rd_point;
31883185 	hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
3186
+
3187
+	return IRQ_HANDLED;
31893188 }
31903189 
31913190 static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
....@@ -3196,9 +3195,7 @@
31963195 
31973196 	hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
31983197 
3199
-	tasklet_schedule(&cq->tasklet);
3200
-
3201
-	return IRQ_HANDLED;
3198
+	return IRQ_WAKE_THREAD;
32023199 }
32033200 
32043201 static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
....@@ -3214,6 +3211,8 @@
32143211 	u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
32153212 	unsigned long flags;
32163213 	int phy_no, offset;
3214
+
3215
+	del_timer(&phy->timer);
32173216 
32183217 	phy_no = sas_phy->id;
32193218 	initial_fis = &hisi_hba->initial_fis[phy_no];
....@@ -3237,7 +3236,7 @@
32373236 	/* check ERR bit of Status Register */
32383237 	if (fis->status & ATA_ERR) {
32393238 		dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", phy_no,
3240
-				fis->status);
3239
+			 fis->status);
32413240 		hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
32423241 		res = IRQ_NONE;
32433242 		goto end;
....@@ -3309,7 +3308,7 @@
33093308 	fatal_axi_int_v2_hw
33103309 };
33113310 
3312
-/**
3311
+/*
33133312  * There is a limitation in the hip06 chipset that we need
33143313  * to map in all mbigen interrupts, even if they are not used.
33153314  */
....@@ -3317,8 +3316,8 @@
33173316 {
33183317 	struct platform_device *pdev = hisi_hba->platform_dev;
33193318 	struct device *dev = &pdev->dev;
3320
-	int irq, rc, irq_map[128];
3321
-	int i, phy_no, fatal_no, queue_no, k;
3319
+	int irq, rc = 0, irq_map[128];
3320
+	int i, phy_no, fatal_no, queue_no;
33223321 
33233322 	for (i = 0; i < 128; i++)
33243323 		irq_map[i] = platform_get_irq(pdev, i);
....@@ -3328,11 +3327,10 @@
33283327 		rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
33293328 				      DRV_NAME " phy", hisi_hba);
33303329 		if (rc) {
3331
-			dev_err(dev, "irq init: could not request "
3332
-				"phy interrupt %d, rc=%d\n",
3330
+			dev_err(dev, "irq init: could not request phy interrupt %d, rc=%d\n",
33333331 				irq, rc);
33343332 			rc = -ENOENT;
3335
-			goto free_phy_int_irqs;
3333
+			goto err_out;
33363334 		}
33373335 	}
33383336 
....@@ -3343,11 +3341,10 @@
33433341 		rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
33443342 				      DRV_NAME " sata", phy);
33453343 		if (rc) {
3346
-			dev_err(dev, "irq init: could not request "
3347
-				"sata interrupt %d, rc=%d\n",
3344
+			dev_err(dev, "irq init: could not request sata interrupt %d, rc=%d\n",
33483345 				irq, rc);
33493346 			rc = -ENOENT;
3350
-			goto free_sata_int_irqs;
3347
+			goto err_out;
33513348 		}
33523349 	}
33533350 
....@@ -3356,52 +3353,32 @@
33563353 		rc = devm_request_irq(dev, irq, fatal_interrupts[fatal_no], 0,
33573354 				      DRV_NAME " fatal", hisi_hba);
33583355 		if (rc) {
3359
-			dev_err(dev,
3360
-				"irq init: could not request fatal interrupt %d, rc=%d\n",
3356
+			dev_err(dev, "irq init: could not request fatal interrupt %d, rc=%d\n",
33613357 				irq, rc);
33623358 			rc = -ENOENT;
3363
-			goto free_fatal_int_irqs;
3359
+			goto err_out;
33643360 		}
33653361 	}
33663362 
33673363 	for (queue_no = 0; queue_no < hisi_hba->queue_count; queue_no++) {
33683364 		struct hisi_sas_cq *cq = &hisi_hba->cq[queue_no];
3369
-		struct tasklet_struct *t = &cq->tasklet;
33703365 
3371
-		irq = irq_map[queue_no + 96];
3372
-		rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0,
3373
-				      DRV_NAME " cq", cq);
3366
+		cq->irq_no = irq_map[queue_no + 96];
3367
+		rc = devm_request_threaded_irq(dev, cq->irq_no,
3368
+					       cq_interrupt_v2_hw,
3369
+					       cq_thread_v2_hw, IRQF_ONESHOT,
3370
+					       DRV_NAME " cq", cq);
33743371 		if (rc) {
3375
-			dev_err(dev,
3376
-				"irq init: could not request cq interrupt %d, rc=%d\n",
3372
+			dev_err(dev, "irq init: could not request cq interrupt %d, rc=%d\n",
33773373 				irq, rc);
33783374 			rc = -ENOENT;
3379
-			goto free_cq_int_irqs;
3375
+			goto err_out;
33803376 		}
3381
-		tasklet_init(t, cq_tasklet_v2_hw, (unsigned long)cq);
33823377 	}
33833378 
3384
-	return 0;
3379
+	hisi_hba->cq_nvecs = hisi_hba->queue_count;
33853380 
3386
-free_cq_int_irqs:
3387
-	for (k = 0; k < queue_no; k++) {
3388
-		struct hisi_sas_cq *cq = &hisi_hba->cq[k];
3389
-
3390
-		free_irq(irq_map[k + 96], cq);
3391
-		tasklet_kill(&cq->tasklet);
3392
-	}
3393
-free_fatal_int_irqs:
3394
-	for (k = 0; k < fatal_no; k++)
3395
-		free_irq(irq_map[k + 81], hisi_hba);
3396
-free_sata_int_irqs:
3397
-	for (k = 0; k < phy_no; k++) {
3398
-		struct hisi_sas_phy *phy = &hisi_hba->phy[k];
3399
-
3400
-		free_irq(irq_map[k + 72], phy);
3401
-	}
3402
-free_phy_int_irqs:
3403
-	for (k = 0; k < i; k++)
3404
-		free_irq(irq_map[k + 1], hisi_hba);
3381
+err_out:
34053382 	return rc;
34063383 }
34073384 
....@@ -3457,7 +3434,6 @@
34573434 
34583435 	interrupt_disable_v2_hw(hisi_hba);
34593436 	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
3460
-	hisi_sas_kill_tasklets(hisi_hba);
34613437 
34623438 	hisi_sas_stop_phys(hisi_hba);
34633439 
....@@ -3523,7 +3499,7 @@
35233499 		break;
35243500 	default:
35253501 		dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
3526
-				reg_type);
3502
+			reg_type);
35273503 		return -EINVAL;
35283504 	}
35293505 
....@@ -3545,30 +3521,45 @@
35453521 		msleep(delay_ms);
35463522 	}
35473523 
3524
+	if (time >= timeout_ms) {
3525
+		dev_dbg(dev, "Wait commands complete timeout!\n");
3526
+		return;
3527
+	}
3528
+
35483529 	dev_dbg(dev, "wait commands complete %dms\n", time);
3530
+
35493531 }
3532
+
3533
+static struct device_attribute *host_attrs_v2_hw[] = {
3534
+	&dev_attr_phy_event_threshold,
3535
+	NULL
3536
+};
35503537 
35513538 static struct scsi_host_template sht_v2_hw = {
35523539 	.name			= DRV_NAME,
3540
+	.proc_name		= DRV_NAME,
35533541 	.module			= THIS_MODULE,
35543542 	.queuecommand		= sas_queuecommand,
3543
+	.dma_need_drain		= ata_scsi_dma_need_drain,
35553544 	.target_alloc		= sas_target_alloc,
35563545 	.slave_configure	= hisi_sas_slave_configure,
35573546 	.scan_finished		= hisi_sas_scan_finished,
35583547 	.scan_start		= hisi_sas_scan_start,
35593548 	.change_queue_depth	= sas_change_queue_depth,
35603549 	.bios_param		= sas_bios_param,
3561
-	.can_queue		= 1,
35623550 	.this_id		= -1,
3563
-	.sg_tablesize		= SG_ALL,
3551
+	.sg_tablesize		= HISI_SAS_SGE_PAGE_CNT,
35643552 	.max_sectors		= SCSI_DEFAULT_MAX_SECTORS,
3565
-	.use_clustering		= ENABLE_CLUSTERING,
35663553 	.eh_device_reset_handler = sas_eh_device_reset_handler,
35673554 	.eh_target_reset_handler = sas_eh_target_reset_handler,
35683555 	.slave_alloc		= sas_slave_alloc,
35693556 	.target_destroy		= sas_target_destroy,
35703557 	.ioctl			= sas_ioctl,
3571
-	.shost_attrs		= host_attrs,
3558
+#ifdef CONFIG_COMPAT
3559
+	.compat_ioctl		= sas_ioctl,
3560
+#endif
3561
+	.shost_attrs		= host_attrs_v2_hw,
3562
+	.host_reset		= hisi_sas_host_reset,
35723563 };
35733564 
35743565 static const struct hisi_sas_hw hisi_sas_v2_hw = {
....@@ -3584,9 +3575,7 @@
35843575 	.prep_ssp = prep_ssp_v2_hw,
35853576 	.prep_stp = prep_ata_v2_hw,
35863577 	.prep_abort = prep_abort_v2_hw,
3587
-	.get_free_slot = get_free_slot_v2_hw,
35883578 	.start_delivery = start_delivery_v2_hw,
3589
-	.slot_complete = slot_complete_v2_hw,
35903579 	.phys_init = phys_init_v2_hw,
35913580 	.phy_start = start_phy_v2_hw,
35923581 	.phy_disable = disable_phy_v2_hw,
....@@ -3594,7 +3583,6 @@
35943583 	.get_events = phy_get_events_v2_hw,
35953584 	.phy_set_linkrate = phy_set_linkrate_v2_hw,
35963585 	.phy_get_max_linkrate = phy_get_max_linkrate_v2_hw,
3597
-	.max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
35983586 	.complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
35993587 	.soft_reset = soft_reset_v2_hw,
36003588 	.get_phys_state = get_phys_state_v2_hw,
....@@ -3622,11 +3610,6 @@
36223610 
36233611 static int hisi_sas_v2_remove(struct platform_device *pdev)
36243612 {
3625
-	struct sas_ha_struct *sha = platform_get_drvdata(pdev);
3626
-	struct hisi_hba *hisi_hba = sha->lldd_ha;
3627
-
3628
-	hisi_sas_kill_tasklets(hisi_hba);
3629
-
36303613 	return hisi_sas_remove(pdev);
36313614 }
36323615