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2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/pinctrl/tegra/pinctrl-tegra.h
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@@ -1,16 +1,8 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * Driver for the NVIDIA Tegra pinmux
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  *
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  * Copyright (c) 2011, NVIDIA CORPORATION.  All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms and conditions of the GNU General Public License,
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- * version 2, as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope it will be useful, but WITHOUT
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- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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- * more details.
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  */
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 #ifndef __PINMUX_TEGRA_H__
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@@ -25,6 +17,7 @@
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 	int nbanks;
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 	void __iomem **regs;
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+	u32 *backup_regs;
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 };
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 enum tegra_pinconf_param {
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@@ -104,7 +97,6 @@
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  * @tri_reg:		Tri-state register offset.
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  * @tri_bank:		Tri-state register bank.
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  * @tri_bit:		Tri-state register bit.
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- * @parked_bit:		Parked register bit. -1 if unsupported.
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  * @einput_bit:		Enable-input register bit.
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  * @odrain_bit:		Open-drain register bit.
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  * @lock_bit:		Lock register bit.
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@@ -115,7 +107,8 @@
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  *			drvup, slwr, slwf, and drvtype parameters.
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  * @drv_bank:		Drive fields register bank.
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  * @hsm_bit:		High Speed Mode register bit.
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- * @schmitt_bit:	Scmitt register bit.
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+ * @sfsel_bit:		GPIO/SFIO selection register bit.
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+ * @schmitt_bit:	Schmitt register bit.
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  * @lpmd_bit:		Low Power Mode register bit.
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  * @drvdn_bit:		Drive Down register bit.
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  * @drvdn_width:	Drive Down field width.
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@@ -126,6 +119,7 @@
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  * @slwf_bit:		Slew Falling register bit.
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  * @slwf_width:		Slew Falling field width.
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  * @drvtype_bit:	Drive type register bit.
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+ * @parked_bitmask:	Parked register mask. 0 if unsupported.
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  *
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  * -1 in a *_reg field means that feature is unsupported for this group.
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  * *_bank and *_reg values are irrelevant when *_reg is -1.
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@@ -143,10 +137,10 @@
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 	const unsigned *pins;
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 	u8 npins;
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 	u8 funcs[4];
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-	s16 mux_reg;
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-	s16 pupd_reg;
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-	s16 tri_reg;
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-	s16 drv_reg;
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+	s32 mux_reg;
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+	s32 pupd_reg;
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+	s32 tri_reg;
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+	s32 drv_reg;
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 	u32 mux_bank:2;
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 	u32 pupd_bank:2;
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 	u32 tri_bank:2;
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@@ -154,13 +148,13 @@
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 	s32 mux_bit:6;
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 	s32 pupd_bit:6;
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 	s32 tri_bit:6;
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-	s32 parked_bit:6;
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 	s32 einput_bit:6;
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 	s32 odrain_bit:6;
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 	s32 lock_bit:6;
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 	s32 ioreset_bit:6;
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 	s32 rcv_sel_bit:6;
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 	s32 hsm_bit:6;
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+	s32 sfsel_bit:6;
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 	s32 schmitt_bit:6;
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 	s32 lpmd_bit:6;
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 	s32 drvdn_bit:6;
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@@ -172,6 +166,7 @@
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 	s32 drvup_width:6;
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 	s32 slwr_width:6;
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 	s32 slwf_width:6;
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+	u32 parked_bitmask;
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 };
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 /**
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 	bool hsm_in_mux;
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 	bool schmitt_in_mux;
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 	bool drvtype_in_mux;
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+	bool sfsel_in_mux;
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 };
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+extern const struct dev_pm_ops tegra_pinctrl_pm;
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+
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 int tegra_pinctrl_probe(struct platform_device *pdev,
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 			const struct tegra_pinctrl_soc_data *soc_data);
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 #endif