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2024-01-04 1543e317f1da31b75942316931e8f491a8920811 
 kernel/drivers/pinctrl/intel/pinctrl-cherryview.c
....@@ -2,7 +2,7 @@
22 /*
33  * Cherryview/Braswell pinctrl driver
44  *
5
- * Copyright (C) 2014, Intel Corporation
5
+ * Copyright (C) 2014, 2020 Intel Corporation
66  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
77  *
88  * This driver is based on the original Cherryview GPIO driver by
....@@ -10,19 +10,20 @@
1010  *   Alan Cox <alan@linux.intel.com>
1111  */
1212 
13
+#include <linux/acpi.h>
1314 #include <linux/dmi.h>
15
+#include <linux/gpio/driver.h>
1416 #include <linux/kernel.h>
1517 #include <linux/module.h>
16
-#include <linux/init.h>
18
+#include <linux/platform_device.h>
1719 #include <linux/types.h>
18
-#include <linux/gpio.h>
19
-#include <linux/gpio/driver.h>
20
-#include <linux/acpi.h>
20
+
2121 #include <linux/pinctrl/pinctrl.h>
2222 #include <linux/pinctrl/pinmux.h>
2323 #include <linux/pinctrl/pinconf.h>
2424 #include <linux/pinctrl/pinconf-generic.h>
25
-#include <linux/platform_device.h>
25
+
26
+#include "pinctrl-intel.h"
2627 
2728 #define CHV_INTSTAT			0x300
2829 #define CHV_INTMASK			0x380
....@@ -34,18 +35,18 @@
3435 
3536 #define CHV_PADCTRL0			0x000
3637 #define CHV_PADCTRL0_INTSEL_SHIFT	28
37
-#define CHV_PADCTRL0_INTSEL_MASK	(0xf << CHV_PADCTRL0_INTSEL_SHIFT)
38
+#define CHV_PADCTRL0_INTSEL_MASK	GENMASK(31, 28)
3839 #define CHV_PADCTRL0_TERM_UP		BIT(23)
3940 #define CHV_PADCTRL0_TERM_SHIFT		20
40
-#define CHV_PADCTRL0_TERM_MASK		(7 << CHV_PADCTRL0_TERM_SHIFT)
41
+#define CHV_PADCTRL0_TERM_MASK		GENMASK(22, 20)
4142 #define CHV_PADCTRL0_TERM_20K		1
4243 #define CHV_PADCTRL0_TERM_5K		2
4344 #define CHV_PADCTRL0_TERM_1K		4
4445 #define CHV_PADCTRL0_PMODE_SHIFT	16
45
-#define CHV_PADCTRL0_PMODE_MASK		(0xf << CHV_PADCTRL0_PMODE_SHIFT)
46
+#define CHV_PADCTRL0_PMODE_MASK		GENMASK(19, 16)
4647 #define CHV_PADCTRL0_GPIOEN		BIT(15)
4748 #define CHV_PADCTRL0_GPIOCFG_SHIFT	8
48
-#define CHV_PADCTRL0_GPIOCFG_MASK	(7 << CHV_PADCTRL0_GPIOCFG_SHIFT)
49
+#define CHV_PADCTRL0_GPIOCFG_MASK	GENMASK(10, 8)
4950 #define CHV_PADCTRL0_GPIOCFG_GPIO	0
5051 #define CHV_PADCTRL0_GPIOCFG_GPO	1
5152 #define CHV_PADCTRL0_GPIOCFG_GPI	2
....@@ -56,167 +57,48 @@
5657 #define CHV_PADCTRL1			0x004
5758 #define CHV_PADCTRL1_CFGLOCK		BIT(31)
5859 #define CHV_PADCTRL1_INVRXTX_SHIFT	4
59
-#define CHV_PADCTRL1_INVRXTX_MASK	(0xf << CHV_PADCTRL1_INVRXTX_SHIFT)
60
-#define CHV_PADCTRL1_INVRXTX_TXENABLE	(2 << CHV_PADCTRL1_INVRXTX_SHIFT)
60
+#define CHV_PADCTRL1_INVRXTX_MASK	GENMASK(7, 4)
61
+#define CHV_PADCTRL1_INVRXTX_TXDATA	BIT(7)
62
+#define CHV_PADCTRL1_INVRXTX_RXDATA	BIT(6)
63
+#define CHV_PADCTRL1_INVRXTX_TXENABLE	BIT(5)
6164 #define CHV_PADCTRL1_ODEN		BIT(3)
62
-#define CHV_PADCTRL1_INVRXTX_RXDATA	(4 << CHV_PADCTRL1_INVRXTX_SHIFT)
63
-#define CHV_PADCTRL1_INTWAKECFG_MASK	7
65
+#define CHV_PADCTRL1_INTWAKECFG_MASK	GENMASK(2, 0)
6466 #define CHV_PADCTRL1_INTWAKECFG_FALLING	1
6567 #define CHV_PADCTRL1_INTWAKECFG_RISING	2
6668 #define CHV_PADCTRL1_INTWAKECFG_BOTH	3
6769 #define CHV_PADCTRL1_INTWAKECFG_LEVEL	4
6870 
69
-/**
70
- * struct chv_alternate_function - A per group or per pin alternate function
71
- * @pin: Pin number (only used in per pin configs)
72
- * @mode: Mode the pin should be set in
73
- * @invert_oe: Invert OE for this pin
74
- */
75
-struct chv_alternate_function {
76
-	unsigned pin;
77
-	u8 mode;
78
-	bool invert_oe;
79
-};
80
-
81
-/**
82
- * struct chv_pincgroup - describes a CHV pin group
83
- * @name: Name of the group
84
- * @pins: An array of pins in this group
85
- * @npins: Number of pins in this group
86
- * @altfunc: Alternate function applied to all pins in this group
87
- * @overrides: Alternate function override per pin or %NULL if not used
88
- * @noverrides: Number of per pin alternate function overrides if
89
- *              @overrides != NULL.
90
- */
91
-struct chv_pingroup {
92
-	const char *name;
93
-	const unsigned *pins;
94
-	size_t npins;
95
-	struct chv_alternate_function altfunc;
96
-	const struct chv_alternate_function *overrides;
97
-	size_t noverrides;
98
-};
99
-
100
-/**
101
- * struct chv_function - A CHV pinmux function
102
- * @name: Name of the function
103
- * @groups: An array of groups for this function
104
- * @ngroups: Number of groups in @groups
105
- */
106
-struct chv_function {
107
-	const char *name;
108
-	const char * const *groups;
109
-	size_t ngroups;
110
-};
111
-
112
-/**
113
- * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs
114
- * @base: Start pin number
115
- * @npins: Number of pins in this range
116
- */
117
-struct chv_gpio_pinrange {
118
-	unsigned base;
119
-	unsigned npins;
120
-};
121
-
122
-/**
123
- * struct chv_community - A community specific configuration
124
- * @uid: ACPI _UID used to match the community
125
- * @pins: All pins in this community
126
- * @npins: Number of pins
127
- * @groups: All groups in this community
128
- * @ngroups: Number of groups
129
- * @functions: All functions in this community
130
- * @nfunctions: Number of functions
131
- * @gpio_ranges: An array of GPIO ranges in this community
132
- * @ngpio_ranges: Number of GPIO ranges
133
- * @nirqs: Total number of IRQs this community can generate
134
- */
135
-struct chv_community {
136
-	const char *uid;
137
-	const struct pinctrl_pin_desc *pins;
138
-	size_t npins;
139
-	const struct chv_pingroup *groups;
140
-	size_t ngroups;
141
-	const struct chv_function *functions;
142
-	size_t nfunctions;
143
-	const struct chv_gpio_pinrange *gpio_ranges;
144
-	size_t ngpio_ranges;
145
-	size_t nirqs;
146
-	acpi_adr_space_type acpi_space_id;
147
-};
148
-
149
-struct chv_pin_context {
71
+struct intel_pad_context {
15072 	u32 padctrl0;
15173 	u32 padctrl1;
15274 };
15375 
15476 /**
155
- * struct chv_pinctrl - CHV pinctrl private structure
156
- * @dev: Pointer to the parent device
157
- * @pctldesc: Pin controller description
158
- * @pctldev: Pointer to the pin controller device
159
- * @chip: GPIO chip in this pin controller
160
- * @irqchip: IRQ chip in this pin controller
161
- * @regs: MMIO registers
162
- * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO
163
- *		offset (in GPIO number space)
164
- * @community: Community this pinctrl instance represents
165
- *
166
- * The first group in @groups is expected to contain all pins that can be
167
- * used as GPIOs.
77
+ * struct intel_community_context - community context for Cherryview
78
+ * @intr_lines: Mapping between 16 HW interrupt wires and GPIO offset (in GPIO number space)
79
+ * @saved_intmask: Interrupt mask saved for system sleep
16880  */
169
-struct chv_pinctrl {
170
-	struct device *dev;
171
-	struct pinctrl_desc pctldesc;
172
-	struct pinctrl_dev *pctldev;
173
-	struct gpio_chip chip;
174
-	struct irq_chip irqchip;
175
-	void __iomem *regs;
176
-	unsigned intr_lines[16];
177
-	const struct chv_community *community;
81
+struct intel_community_context {
82
+	unsigned int intr_lines[16];
17883 	u32 saved_intmask;
179
-	struct chv_pin_context *saved_pin_context;
18084 };
18185 
182
-#define ALTERNATE_FUNCTION(p, m, i)		\
183
-	{					\
184
-		.pin = (p),			\
185
-		.mode = (m),			\
186
-		.invert_oe = (i),		\
187
-	}
86
+#define	PINMODE_INVERT_OE	BIT(15)
18887 
189
-#define PIN_GROUP(n, p, m, i)			\
190
-	{					\
191
-		.name = (n),			\
192
-		.pins = (p),			\
193
-		.npins = ARRAY_SIZE((p)),	\
194
-		.altfunc.mode = (m),		\
195
-		.altfunc.invert_oe = (i),	\
196
-	}
88
+#define PINMODE(m, i)		((m) | ((i) * PINMODE_INVERT_OE))
19789 
198
-#define PIN_GROUP_WITH_OVERRIDE(n, p, m, i, o)	\
199
-	{					\
200
-		.name = (n),			\
201
-		.pins = (p),			\
202
-		.npins = ARRAY_SIZE((p)),	\
203
-		.altfunc.mode = (m),		\
204
-		.altfunc.invert_oe = (i),	\
205
-		.overrides = (o),		\
206
-		.noverrides = ARRAY_SIZE((o)),	\
207
-	}
208
-
209
-#define FUNCTION(n, g)				\
210
-	{					\
211
-		.name = (n),			\
212
-		.groups = (g),			\
213
-		.ngroups = ARRAY_SIZE((g)),	\
214
-	}
215
-
216
-#define GPIO_PINRANGE(start, end)		\
90
+#define CHV_GPP(start, end)			\
21791 	{					\
21892 		.base = (start),		\
219
-		.npins = (end) - (start) + 1,	\
93
+		.size = (end) - (start) + 1,	\
94
+	}
95
+
96
+#define CHV_COMMUNITY(g, i, a)			\
97
+	{					\
98
+		.gpps = (g),			\
99
+		.ngpps = ARRAY_SIZE(g),		\
100
+		.nirqs = (i),			\
101
+		.acpi_space_id = (a),		\
220102 	}
221103 
222104 static const struct pinctrl_pin_desc southwest_pins[] = {
....@@ -284,7 +166,6 @@
284166 	PINCTRL_PIN(97, "GP_SSP_2_TXD"),
285167 };
286168 
287
-static const unsigned southwest_fspi_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
288169 static const unsigned southwest_uart0_pins[] = { 16, 20 };
289170 static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 };
290171 static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 };
....@@ -300,43 +181,39 @@
300181 static const unsigned southwest_i2c5_pins[] = { 45, 48 };
301182 static const unsigned southwest_i2c6_pins[] = { 47, 51 };
302183 static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 };
303
-static const unsigned southwest_smbus_pins[] = { 79, 81, 82 };
304184 static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 };
305185 
306
-/* LPE I2S TXD pins need to have invert_oe set */
307
-static const struct chv_alternate_function southwest_lpe_altfuncs[] = {
308
-	ALTERNATE_FUNCTION(30, 1, true),
309
-	ALTERNATE_FUNCTION(34, 1, true),
310
-	ALTERNATE_FUNCTION(97, 1, true),
186
+/* Some of LPE I2S TXD pins need to have OE inversion set */
187
+static const unsigned int southwest_lpe_altfuncs[] = {
188
+	PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 30, 31, 32, 33 */
189
+	PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 34, 35, 36, 37 */
190
+	PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 1), /* 92, 94, 96, 97 */
311191 };
312192 
313193 /*
314194  * Two spi3 chipselects are available in different mode than the main spi3
315
- * functionality, which is using mode 1.
195
+ * functionality, which is using mode 2.
316196  */
317
-static const struct chv_alternate_function southwest_spi3_altfuncs[] = {
318
-	ALTERNATE_FUNCTION(76, 3, false),
319
-	ALTERNATE_FUNCTION(80, 3, false),
197
+static const unsigned int southwest_spi3_altfuncs[] = {
198
+	PINMODE(3, 0), PINMODE(2, 0), PINMODE(3, 0), PINMODE(2, 0), /* 76, 79, 80, 81 */
199
+	PINMODE(2, 0),						    /* 82 */
320200 };
321201 
322
-static const struct chv_pingroup southwest_groups[] = {
323
-	PIN_GROUP("uart0_grp", southwest_uart0_pins, 2, false),
324
-	PIN_GROUP("uart1_grp", southwest_uart1_pins, 1, false),
325
-	PIN_GROUP("uart2_grp", southwest_uart2_pins, 1, false),
326
-	PIN_GROUP("hda_grp", southwest_hda_pins, 2, false),
327
-	PIN_GROUP("i2c0_grp", southwest_i2c0_pins, 1, true),
328
-	PIN_GROUP("i2c1_grp", southwest_i2c1_pins, 1, true),
329
-	PIN_GROUP("i2c2_grp", southwest_i2c2_pins, 1, true),
330
-	PIN_GROUP("i2c3_grp", southwest_i2c3_pins, 1, true),
331
-	PIN_GROUP("i2c4_grp", southwest_i2c4_pins, 1, true),
332
-	PIN_GROUP("i2c5_grp", southwest_i2c5_pins, 1, true),
333
-	PIN_GROUP("i2c6_grp", southwest_i2c6_pins, 1, true),
334
-	PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true),
335
-
336
-	PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins, 1, false,
337
-				southwest_lpe_altfuncs),
338
-	PIN_GROUP_WITH_OVERRIDE("spi3_grp", southwest_spi3_pins, 2, false,
339
-				southwest_spi3_altfuncs),
202
+static const struct intel_pingroup southwest_groups[] = {
203
+	PIN_GROUP("uart0_grp", southwest_uart0_pins, PINMODE(2, 0)),
204
+	PIN_GROUP("uart1_grp", southwest_uart1_pins, PINMODE(1, 0)),
205
+	PIN_GROUP("uart2_grp", southwest_uart2_pins, PINMODE(1, 0)),
206
+	PIN_GROUP("hda_grp", southwest_hda_pins, PINMODE(2, 0)),
207
+	PIN_GROUP("i2c0_grp", southwest_i2c0_pins, PINMODE(1, 1)),
208
+	PIN_GROUP("i2c1_grp", southwest_i2c1_pins, PINMODE(1, 1)),
209
+	PIN_GROUP("i2c2_grp", southwest_i2c2_pins, PINMODE(1, 1)),
210
+	PIN_GROUP("i2c3_grp", southwest_i2c3_pins, PINMODE(1, 1)),
211
+	PIN_GROUP("i2c4_grp", southwest_i2c4_pins, PINMODE(1, 1)),
212
+	PIN_GROUP("i2c5_grp", southwest_i2c5_pins, PINMODE(1, 1)),
213
+	PIN_GROUP("i2c6_grp", southwest_i2c6_pins, PINMODE(1, 1)),
214
+	PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, PINMODE(2, 1)),
215
+	PIN_GROUP("lpe_grp", southwest_lpe_pins, southwest_lpe_altfuncs),
216
+	PIN_GROUP("spi3_grp", southwest_spi3_pins, southwest_spi3_altfuncs),
340217 };
341218 
342219 static const char * const southwest_uart0_groups[] = { "uart0_grp" };
....@@ -358,7 +235,7 @@
358235  * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are
359236  * enabled only as GPIOs.
360237  */
361
-static const struct chv_function southwest_functions[] = {
238
+static const struct intel_function southwest_functions[] = {
362239 	FUNCTION("uart0", southwest_uart0_groups),
363240 	FUNCTION("uart1", southwest_uart1_groups),
364241 	FUNCTION("uart2", southwest_uart2_groups),
....@@ -375,17 +252,25 @@
375252 	FUNCTION("spi3", southwest_spi3_groups),
376253 };
377254 
378
-static const struct chv_gpio_pinrange southwest_gpio_ranges[] = {
379
-	GPIO_PINRANGE(0, 7),
380
-	GPIO_PINRANGE(15, 22),
381
-	GPIO_PINRANGE(30, 37),
382
-	GPIO_PINRANGE(45, 52),
383
-	GPIO_PINRANGE(60, 67),
384
-	GPIO_PINRANGE(75, 82),
385
-	GPIO_PINRANGE(90, 97),
255
+static const struct intel_padgroup southwest_gpps[] = {
256
+	CHV_GPP(0, 7),
257
+	CHV_GPP(15, 22),
258
+	CHV_GPP(30, 37),
259
+	CHV_GPP(45, 52),
260
+	CHV_GPP(60, 67),
261
+	CHV_GPP(75, 82),
262
+	CHV_GPP(90, 97),
386263 };
387264 
388
-static const struct chv_community southwest_community = {
265
+/*
266
+ * Southwest community can generate GPIO interrupts only for the first 8
267
+ * interrupts. The upper half (8-15) can only be used to trigger GPEs.
268
+ */
269
+static const struct intel_community southwest_communities[] = {
270
+	CHV_COMMUNITY(southwest_gpps, 8, 0x91),
271
+};
272
+
273
+static const struct intel_pinctrl_soc_data southwest_soc_data = {
389274 	.uid = "1",
390275 	.pins = southwest_pins,
391276 	.npins = ARRAY_SIZE(southwest_pins),
....@@ -393,15 +278,8 @@
393278 	.ngroups = ARRAY_SIZE(southwest_groups),
394279 	.functions = southwest_functions,
395280 	.nfunctions = ARRAY_SIZE(southwest_functions),
396
-	.gpio_ranges = southwest_gpio_ranges,
397
-	.ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges),
398
-	/*
399
-	 * Southwest community can benerate GPIO interrupts only for the
400
-	 * first 8 interrupts. The upper half (8-15) can only be used to
401
-	 * trigger GPEs.
402
-	 */
403
-	.nirqs = 8,
404
-	.acpi_space_id = 0x91,
281
+	.communities = southwest_communities,
282
+	.ncommunities = ARRAY_SIZE(southwest_communities),
405283 };
406284 
407285 static const struct pinctrl_pin_desc north_pins[] = {
....@@ -470,27 +348,28 @@
470348 	PINCTRL_PIN(72, "PANEL0_VDDEN"),
471349 };
472350 
473
-static const struct chv_gpio_pinrange north_gpio_ranges[] = {
474
-	GPIO_PINRANGE(0, 8),
475
-	GPIO_PINRANGE(15, 27),
476
-	GPIO_PINRANGE(30, 41),
477
-	GPIO_PINRANGE(45, 56),
478
-	GPIO_PINRANGE(60, 72),
351
+static const struct intel_padgroup north_gpps[] = {
352
+	CHV_GPP(0, 8),
353
+	CHV_GPP(15, 27),
354
+	CHV_GPP(30, 41),
355
+	CHV_GPP(45, 56),
356
+	CHV_GPP(60, 72),
479357 };
480358 
481
-static const struct chv_community north_community = {
359
+/*
360
+ * North community can generate GPIO interrupts only for the first 8
361
+ * interrupts. The upper half (8-15) can only be used to trigger GPEs.
362
+ */
363
+static const struct intel_community north_communities[] = {
364
+	CHV_COMMUNITY(north_gpps, 8, 0x92),
365
+};
366
+
367
+static const struct intel_pinctrl_soc_data north_soc_data = {
482368 	.uid = "2",
483369 	.pins = north_pins,
484370 	.npins = ARRAY_SIZE(north_pins),
485
-	.gpio_ranges = north_gpio_ranges,
486
-	.ngpio_ranges = ARRAY_SIZE(north_gpio_ranges),
487
-	/*
488
-	 * North community can generate GPIO interrupts only for the first
489
-	 * 8 interrupts. The upper half (8-15) can only be used to trigger
490
-	 * GPEs.
491
-	 */
492
-	.nirqs = 8,
493
-	.acpi_space_id = 0x92,
371
+	.communities = north_communities,
372
+	.ncommunities = ARRAY_SIZE(north_communities),
494373 };
495374 
496375 static const struct pinctrl_pin_desc east_pins[] = {
....@@ -521,19 +400,21 @@
521400 	PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"),
522401 };
523402 
524
-static const struct chv_gpio_pinrange east_gpio_ranges[] = {
525
-	GPIO_PINRANGE(0, 11),
526
-	GPIO_PINRANGE(15, 26),
403
+static const struct intel_padgroup east_gpps[] = {
404
+	CHV_GPP(0, 11),
405
+	CHV_GPP(15, 26),
527406 };
528407 
529
-static const struct chv_community east_community = {
408
+static const struct intel_community east_communities[] = {
409
+	CHV_COMMUNITY(east_gpps, 16, 0x93),
410
+};
411
+
412
+static const struct intel_pinctrl_soc_data east_soc_data = {
530413 	.uid = "3",
531414 	.pins = east_pins,
532415 	.npins = ARRAY_SIZE(east_pins),
533
-	.gpio_ranges = east_gpio_ranges,
534
-	.ngpio_ranges = ARRAY_SIZE(east_gpio_ranges),
535
-	.nirqs = 16,
536
-	.acpi_space_id = 0x93,
416
+	.communities = east_communities,
417
+	.ncommunities = ARRAY_SIZE(east_communities),
537418 };
538419 
539420 static const struct pinctrl_pin_desc southeast_pins[] = {
....@@ -611,14 +492,14 @@
611492 static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 };
612493 static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 };
613494 
614
-static const struct chv_pingroup southeast_groups[] = {
615
-	PIN_GROUP("pwm0_grp", southeast_pwm0_pins, 1, false),
616
-	PIN_GROUP("pwm1_grp", southeast_pwm1_pins, 1, false),
617
-	PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, 1, false),
618
-	PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, 1, false),
619
-	PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, 1, false),
620
-	PIN_GROUP("spi1_grp", southeast_spi1_pins, 1, false),
621
-	PIN_GROUP("spi2_grp", southeast_spi2_pins, 4, false),
495
+static const struct intel_pingroup southeast_groups[] = {
496
+	PIN_GROUP("pwm0_grp", southeast_pwm0_pins, PINMODE(1, 0)),
497
+	PIN_GROUP("pwm1_grp", southeast_pwm1_pins, PINMODE(1, 0)),
498
+	PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, PINMODE(1, 0)),
499
+	PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, PINMODE(1, 0)),
500
+	PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, PINMODE(1, 0)),
501
+	PIN_GROUP("spi1_grp", southeast_spi1_pins, PINMODE(1, 0)),
502
+	PIN_GROUP("spi2_grp", southeast_spi2_pins, PINMODE(4, 0)),
622503 };
623504 
624505 static const char * const southeast_pwm0_groups[] = { "pwm0_grp" };
....@@ -629,7 +510,7 @@
629510 static const char * const southeast_spi1_groups[] = { "spi1_grp" };
630511 static const char * const southeast_spi2_groups[] = { "spi2_grp" };
631512 
632
-static const struct chv_function southeast_functions[] = {
513
+static const struct intel_function southeast_functions[] = {
633514 	FUNCTION("pwm0", southeast_pwm0_groups),
634515 	FUNCTION("pwm1", southeast_pwm1_groups),
635516 	FUNCTION("sdmmc1", southeast_sdmmc1_groups),
....@@ -639,16 +520,20 @@
639520 	FUNCTION("spi2", southeast_spi2_groups),
640521 };
641522 
642
-static const struct chv_gpio_pinrange southeast_gpio_ranges[] = {
643
-	GPIO_PINRANGE(0, 7),
644
-	GPIO_PINRANGE(15, 26),
645
-	GPIO_PINRANGE(30, 35),
646
-	GPIO_PINRANGE(45, 52),
647
-	GPIO_PINRANGE(60, 69),
648
-	GPIO_PINRANGE(75, 85),
523
+static const struct intel_padgroup southeast_gpps[] = {
524
+	CHV_GPP(0, 7),
525
+	CHV_GPP(15, 26),
526
+	CHV_GPP(30, 35),
527
+	CHV_GPP(45, 52),
528
+	CHV_GPP(60, 69),
529
+	CHV_GPP(75, 85),
649530 };
650531 
651
-static const struct chv_community southeast_community = {
532
+static const struct intel_community southeast_communities[] = {
533
+	CHV_COMMUNITY(southeast_gpps, 16, 0x94),
534
+};
535
+
536
+static const struct intel_pinctrl_soc_data southeast_soc_data = {
652537 	.uid = "4",
653538 	.pins = southeast_pins,
654539 	.npins = ARRAY_SIZE(southeast_pins),
....@@ -656,17 +541,16 @@
656541 	.ngroups = ARRAY_SIZE(southeast_groups),
657542 	.functions = southeast_functions,
658543 	.nfunctions = ARRAY_SIZE(southeast_functions),
659
-	.gpio_ranges = southeast_gpio_ranges,
660
-	.ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges),
661
-	.nirqs = 16,
662
-	.acpi_space_id = 0x94,
544
+	.communities = southeast_communities,
545
+	.ncommunities = ARRAY_SIZE(southeast_communities),
663546 };
664547 
665
-static const struct chv_community *chv_communities[] = {
666
-	&southwest_community,
667
-	&north_community,
668
-	&east_community,
669
-	&southeast_community,
548
+static const struct intel_pinctrl_soc_data *chv_soc_data[] = {
549
+	&southwest_soc_data,
550
+	&north_soc_data,
551
+	&east_soc_data,
552
+	&southeast_soc_data,
553
+	NULL
670554 };
671555 
672556 /*
....@@ -680,71 +564,92 @@
680564  */
681565 static DEFINE_RAW_SPINLOCK(chv_lock);
682566 
683
-static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned offset,
684
-				unsigned reg)
567
+static u32 chv_pctrl_readl(struct intel_pinctrl *pctrl, unsigned int offset)
685568 {
686
-	unsigned family_no = offset / MAX_FAMILY_PAD_GPIO_NO;
687
-	unsigned pad_no = offset % MAX_FAMILY_PAD_GPIO_NO;
569
+	const struct intel_community *community = &pctrl->communities[0];
688570 
689
-	offset = FAMILY_PAD_REGS_OFF + FAMILY_PAD_REGS_SIZE * family_no +
690
-		 GPIO_REGS_SIZE * pad_no;
691
-
692
-	return pctrl->regs + offset + reg;
571
+	return readl(community->regs + offset);
693572 }
694573 
695
-static void chv_writel(u32 value, void __iomem *reg)
574
+static void chv_pctrl_writel(struct intel_pinctrl *pctrl, unsigned int offset, u32 value)
696575 {
576
+	const struct intel_community *community = &pctrl->communities[0];
577
+	void __iomem *reg = community->regs + offset;
578
+
579
+	/* Write and simple read back to confirm the bus transferring done */
697580 	writel(value, reg);
698
-	/* simple readback to confirm the bus transferring done */
581
+	readl(reg);
582
+}
583
+
584
+static void __iomem *chv_padreg(struct intel_pinctrl *pctrl, unsigned int offset,
585
+				unsigned int reg)
586
+{
587
+	const struct intel_community *community = &pctrl->communities[0];
588
+	unsigned int family_no = offset / MAX_FAMILY_PAD_GPIO_NO;
589
+	unsigned int pad_no = offset % MAX_FAMILY_PAD_GPIO_NO;
590
+
591
+	offset = FAMILY_PAD_REGS_SIZE * family_no + GPIO_REGS_SIZE * pad_no;
592
+
593
+	return community->pad_regs + offset + reg;
594
+}
595
+
596
+static u32 chv_readl(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset)
597
+{
598
+	return readl(chv_padreg(pctrl, pin, offset));
599
+}
600
+
601
+static void chv_writel(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset, u32 value)
602
+{
603
+	void __iomem *reg = chv_padreg(pctrl, pin, offset);
604
+
605
+	/* Write and simple read back to confirm the bus transferring done */
606
+	writel(value, reg);
699607 	readl(reg);
700608 }
701609 
702610 /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
703
-static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned offset)
611
+static bool chv_pad_locked(struct intel_pinctrl *pctrl, unsigned int offset)
704612 {
705
-	void __iomem *reg;
706
-
707
-	reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
708
-	return readl(reg) & CHV_PADCTRL1_CFGLOCK;
613
+	return chv_readl(pctrl, offset, CHV_PADCTRL1) & CHV_PADCTRL1_CFGLOCK;
709614 }
710615 
711616 static int chv_get_groups_count(struct pinctrl_dev *pctldev)
712617 {
713
-	struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
618
+	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
714619 
715
-	return pctrl->community->ngroups;
620
+	return pctrl->soc->ngroups;
716621 }
717622 
718623 static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
719
-				      unsigned group)
624
+				      unsigned int group)
720625 {
721
-	struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
626
+	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
722627 
723
-	return pctrl->community->groups[group].name;
628
+	return pctrl->soc->groups[group].name;
724629 }
725630 
726
-static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
727
-			      const unsigned **pins, unsigned *npins)
631
+static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
632
+			      const unsigned int **pins, unsigned int *npins)
728633 {
729
-	struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
634
+	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
730635 
731
-	*pins = pctrl->community->groups[group].pins;
732
-	*npins = pctrl->community->groups[group].npins;
636
+	*pins = pctrl->soc->groups[group].pins;
637
+	*npins = pctrl->soc->groups[group].npins;
733638 	return 0;
734639 }
735640 
736641 static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
737
-			     unsigned offset)
642
+			     unsigned int offset)
738643 {
739
-	struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
644
+	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
740645 	unsigned long flags;
741646 	u32 ctrl0, ctrl1;
742647 	bool locked;
743648 
744649 	raw_spin_lock_irqsave(&chv_lock, flags);
745650 
746
-	ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
747
-	ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1));
651
+	ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
652
+	ctrl1 = chv_readl(pctrl, offset, CHV_PADCTRL1);
748653 	locked = chv_pad_locked(pctrl, offset);
749654 
750655 	raw_spin_unlock_irqrestore(&chv_lock, flags);
....@@ -775,40 +680,40 @@
775680 
776681 static int chv_get_functions_count(struct pinctrl_dev *pctldev)
777682 {
778
-	struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
683
+	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
779684 
780
-	return pctrl->community->nfunctions;
685
+	return pctrl->soc->nfunctions;
781686 }
782687 
783688 static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
784
-					 unsigned function)
689
+					 unsigned int function)
785690 {
786
-	struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
691
+	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
787692 
788
-	return pctrl->community->functions[function].name;
693
+	return pctrl->soc->functions[function].name;
789694 }
790695 
791696 static int chv_get_function_groups(struct pinctrl_dev *pctldev,
792
-				   unsigned function,
697
+				   unsigned int function,
793698 				   const char * const **groups,
794
-				   unsigned * const ngroups)
699
+				   unsigned int * const ngroups)
795700 {
796
-	struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
701
+	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
797702 
798
-	*groups = pctrl->community->functions[function].groups;
799
-	*ngroups = pctrl->community->functions[function].ngroups;
703
+	*groups = pctrl->soc->functions[function].groups;
704
+	*ngroups = pctrl->soc->functions[function].ngroups;
800705 	return 0;
801706 }
802707 
803
-static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
804
-			      unsigned group)
708
+static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
709
+			      unsigned int function, unsigned int group)
805710 {
806
-	struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
807
-	const struct chv_pingroup *grp;
711
+	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
712
+	const struct intel_pingroup *grp;
808713 	unsigned long flags;
809714 	int i;
810715 
811
-	grp = &pctrl->community->groups[group];
716
+	grp = &pctrl->soc->groups[group];
812717 
813718 	raw_spin_lock_irqsave(&chv_lock, flags);
814719 
....@@ -823,41 +728,37 @@
823728 	}
824729 
825730 	for (i = 0; i < grp->npins; i++) {
826
-		const struct chv_alternate_function *altfunc = &grp->altfunc;
827731 		int pin = grp->pins[i];
828
-		void __iomem *reg;
732
+		unsigned int mode;
733
+		bool invert_oe;
829734 		u32 value;
830735 
831736 		/* Check if there is pin-specific config */
832
-		if (grp->overrides) {
833
-			int j;
737
+		if (grp->modes)
738
+			mode = grp->modes[i];
739
+		else
740
+			mode = grp->mode;
834741 
835
-			for (j = 0; j < grp->noverrides; j++) {
836
-				if (grp->overrides[j].pin == pin) {
837
-					altfunc = &grp->overrides[j];
838
-					break;
839
-				}
840
-			}
841
-		}
742
+		/* Extract OE inversion */
743
+		invert_oe = mode & PINMODE_INVERT_OE;
744
+		mode &= ~PINMODE_INVERT_OE;
842745 
843
-		reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
844
-		value = readl(reg);
746
+		value = chv_readl(pctrl, pin, CHV_PADCTRL0);
845747 		/* Disable GPIO mode */
846748 		value &= ~CHV_PADCTRL0_GPIOEN;
847749 		/* Set to desired mode */
848750 		value &= ~CHV_PADCTRL0_PMODE_MASK;
849
-		value |= altfunc->mode << CHV_PADCTRL0_PMODE_SHIFT;
850
-		chv_writel(value, reg);
751
+		value |= mode << CHV_PADCTRL0_PMODE_SHIFT;
752
+		chv_writel(pctrl, pin, CHV_PADCTRL0, value);
851753 
852754 		/* Update for invert_oe */
853
-		reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
854
-		value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK;
855
-		if (altfunc->invert_oe)
755
+		value = chv_readl(pctrl, pin, CHV_PADCTRL1) & ~CHV_PADCTRL1_INVRXTX_MASK;
756
+		if (invert_oe)
856757 			value |= CHV_PADCTRL1_INVRXTX_TXENABLE;
857
-		chv_writel(value, reg);
758
+		chv_writel(pctrl, pin, CHV_PADCTRL1, value);
858759 
859760 		dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n",
860
-			pin, altfunc->mode, altfunc->invert_oe ? "" : "not ");
761
+			pin, mode, invert_oe ? "" : "not ");
861762 	}
862763 
863764 	raw_spin_unlock_irqrestore(&chv_lock, flags);
....@@ -865,44 +766,61 @@
865766 	return 0;
866767 }
867768 
769
+static void chv_gpio_clear_triggering(struct intel_pinctrl *pctrl,
770
+				      unsigned int offset)
771
+{
772
+	u32 invrxtx_mask = CHV_PADCTRL1_INVRXTX_MASK;
773
+	u32 value;
774
+
775
+	/*
776
+	 * One some devices the GPIO should output the inverted value from what
777
+	 * device-drivers / ACPI code expects (inverted external buffer?). The
778
+	 * BIOS makes this work by setting the CHV_PADCTRL1_INVRXTX_TXDATA flag,
779
+	 * preserve this flag if the pin is already setup as GPIO.
780
+	 */
781
+	value = chv_readl(pctrl, offset, CHV_PADCTRL0);
782
+	if (value & CHV_PADCTRL0_GPIOEN)
783
+		invrxtx_mask &= ~CHV_PADCTRL1_INVRXTX_TXDATA;
784
+
785
+	value = chv_readl(pctrl, offset, CHV_PADCTRL1);
786
+	value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
787
+	value &= ~invrxtx_mask;
788
+	chv_writel(pctrl, offset, CHV_PADCTRL1, value);
789
+}
790
+
868791 static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
869792 				   struct pinctrl_gpio_range *range,
870
-				   unsigned offset)
793
+				   unsigned int offset)
871794 {
872
-	struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
795
+	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
873796 	unsigned long flags;
874
-	void __iomem *reg;
875797 	u32 value;
876798 
877799 	raw_spin_lock_irqsave(&chv_lock, flags);
878800 
879801 	if (chv_pad_locked(pctrl, offset)) {
880
-		value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
802
+		value = chv_readl(pctrl, offset, CHV_PADCTRL0);
881803 		if (!(value & CHV_PADCTRL0_GPIOEN)) {
882804 			/* Locked so cannot enable */
883805 			raw_spin_unlock_irqrestore(&chv_lock, flags);
884806 			return -EBUSY;
885807 		}
886808 	} else {
809
+		struct intel_community_context *cctx = &pctrl->context.communities[0];
887810 		int i;
888811 
889812 		/* Reset the interrupt mapping */
890
-		for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) {
891
-			if (pctrl->intr_lines[i] == offset) {
892
-				pctrl->intr_lines[i] = 0;
813
+		for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++) {
814
+			if (cctx->intr_lines[i] == offset) {
815
+				cctx->intr_lines[i] = 0;
893816 				break;
894817 			}
895818 		}
896819 
897820 		/* Disable interrupt generation */
898
-		reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
899
-		value = readl(reg);
900
-		value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
901
-		value &= ~CHV_PADCTRL1_INVRXTX_MASK;
902
-		chv_writel(value, reg);
821
+		chv_gpio_clear_triggering(pctrl, offset);
903822 
904
-		reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
905
-		value = readl(reg);
823
+		value = chv_readl(pctrl, offset, CHV_PADCTRL0);
906824 
907825 		/*
908826 		 * If the pin is in HiZ mode (both TX and RX buffers are
....@@ -911,13 +829,12 @@
911829 		if ((value & CHV_PADCTRL0_GPIOCFG_MASK) ==
912830 		     (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) {
913831 			value &= ~CHV_PADCTRL0_GPIOCFG_MASK;
914
-			value |= CHV_PADCTRL0_GPIOCFG_GPI <<
915
-				CHV_PADCTRL0_GPIOCFG_SHIFT;
832
+			value |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
916833 		}
917834 
918835 		/* Switch to a GPIO mode */
919836 		value |= CHV_PADCTRL0_GPIOEN;
920
-		chv_writel(value, reg);
837
+		chv_writel(pctrl, offset, CHV_PADCTRL0, value);
921838 	}
922839 
923840 	raw_spin_unlock_irqrestore(&chv_lock, flags);
....@@ -927,39 +844,35 @@
927844 
928845 static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
929846 				  struct pinctrl_gpio_range *range,
930
-				  unsigned offset)
847
+				  unsigned int offset)
931848 {
932
-	struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
849
+	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
933850 	unsigned long flags;
934
-	void __iomem *reg;
935
-	u32 value;
936851 
937852 	raw_spin_lock_irqsave(&chv_lock, flags);
938853 
939
-	reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
940
-	value = readl(reg) & ~CHV_PADCTRL0_GPIOEN;
941
-	chv_writel(value, reg);
854
+	if (!chv_pad_locked(pctrl, offset))
855
+		chv_gpio_clear_triggering(pctrl, offset);
942856 
943857 	raw_spin_unlock_irqrestore(&chv_lock, flags);
944858 }
945859 
946860 static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
947861 				  struct pinctrl_gpio_range *range,
948
-				  unsigned offset, bool input)
862
+				  unsigned int offset, bool input)
949863 {
950
-	struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
951
-	void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
864
+	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
952865 	unsigned long flags;
953866 	u32 ctrl0;
954867 
955868 	raw_spin_lock_irqsave(&chv_lock, flags);
956869 
957
-	ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK;
870
+	ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0) & ~CHV_PADCTRL0_GPIOCFG_MASK;
958871 	if (input)
959872 		ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
960873 	else
961874 		ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
962
-	chv_writel(ctrl0, reg);
875
+	chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0);
963876 
964877 	raw_spin_unlock_irqrestore(&chv_lock, flags);
965878 
....@@ -976,10 +889,10 @@
976889 	.gpio_set_direction = chv_gpio_set_direction,
977890 };
978891 
979
-static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin,
892
+static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
980893 			  unsigned long *config)
981894 {
982
-	struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
895
+	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
983896 	enum pin_config_param param = pinconf_to_config_param(*config);
984897 	unsigned long flags;
985898 	u32 ctrl0, ctrl1;
....@@ -987,8 +900,8 @@
987900 	u32 term;
988901 
989902 	raw_spin_lock_irqsave(&chv_lock, flags);
990
-	ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
991
-	ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
903
+	ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);
904
+	ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);
992905 	raw_spin_unlock_irqrestore(&chv_lock, flags);
993906 
994907 	term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
....@@ -1032,11 +945,6 @@
1032945 
1033946 		break;
1034947 
1035
-	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1036
-		if (!(ctrl1 & CHV_PADCTRL1_ODEN))
1037
-			return -EINVAL;
1038
-		break;
1039
-
1040948 	case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: {
1041949 		u32 cfg;
1042950 
....@@ -1045,6 +953,16 @@
1045953 		if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ)
1046954 			return -EINVAL;
1047955 
956
+		break;
957
+
958
+	case PIN_CONFIG_DRIVE_PUSH_PULL:
959
+		if (ctrl1 & CHV_PADCTRL1_ODEN)
960
+			return -EINVAL;
961
+		break;
962
+
963
+	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
964
+		if (!(ctrl1 & CHV_PADCTRL1_ODEN))
965
+			return -EINVAL;
1048966 		break;
1049967 	}
1050968 
....@@ -1056,15 +974,14 @@
1056974 	return 0;
1057975 }
1058976 
1059
-static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin,
977
+static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
1060978 			       enum pin_config_param param, u32 arg)
1061979 {
1062
-	void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
1063980 	unsigned long flags;
1064981 	u32 ctrl0, pull;
1065982 
1066983 	raw_spin_lock_irqsave(&chv_lock, flags);
1067
-	ctrl0 = readl(reg);
984
+	ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);
1068985 
1069986 	switch (param) {
1070987 	case PIN_CONFIG_BIAS_DISABLE:
....@@ -1116,37 +1033,36 @@
11161033 		return -EINVAL;
11171034 	}
11181035 
1119
-	chv_writel(ctrl0, reg);
1036
+	chv_writel(pctrl, pin, CHV_PADCTRL0, ctrl0);
11201037 	raw_spin_unlock_irqrestore(&chv_lock, flags);
11211038 
11221039 	return 0;
11231040 }
11241041 
1125
-static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin,
1042
+static int chv_config_set_oden(struct intel_pinctrl *pctrl, unsigned int pin,
11261043 			       bool enable)
11271044 {
1128
-	void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
11291045 	unsigned long flags;
11301046 	u32 ctrl1;
11311047 
11321048 	raw_spin_lock_irqsave(&chv_lock, flags);
1133
-	ctrl1 = readl(reg);
1049
+	ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);
11341050 
11351051 	if (enable)
11361052 		ctrl1 |= CHV_PADCTRL1_ODEN;
11371053 	else
11381054 		ctrl1 &= ~CHV_PADCTRL1_ODEN;
11391055 
1140
-	chv_writel(ctrl1, reg);
1056
+	chv_writel(pctrl, pin, CHV_PADCTRL1, ctrl1);
11411057 	raw_spin_unlock_irqrestore(&chv_lock, flags);
11421058 
11431059 	return 0;
11441060 }
11451061 
1146
-static int chv_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1147
-			  unsigned long *configs, unsigned nconfigs)
1062
+static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
1063
+			  unsigned long *configs, unsigned int nconfigs)
11481064 {
1149
-	struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1065
+	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
11501066 	enum pin_config_param param;
11511067 	int i, ret;
11521068 	u32 arg;
....@@ -1245,14 +1161,14 @@
12451161 	.owner = THIS_MODULE,
12461162 };
12471163 
1248
-static int chv_gpio_get(struct gpio_chip *chip, unsigned offset)
1164
+static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset)
12491165 {
1250
-	struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1166
+	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
12511167 	unsigned long flags;
12521168 	u32 ctrl0, cfg;
12531169 
12541170 	raw_spin_lock_irqsave(&chv_lock, flags);
1255
-	ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
1171
+	ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
12561172 	raw_spin_unlock_irqrestore(&chv_lock, flags);
12571173 
12581174 	cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
....@@ -1263,50 +1179,51 @@
12631179 	return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE);
12641180 }
12651181 
1266
-static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1182
+static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
12671183 {
1268
-	struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1184
+	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
12691185 	unsigned long flags;
1270
-	void __iomem *reg;
12711186 	u32 ctrl0;
12721187 
12731188 	raw_spin_lock_irqsave(&chv_lock, flags);
12741189 
1275
-	reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
1276
-	ctrl0 = readl(reg);
1190
+	ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
12771191 
12781192 	if (value)
12791193 		ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE;
12801194 	else
12811195 		ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE;
12821196 
1283
-	chv_writel(ctrl0, reg);
1197
+	chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0);
12841198 
12851199 	raw_spin_unlock_irqrestore(&chv_lock, flags);
12861200 }
12871201 
1288
-static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1202
+static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
12891203 {
1290
-	struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1204
+	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
12911205 	u32 ctrl0, direction;
12921206 	unsigned long flags;
12931207 
12941208 	raw_spin_lock_irqsave(&chv_lock, flags);
1295
-	ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
1209
+	ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
12961210 	raw_spin_unlock_irqrestore(&chv_lock, flags);
12971211 
12981212 	direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
12991213 	direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
13001214 
1301
-	return direction != CHV_PADCTRL0_GPIOCFG_GPO;
1215
+	if (direction == CHV_PADCTRL0_GPIOCFG_GPO)
1216
+		return GPIO_LINE_DIRECTION_OUT;
1217
+
1218
+	return GPIO_LINE_DIRECTION_IN;
13021219 }
13031220 
1304
-static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1221
+static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
13051222 {
13061223 	return pinctrl_gpio_direction_input(chip->base + offset);
13071224 }
13081225 
1309
-static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1226
+static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
13101227 				     int value)
13111228 {
13121229 	chv_gpio_set(chip, offset, value);
....@@ -1327,16 +1244,16 @@
13271244 static void chv_gpio_irq_ack(struct irq_data *d)
13281245 {
13291246 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1330
-	struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1247
+	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
13311248 	int pin = irqd_to_hwirq(d);
13321249 	u32 intr_line;
13331250 
13341251 	raw_spin_lock(&chv_lock);
13351252 
1336
-	intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1253
+	intr_line = chv_readl(pctrl, pin, CHV_PADCTRL0);
13371254 	intr_line &= CHV_PADCTRL0_INTSEL_MASK;
13381255 	intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1339
-	chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT);
1256
+	chv_pctrl_writel(pctrl, CHV_INTSTAT, BIT(intr_line));
13401257 
13411258 	raw_spin_unlock(&chv_lock);
13421259 }
....@@ -1344,23 +1261,23 @@
13441261 static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
13451262 {
13461263 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1347
-	struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1264
+	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
13481265 	int pin = irqd_to_hwirq(d);
13491266 	u32 value, intr_line;
13501267 	unsigned long flags;
13511268 
13521269 	raw_spin_lock_irqsave(&chv_lock, flags);
13531270 
1354
-	intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1271
+	intr_line = chv_readl(pctrl, pin, CHV_PADCTRL0);
13551272 	intr_line &= CHV_PADCTRL0_INTSEL_MASK;
13561273 	intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
13571274 
1358
-	value = readl(pctrl->regs + CHV_INTMASK);
1275
+	value = chv_pctrl_readl(pctrl, CHV_INTMASK);
13591276 	if (mask)
13601277 		value &= ~BIT(intr_line);
13611278 	else
13621279 		value |= BIT(intr_line);
1363
-	chv_writel(value, pctrl->regs + CHV_INTMASK);
1280
+	chv_pctrl_writel(pctrl, CHV_INTMASK, value);
13641281 
13651282 	raw_spin_unlock_irqrestore(&chv_lock, flags);
13661283 }
....@@ -1389,26 +1306,27 @@
13891306 	 */
13901307 	if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
13911308 		struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1392
-		struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1393
-		unsigned pin = irqd_to_hwirq(d);
1309
+		struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1310
+		struct intel_community_context *cctx = &pctrl->context.communities[0];
1311
+		unsigned int pin = irqd_to_hwirq(d);
13941312 		irq_flow_handler_t handler;
13951313 		unsigned long flags;
13961314 		u32 intsel, value;
13971315 
13981316 		raw_spin_lock_irqsave(&chv_lock, flags);
1399
-		intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1317
+		intsel = chv_readl(pctrl, pin, CHV_PADCTRL0);
14001318 		intsel &= CHV_PADCTRL0_INTSEL_MASK;
14011319 		intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
14021320 
1403
-		value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
1321
+		value = chv_readl(pctrl, pin, CHV_PADCTRL1);
14041322 		if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL)
14051323 			handler = handle_level_irq;
14061324 		else
14071325 			handler = handle_edge_irq;
14081326 
1409
-		if (!pctrl->intr_lines[intsel]) {
1327
+		if (!cctx->intr_lines[intsel]) {
14101328 			irq_set_handler_locked(d, handler);
1411
-			pctrl->intr_lines[intsel] = pin;
1329
+			cctx->intr_lines[intsel] = pin;
14121330 		}
14131331 		raw_spin_unlock_irqrestore(&chv_lock, flags);
14141332 	}
....@@ -1417,11 +1335,12 @@
14171335 	return 0;
14181336 }
14191337 
1420
-static int chv_gpio_irq_type(struct irq_data *d, unsigned type)
1338
+static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
14211339 {
14221340 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1423
-	struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1424
-	unsigned pin = irqd_to_hwirq(d);
1341
+	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1342
+	struct intel_community_context *cctx = &pctrl->context.communities[0];
1343
+	unsigned int pin = irqd_to_hwirq(d);
14251344 	unsigned long flags;
14261345 	u32 value;
14271346 
....@@ -1441,9 +1360,7 @@
14411360 	 *	Driver programs the IntWakeCfg bits and save the mapping.
14421361 	 */
14431362 	if (!chv_pad_locked(pctrl, pin)) {
1444
-		void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
1445
-
1446
-		value = readl(reg);
1363
+		value = chv_readl(pctrl, pin, CHV_PADCTRL1);
14471364 		value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
14481365 		value &= ~CHV_PADCTRL1_INVRXTX_MASK;
14491366 
....@@ -1460,14 +1377,14 @@
14601377 				value |= CHV_PADCTRL1_INVRXTX_RXDATA;
14611378 		}
14621379 
1463
-		chv_writel(value, reg);
1380
+		chv_writel(pctrl, pin, CHV_PADCTRL1, value);
14641381 	}
14651382 
1466
-	value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1383
+	value = chv_readl(pctrl, pin, CHV_PADCTRL0);
14671384 	value &= CHV_PADCTRL0_INTSEL_MASK;
14681385 	value >>= CHV_PADCTRL0_INTSEL_SHIFT;
14691386 
1470
-	pctrl->intr_lines[value] = pin;
1387
+	cctx->intr_lines[value] = pin;
14711388 
14721389 	if (type & IRQ_TYPE_EDGE_BOTH)
14731390 		irq_set_handler_locked(d, handle_edge_irq);
....@@ -1482,7 +1399,9 @@
14821399 static void chv_gpio_irq_handler(struct irq_desc *desc)
14831400 {
14841401 	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1485
-	struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1402
+	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1403
+	const struct intel_community *community = &pctrl->communities[0];
1404
+	struct intel_community_context *cctx = &pctrl->context.communities[0];
14861405 	struct irq_chip *chip = irq_desc_get_chip(desc);
14871406 	unsigned long pending;
14881407 	unsigned long flags;
....@@ -1491,13 +1410,13 @@
14911410 	chained_irq_enter(chip, desc);
14921411 
14931412 	raw_spin_lock_irqsave(&chv_lock, flags);
1494
-	pending = readl(pctrl->regs + CHV_INTSTAT);
1413
+	pending = chv_pctrl_readl(pctrl, CHV_INTSTAT);
14951414 	raw_spin_unlock_irqrestore(&chv_lock, flags);
14961415 
1497
-	for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) {
1498
-		unsigned irq, offset;
1416
+	for_each_set_bit(intr_line, &pending, community->nirqs) {
1417
+		unsigned int irq, offset;
14991418 
1500
-		offset = pctrl->intr_lines[intr_line];
1419
+		offset = cctx->intr_lines[intr_line];
15011420 		irq = irq_find_mapping(gc->irq.domain, offset);
15021421 		generic_handle_irq(irq);
15031422 	}
....@@ -1546,53 +1465,34 @@
15461465 	{}
15471466 };
15481467 
1549
-static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
1468
+static void chv_init_irq_valid_mask(struct gpio_chip *chip,
1469
+				    unsigned long *valid_mask,
1470
+				    unsigned int ngpios)
15501471 {
1551
-	const struct chv_gpio_pinrange *range;
1552
-	struct gpio_chip *chip = &pctrl->chip;
1553
-	bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
1554
-	const struct chv_community *community = pctrl->community;
1555
-	int ret, i, irq_base;
1556
-
1557
-	*chip = chv_gpio_chip;
1558
-
1559
-	chip->ngpio = community->pins[community->npins - 1].number + 1;
1560
-	chip->label = dev_name(pctrl->dev);
1561
-	chip->parent = pctrl->dev;
1562
-	chip->base = -1;
1563
-	chip->irq.need_valid_mask = need_valid_mask;
1564
-
1565
-	ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
1566
-	if (ret) {
1567
-		dev_err(pctrl->dev, "Failed to register gpiochip\n");
1568
-		return ret;
1569
-	}
1570
-
1571
-	for (i = 0; i < community->ngpio_ranges; i++) {
1572
-		range = &community->gpio_ranges[i];
1573
-		ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev),
1574
-					     range->base, range->base,
1575
-					     range->npins);
1576
-		if (ret) {
1577
-			dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1578
-			return ret;
1579
-		}
1580
-	}
1472
+	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1473
+	const struct intel_community *community = &pctrl->communities[0];
1474
+	int i;
15811475 
15821476 	/* Do not add GPIOs that can only generate GPEs to the IRQ domain */
1583
-	for (i = 0; i < community->npins; i++) {
1477
+	for (i = 0; i < pctrl->soc->npins; i++) {
15841478 		const struct pinctrl_pin_desc *desc;
15851479 		u32 intsel;
15861480 
1587
-		desc = &community->pins[i];
1481
+		desc = &pctrl->soc->pins[i];
15881482 
1589
-		intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0));
1483
+		intsel = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
15901484 		intsel &= CHV_PADCTRL0_INTSEL_MASK;
15911485 		intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
15921486 
1593
-		if (need_valid_mask && intsel >= community->nirqs)
1594
-			clear_bit(desc->number, chip->irq.valid_mask);
1487
+		if (intsel >= community->nirqs)
1488
+			clear_bit(desc->number, valid_mask);
15951489 	}
1490
+}
1491
+
1492
+static int chv_gpio_irq_init_hw(struct gpio_chip *chip)
1493
+{
1494
+	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1495
+	const struct intel_community *community = &pctrl->communities[0];
15961496 
15971497 	/*
15981498 	 * The same set of machines in chv_no_valid_mask[] have incorrectly
....@@ -1601,27 +1501,58 @@
16011501 	 *
16021502 	 * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953.
16031503 	 */
1604
-	if (!need_valid_mask) {
1504
+	if (!pctrl->chip.irq.init_valid_mask) {
16051505 		/*
16061506 		 * Mask all interrupts the community is able to generate
16071507 		 * but leave the ones that can only generate GPEs unmasked.
16081508 		 */
1609
-		chv_writel(GENMASK(31, pctrl->community->nirqs),
1610
-			   pctrl->regs + CHV_INTMASK);
1509
+		chv_pctrl_writel(pctrl, CHV_INTMASK, GENMASK(31, community->nirqs));
16111510 	}
16121511 
16131512 	/* Clear all interrupts */
1614
-	chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1513
+	chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff);
16151514 
1616
-	if (!need_valid_mask) {
1617
-		irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
1618
-						community->npins, NUMA_NO_NODE);
1619
-		if (irq_base < 0) {
1620
-			dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n");
1621
-			return irq_base;
1515
+	return 0;
1516
+}
1517
+
1518
+static int chv_gpio_add_pin_ranges(struct gpio_chip *chip)
1519
+{
1520
+	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1521
+	const struct intel_community *community = &pctrl->communities[0];
1522
+	const struct intel_padgroup *gpp;
1523
+	int ret, i;
1524
+
1525
+	for (i = 0; i < community->ngpps; i++) {
1526
+		gpp = &community->gpps[i];
1527
+		ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev),
1528
+					     gpp->base, gpp->base,
1529
+					     gpp->size);
1530
+		if (ret) {
1531
+			dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1532
+			return ret;
16221533 		}
16231534 	}
16241535 
1536
+	return 0;
1537
+}
1538
+
1539
+static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1540
+{
1541
+	const struct intel_community *community = &pctrl->communities[0];
1542
+	const struct intel_padgroup *gpp;
1543
+	struct gpio_chip *chip = &pctrl->chip;
1544
+	bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
1545
+	int ret, i, irq_base;
1546
+
1547
+	*chip = chv_gpio_chip;
1548
+
1549
+	chip->ngpio = pctrl->soc->pins[pctrl->soc->npins - 1].number + 1;
1550
+	chip->label = dev_name(pctrl->dev);
1551
+	chip->add_pin_ranges = chv_gpio_add_pin_ranges;
1552
+	chip->parent = pctrl->dev;
1553
+	chip->base = -1;
1554
+
1555
+	pctrl->irq = irq;
16251556 	pctrl->irqchip.name = "chv-gpio";
16261557 	pctrl->irqchip.irq_startup = chv_gpio_irq_startup;
16271558 	pctrl->irqchip.irq_ack = chv_gpio_irq_ack;
....@@ -1630,25 +1561,40 @@
16301561 	pctrl->irqchip.irq_set_type = chv_gpio_irq_type;
16311562 	pctrl->irqchip.flags = IRQCHIP_SKIP_SET_WAKE;
16321563 
1633
-	ret = gpiochip_irqchip_add(chip, &pctrl->irqchip, 0,
1634
-				   handle_bad_irq, IRQ_TYPE_NONE);
1564
+	chip->irq.chip = &pctrl->irqchip;
1565
+	chip->irq.init_hw = chv_gpio_irq_init_hw;
1566
+	chip->irq.parent_handler = chv_gpio_irq_handler;
1567
+	chip->irq.num_parents = 1;
1568
+	chip->irq.parents = &pctrl->irq;
1569
+	chip->irq.default_type = IRQ_TYPE_NONE;
1570
+	chip->irq.handler = handle_bad_irq;
1571
+	if (need_valid_mask) {
1572
+		chip->irq.init_valid_mask = chv_init_irq_valid_mask;
1573
+	} else {
1574
+		irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
1575
+						pctrl->soc->npins, NUMA_NO_NODE);
1576
+		if (irq_base < 0) {
1577
+			dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n");
1578
+			return irq_base;
1579
+		}
1580
+	}
1581
+
1582
+	ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
16351583 	if (ret) {
1636
-		dev_err(pctrl->dev, "failed to add IRQ chip\n");
1584
+		dev_err(pctrl->dev, "Failed to register gpiochip\n");
16371585 		return ret;
16381586 	}
16391587 
16401588 	if (!need_valid_mask) {
1641
-		for (i = 0; i < community->ngpio_ranges; i++) {
1642
-			range = &community->gpio_ranges[i];
1589
+		for (i = 0; i < community->ngpps; i++) {
1590
+			gpp = &community->gpps[i];
16431591 
16441592 			irq_domain_associate_many(chip->irq.domain, irq_base,
1645
-						  range->base, range->npins);
1646
-			irq_base += range->npins;
1593
+						  gpp->base, gpp->size);
1594
+			irq_base += gpp->size;
16471595 		}
16481596 	}
16491597 
1650
-	gpiochip_set_chained_irqchip(chip, &pctrl->irqchip, irq,
1651
-				     chv_gpio_irq_handler);
16521598 	return 0;
16531599 }
16541600 
....@@ -1656,16 +1602,16 @@
16561602 	acpi_physical_address address, u32 bits, u64 *value,
16571603 	void *handler_context, void *region_context)
16581604 {
1659
-	struct chv_pinctrl *pctrl = region_context;
1605
+	struct intel_pinctrl *pctrl = region_context;
16601606 	unsigned long flags;
16611607 	acpi_status ret = AE_OK;
16621608 
16631609 	raw_spin_lock_irqsave(&chv_lock, flags);
16641610 
16651611 	if (function == ACPI_WRITE)
1666
-		chv_writel((u32)(*value), pctrl->regs + (u32)address);
1612
+		chv_pctrl_writel(pctrl, address, *value);
16671613 	else if (function == ACPI_READ)
1668
-		*value = readl(pctrl->regs + (u32)address);
1614
+		*value = chv_pctrl_readl(pctrl, address);
16691615 	else
16701616 		ret = AE_BAD_PARAMETER;
16711617 
....@@ -1676,58 +1622,64 @@
16761622 
16771623 static int chv_pinctrl_probe(struct platform_device *pdev)
16781624 {
1679
-	struct chv_pinctrl *pctrl;
1680
-	struct acpi_device *adev;
1681
-	struct resource *res;
1625
+	const struct intel_pinctrl_soc_data *soc_data;
1626
+	struct intel_community *community;
1627
+	struct device *dev = &pdev->dev;
1628
+	struct intel_pinctrl *pctrl;
16821629 	acpi_status status;
1683
-	int ret, irq, i;
1630
+	int ret, irq;
16841631 
1685
-	adev = ACPI_COMPANION(&pdev->dev);
1686
-	if (!adev)
1687
-		return -ENODEV;
1632
+	soc_data = intel_pinctrl_get_soc_data(pdev);
1633
+	if (IS_ERR(soc_data))
1634
+		return PTR_ERR(soc_data);
16881635 
1689
-	pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1636
+	pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
16901637 	if (!pctrl)
16911638 		return -ENOMEM;
16921639 
1693
-	for (i = 0; i < ARRAY_SIZE(chv_communities); i++)
1694
-		if (!strcmp(adev->pnp.unique_id, chv_communities[i]->uid)) {
1695
-			pctrl->community = chv_communities[i];
1696
-			break;
1697
-		}
1698
-	if (i == ARRAY_SIZE(chv_communities))
1699
-		return -ENODEV;
1640
+	pctrl->dev = dev;
1641
+	pctrl->soc = soc_data;
17001642 
1701
-	pctrl->dev = &pdev->dev;
1643
+	pctrl->ncommunities = pctrl->soc->ncommunities;
1644
+	pctrl->communities = devm_kmemdup(dev, pctrl->soc->communities,
1645
+					  pctrl->ncommunities * sizeof(*pctrl->communities),
1646
+					  GFP_KERNEL);
1647
+	if (!pctrl->communities)
1648
+		return -ENOMEM;
1649
+
1650
+	community = &pctrl->communities[0];
1651
+	community->regs = devm_platform_ioremap_resource(pdev, 0);
1652
+	if (IS_ERR(community->regs))
1653
+		return PTR_ERR(community->regs);
1654
+
1655
+	community->pad_regs = community->regs + FAMILY_PAD_REGS_OFF;
17021656 
17031657 #ifdef CONFIG_PM_SLEEP
1704
-	pctrl->saved_pin_context = devm_kcalloc(pctrl->dev,
1705
-		pctrl->community->npins, sizeof(*pctrl->saved_pin_context),
1706
-		GFP_KERNEL);
1707
-	if (!pctrl->saved_pin_context)
1658
+	pctrl->context.pads = devm_kcalloc(dev, pctrl->soc->npins,
1659
+					   sizeof(*pctrl->context.pads),
1660
+					   GFP_KERNEL);
1661
+	if (!pctrl->context.pads)
17081662 		return -ENOMEM;
17091663 #endif
17101664 
1711
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1712
-	pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
1713
-	if (IS_ERR(pctrl->regs))
1714
-		return PTR_ERR(pctrl->regs);
1665
+	pctrl->context.communities = devm_kcalloc(dev, pctrl->soc->ncommunities,
1666
+						  sizeof(*pctrl->context.communities),
1667
+						  GFP_KERNEL);
1668
+	if (!pctrl->context.communities)
1669
+		return -ENOMEM;
17151670 
17161671 	irq = platform_get_irq(pdev, 0);
1717
-	if (irq < 0) {
1718
-		dev_err(&pdev->dev, "failed to get interrupt number\n");
1672
+	if (irq < 0)
17191673 		return irq;
1720
-	}
17211674 
17221675 	pctrl->pctldesc = chv_pinctrl_desc;
1723
-	pctrl->pctldesc.name = dev_name(&pdev->dev);
1724
-	pctrl->pctldesc.pins = pctrl->community->pins;
1725
-	pctrl->pctldesc.npins = pctrl->community->npins;
1676
+	pctrl->pctldesc.name = dev_name(dev);
1677
+	pctrl->pctldesc.pins = pctrl->soc->pins;
1678
+	pctrl->pctldesc.npins = pctrl->soc->npins;
17261679 
1727
-	pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1728
-					       pctrl);
1680
+	pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl);
17291681 	if (IS_ERR(pctrl->pctldev)) {
1730
-		dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1682
+		dev_err(dev, "failed to register pinctrl driver\n");
17311683 		return PTR_ERR(pctrl->pctldev);
17321684 	}
17331685 
....@@ -1735,12 +1687,12 @@
17351687 	if (ret)
17361688 		return ret;
17371689 
1738
-	status = acpi_install_address_space_handler(adev->handle,
1739
-					pctrl->community->acpi_space_id,
1690
+	status = acpi_install_address_space_handler(ACPI_HANDLE(dev),
1691
+					community->acpi_space_id,
17401692 					chv_pinctrl_mmio_access_handler,
17411693 					NULL, pctrl);
17421694 	if (ACPI_FAILURE(status))
1743
-		dev_err(&pdev->dev, "failed to install ACPI addr space handler\n");
1695
+		dev_err(dev, "failed to install ACPI addr space handler\n");
17441696 
17451697 	platform_set_drvdata(pdev, pctrl);
17461698 
....@@ -1749,10 +1701,11 @@
17491701 
17501702 static int chv_pinctrl_remove(struct platform_device *pdev)
17511703 {
1752
-	struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
1704
+	struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1705
+	const struct intel_community *community = &pctrl->communities[0];
17531706 
1754
-	acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev),
1755
-					  pctrl->community->acpi_space_id,
1707
+	acpi_remove_address_space_handler(ACPI_HANDLE(&pdev->dev),
1708
+					  community->acpi_space_id,
17561709 					  chv_pinctrl_mmio_access_handler);
17571710 
17581711 	return 0;
....@@ -1761,31 +1714,27 @@
17611714 #ifdef CONFIG_PM_SLEEP
17621715 static int chv_pinctrl_suspend_noirq(struct device *dev)
17631716 {
1764
-	struct platform_device *pdev = to_platform_device(dev);
1765
-	struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
1717
+	struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1718
+	struct intel_community_context *cctx = &pctrl->context.communities[0];
17661719 	unsigned long flags;
17671720 	int i;
17681721 
17691722 	raw_spin_lock_irqsave(&chv_lock, flags);
17701723 
1771
-	pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK);
1724
+	cctx->saved_intmask = chv_pctrl_readl(pctrl, CHV_INTMASK);
17721725 
1773
-	for (i = 0; i < pctrl->community->npins; i++) {
1726
+	for (i = 0; i < pctrl->soc->npins; i++) {
17741727 		const struct pinctrl_pin_desc *desc;
1775
-		struct chv_pin_context *ctx;
1776
-		void __iomem *reg;
1728
+		struct intel_pad_context *ctx = &pctrl->context.pads[i];
17771729 
1778
-		desc = &pctrl->community->pins[i];
1730
+		desc = &pctrl->soc->pins[i];
17791731 		if (chv_pad_locked(pctrl, desc->number))
17801732 			continue;
17811733 
1782
-		ctx = &pctrl->saved_pin_context[i];
1734
+		ctx->padctrl0 = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
1735
+		ctx->padctrl0 &= ~CHV_PADCTRL0_GPIORXSTATE;
17831736 
1784
-		reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1785
-		ctx->padctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1786
-
1787
-		reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1788
-		ctx->padctrl1 = readl(reg);
1737
+		ctx->padctrl1 = chv_readl(pctrl, desc->number, CHV_PADCTRL1);
17891738 	}
17901739 
17911740 	raw_spin_unlock_irqrestore(&chv_lock, flags);
....@@ -1795,8 +1744,8 @@
17951744 
17961745 static int chv_pinctrl_resume_noirq(struct device *dev)
17971746 {
1798
-	struct platform_device *pdev = to_platform_device(dev);
1799
-	struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
1747
+	struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1748
+	struct intel_community_context *cctx = &pctrl->context.communities[0];
18001749 	unsigned long flags;
18011750 	int i;
18021751 
....@@ -1807,35 +1756,31 @@
18071756 	 * registers because we don't know in which state BIOS left them
18081757 	 * upon exiting suspend.
18091758 	 */
1810
-	chv_writel(0, pctrl->regs + CHV_INTMASK);
1759
+	chv_pctrl_writel(pctrl, CHV_INTMASK, 0x0000);
18111760 
1812
-	for (i = 0; i < pctrl->community->npins; i++) {
1761
+	for (i = 0; i < pctrl->soc->npins; i++) {
18131762 		const struct pinctrl_pin_desc *desc;
1814
-		const struct chv_pin_context *ctx;
1815
-		void __iomem *reg;
1763
+		struct intel_pad_context *ctx = &pctrl->context.pads[i];
18161764 		u32 val;
18171765 
1818
-		desc = &pctrl->community->pins[i];
1766
+		desc = &pctrl->soc->pins[i];
18191767 		if (chv_pad_locked(pctrl, desc->number))
18201768 			continue;
18211769 
1822
-		ctx = &pctrl->saved_pin_context[i];
1823
-
18241770 		/* Only restore if our saved state differs from the current */
1825
-		reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1826
-		val = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1771
+		val = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
1772
+		val &= ~CHV_PADCTRL0_GPIORXSTATE;
18271773 		if (ctx->padctrl0 != val) {
1828
-			chv_writel(ctx->padctrl0, reg);
1774
+			chv_writel(pctrl, desc->number, CHV_PADCTRL0, ctx->padctrl0);
18291775 			dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n",
1830
-				desc->number, readl(reg));
1776
+				desc->number, chv_readl(pctrl, desc->number, CHV_PADCTRL0));
18311777 		}
18321778 
1833
-		reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1834
-		val = readl(reg);
1779
+		val = chv_readl(pctrl, desc->number, CHV_PADCTRL1);
18351780 		if (ctx->padctrl1 != val) {
1836
-			chv_writel(ctx->padctrl1, reg);
1781
+			chv_writel(pctrl, desc->number, CHV_PADCTRL1, ctx->padctrl1);
18371782 			dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n",
1838
-				desc->number, readl(reg));
1783
+				desc->number, chv_readl(pctrl, desc->number, CHV_PADCTRL1));
18391784 		}
18401785 	}
18411786 
....@@ -1843,8 +1788,8 @@
18431788 	 * Now that all pins are restored to known state, we can restore
18441789 	 * the interrupt mask register as well.
18451790 	 */
1846
-	chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1847
-	chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK);
1791
+	chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff);
1792
+	chv_pctrl_writel(pctrl, CHV_INTMASK, cctx->saved_intmask);
18481793 
18491794 	raw_spin_unlock_irqrestore(&chv_lock, flags);
18501795 
....@@ -1858,7 +1803,7 @@
18581803 };
18591804 
18601805 static const struct acpi_device_id chv_pinctrl_acpi_match[] = {
1861
-	{ "INT33FF" },
1806
+	{ "INT33FF", (kernel_ulong_t)chv_soc_data },
18621807 	{ }
18631808 };
18641809 MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match);