| .. | .. |
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| 17 | 17 | struct platform_device; |
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| 18 | 18 | |
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| 19 | 19 | extern struct pinmux_ops imx_pmx_ops; |
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| 20 | +extern const struct dev_pm_ops imx_pinctrl_pm_ops; |
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| 20 | 21 | |
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| 21 | 22 | /** |
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| 22 | | - * struct imx_pin - describes a single i.MX pin |
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| 23 | | - * @pin: the pin_id of this pin |
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| 23 | + * struct imx_pin_mmio - MMIO pin configurations |
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| 24 | 24 | * @mux_mode: the mux mode for this pin. |
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| 25 | 25 | * @input_reg: the select input register offset for this pin if any |
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| 26 | 26 | * 0 if no select input setting needed. |
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| 27 | 27 | * @input_val: the select input value for this pin. |
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| 28 | 28 | * @configs: the config for this pin. |
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| 29 | 29 | */ |
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| 30 | | -struct imx_pin { |
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| 31 | | - unsigned int pin; |
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| 30 | +struct imx_pin_mmio { |
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| 32 | 31 | unsigned int mux_mode; |
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| 33 | 32 | u16 input_reg; |
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| 34 | 33 | unsigned int input_val; |
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| 35 | 34 | unsigned long config; |
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| 35 | +}; |
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| 36 | + |
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| 37 | +/** |
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| 38 | + * struct imx_pin_scu - SCU pin configurations |
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| 39 | + * @mux: the mux mode for this pin. |
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| 40 | + * @configs: the config for this pin. |
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| 41 | + */ |
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| 42 | +struct imx_pin_scu { |
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| 43 | + unsigned int mux_mode; |
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| 44 | + unsigned long config; |
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| 45 | +}; |
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| 46 | + |
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| 47 | +/** |
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| 48 | + * struct imx_pin - describes a single i.MX pin |
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| 49 | + * @pin: the pin_id of this pin |
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| 50 | + * @conf: config type of this pin, either mmio or scu |
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| 51 | + */ |
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| 52 | +struct imx_pin { |
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| 53 | + unsigned int pin; |
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| 54 | + union { |
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| 55 | + struct imx_pin_mmio mmio; |
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| 56 | + struct imx_pin_scu scu; |
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| 57 | + } conf; |
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| 36 | 58 | }; |
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| 37 | 59 | |
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| 38 | 60 | /** |
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| .. | .. |
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| 51 | 73 | u32 mask; |
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| 52 | 74 | u8 shift; |
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| 53 | 75 | bool invert; |
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| 76 | +}; |
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| 77 | + |
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| 78 | +/** |
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| 79 | + * @dev: a pointer back to containing device |
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| 80 | + * @base: the offset to the controller in virtual memory |
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| 81 | + */ |
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| 82 | +struct imx_pinctrl { |
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| 83 | + struct device *dev; |
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| 84 | + struct pinctrl_dev *pctl; |
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| 85 | + void __iomem *base; |
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| 86 | + void __iomem *input_sel_base; |
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| 87 | + const struct imx_pinctrl_soc_info *info; |
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| 88 | + struct imx_pin_reg *pin_regs; |
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| 89 | + unsigned int group_index; |
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| 90 | + struct mutex mutex; |
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| 54 | 91 | }; |
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| 55 | 92 | |
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| 56 | 93 | struct imx_pinctrl_soc_info { |
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| .. | .. |
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| 76 | 113 | struct pinctrl_gpio_range *range, |
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| 77 | 114 | unsigned offset, |
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| 78 | 115 | bool input); |
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| 79 | | -}; |
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| 80 | | - |
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| 81 | | -/** |
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| 82 | | - * @dev: a pointer back to containing device |
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| 83 | | - * @base: the offset to the controller in virtual memory |
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| 84 | | - */ |
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| 85 | | -struct imx_pinctrl { |
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| 86 | | - struct device *dev; |
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| 87 | | - struct pinctrl_dev *pctl; |
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| 88 | | - void __iomem *base; |
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| 89 | | - void __iomem *input_sel_base; |
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| 90 | | - const struct imx_pinctrl_soc_info *info; |
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| 91 | | - struct imx_pin_reg *pin_regs; |
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| 92 | | - unsigned int group_index; |
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| 93 | | - struct mutex mutex; |
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| 116 | + int (*imx_pinconf_get)(struct pinctrl_dev *pctldev, unsigned int pin_id, |
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| 117 | + unsigned long *config); |
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| 118 | + int (*imx_pinconf_set)(struct pinctrl_dev *pctldev, unsigned int pin_id, |
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| 119 | + unsigned long *configs, unsigned int num_configs); |
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| 120 | + void (*imx_pinctrl_parse_pin)(struct imx_pinctrl *ipctl, |
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| 121 | + unsigned int *pin_id, struct imx_pin *pin, |
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| 122 | + const __be32 **list_p); |
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| 94 | 123 | }; |
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| 95 | 124 | |
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| 96 | 125 | #define IMX_CFG_PARAMS_DECODE(p, m, o) \ |
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| .. | .. |
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| 99 | 128 | #define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \ |
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| 100 | 129 | { .param = p, .mask = m, .shift = o, .invert = true, } |
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| 101 | 130 | |
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| 102 | | -#define SHARE_MUX_CONF_REG 0x1 |
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| 103 | | -#define ZERO_OFFSET_VALID 0x2 |
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| 131 | +#define SHARE_MUX_CONF_REG BIT(0) |
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| 132 | +#define ZERO_OFFSET_VALID BIT(1) |
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| 133 | +#define IMX_USE_SCU BIT(2) |
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| 104 | 134 | |
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| 105 | 135 | #define NO_MUX 0x0 |
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| 106 | 136 | #define NO_PAD 0x0 |
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| .. | .. |
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| 113 | 143 | |
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| 114 | 144 | int imx_pinctrl_probe(struct platform_device *pdev, |
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| 115 | 145 | const struct imx_pinctrl_soc_info *info); |
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| 146 | + |
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| 147 | +#define BM_PAD_CTL_GP_ENABLE BIT(30) |
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| 148 | +#define BM_PAD_CTL_IFMUX_ENABLE BIT(31) |
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| 149 | +#define BP_PAD_CTL_IFMUX 27 |
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| 150 | + |
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| 151 | +int imx_pinctrl_sc_ipc_init(struct platform_device *pdev); |
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| 152 | +int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id, |
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| 153 | + unsigned long *config); |
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| 154 | +int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id, |
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| 155 | + unsigned long *configs, unsigned num_configs); |
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| 156 | +void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl, |
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| 157 | + unsigned int *pin_id, struct imx_pin *pin, |
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| 158 | + const __be32 **list_p); |
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| 116 | 159 | #endif /* __DRIVERS_PINCTRL_IMX_H */ |
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