disable FB

hc

2024-01-04 1543e317f1da31b75942316931e8f491a8920811

 kernel/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
..
..
@@ -64,17 +64,16 @@
64
64
  * @gc: GPIO chip
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65
  * @pctl: pointer to pinctrl_dev
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  * @pctldesc: pinctrl descriptor
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- * @irq_domain: pointer to irq domain
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  * @lock: lock to protect access to I/O registers
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  */
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 struct nsp_gpio {
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 	struct device *dev;
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 	void __iomem *base;
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 	void __iomem *io_ctrl;
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+	struct irq_chip irqchip;
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 	struct gpio_chip gc;
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 	struct pinctrl_dev *pctl;
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 	struct pinctrl_desc pctldesc;
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-	struct irq_domain *irq_domain;
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 	raw_spinlock_t lock;
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 };
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79
 
..
..
@@ -136,8 +135,8 @@
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135
 
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 static irqreturn_t nsp_gpio_irq_handler(int irq, void *data)
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 {
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-	struct nsp_gpio *chip = (struct nsp_gpio *)data;
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-	struct gpio_chip gc = chip->gc;
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+	struct gpio_chip *gc = (struct gpio_chip *)data;
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+	struct nsp_gpio *chip = gpiochip_get_data(gc);
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 	int bit;
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141
 	unsigned long int_bits = 0;
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 	u32 int_status;
..
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@@ -155,15 +154,9 @@
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 		level &= readl(chip->base + NSP_GPIO_INT_MASK);
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 		int_bits = level | event;
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156
 
158
-		for_each_set_bit(bit, &int_bits, gc.ngpio) {
159
-			/*
160
-			 * Clear the interrupt before invoking the
161
-			 * handler, so we do not leave any window
162
-			 */
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-			writel(BIT(bit), chip->base + NSP_GPIO_EVENT);
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+		for_each_set_bit(bit, &int_bits, gc->ngpio)
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158
 			generic_handle_irq(
165
-				irq_linear_revmap(chip->irq_domain, bit));
166
-		}
159
+				irq_linear_revmap(gc->irq.domain, bit));
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160
 	}
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161
 
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 	return  int_bits ? IRQ_HANDLED : IRQ_NONE;
..
..
@@ -171,14 +164,15 @@
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164
 
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 static void nsp_gpio_irq_ack(struct irq_data *d)
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166
 {
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-	struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
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+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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+	struct nsp_gpio *chip = gpiochip_get_data(gc);
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 	unsigned gpio = d->hwirq;
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 	u32 val = BIT(gpio);
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 	u32 trigger_type;
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172
 
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 	trigger_type = irq_get_trigger_type(d->irq);
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 	if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
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-		nsp_set_bit(chip, REG, NSP_GPIO_EVENT, gpio, val);
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+		writel(val, chip->base + NSP_GPIO_EVENT);
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176
 }
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177
 
184
178
 /*
..
..
@@ -189,7 +183,8 @@
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  */
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184
 static void nsp_gpio_irq_set_mask(struct irq_data *d, bool unmask)
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185
 {
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-	struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
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+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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+	struct nsp_gpio *chip = gpiochip_get_data(gc);
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 	unsigned gpio = d->hwirq;
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 	u32 trigger_type;
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190
 
..
..
@@ -202,7 +197,8 @@
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197
 
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 static void nsp_gpio_irq_mask(struct irq_data *d)
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 {
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-	struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
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+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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+	struct nsp_gpio *chip = gpiochip_get_data(gc);
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 	unsigned long flags;
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203
 
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 	raw_spin_lock_irqsave(&chip->lock, flags);
..
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@@ -212,7 +208,8 @@
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208
 
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 static void nsp_gpio_irq_unmask(struct irq_data *d)
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210
 {
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-	struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
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+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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+	struct nsp_gpio *chip = gpiochip_get_data(gc);
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 	unsigned long flags;
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214
 
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 	raw_spin_lock_irqsave(&chip->lock, flags);
..
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@@ -222,7 +219,8 @@
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219
 
223
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 static int nsp_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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221
 {
225
-	struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
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+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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+	struct nsp_gpio *chip = gpiochip_get_data(gc);
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224
 	unsigned gpio = d->hwirq;
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225
 	bool level_low;
228
226
 	bool falling;
..
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@@ -258,22 +256,18 @@
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256
 
259
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 	nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio, falling);
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 	nsp_set_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio, level_low);
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+
260
+	if (type & IRQ_TYPE_EDGE_BOTH)
261
+		irq_set_handler_locked(d, handle_edge_irq);
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+	else
263
+		irq_set_handler_locked(d, handle_level_irq);
264
+
261
265
 	raw_spin_unlock_irqrestore(&chip->lock, flags);
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266
 
263
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 	dev_dbg(chip->dev, "gpio:%u level_low:%s falling:%s\n", gpio,
264
268
 		level_low ? "true" : "false", falling ? "true" : "false");
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269
 	return 0;
266
270
 }
267
-
268
-static struct irq_chip nsp_gpio_irq_chip = {
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-	.name = "gpio-a",
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-	.irq_enable = nsp_gpio_irq_unmask,
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-	.irq_disable = nsp_gpio_irq_mask,
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-	.irq_ack = nsp_gpio_irq_ack,
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-	.irq_mask = nsp_gpio_irq_mask,
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-	.irq_unmask = nsp_gpio_irq_unmask,
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-	.irq_set_type = nsp_gpio_irq_set_type,
276
-};
277
271
 
278
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 static int nsp_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
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273
 {
..
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@@ -303,6 +297,19 @@
303
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 	return 0;
304
298
 }
305
299
 
300
+static int nsp_gpio_get_direction(struct gpio_chip *gc, unsigned gpio)
301
+{
302
+	struct nsp_gpio *chip = gpiochip_get_data(gc);
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+	unsigned long flags;
304
+	int val;
305
+
306
+	raw_spin_lock_irqsave(&chip->lock, flags);
307
+	val = nsp_get_bit(chip, REG, NSP_GPIO_OUT_EN, gpio);
308
+	raw_spin_unlock_irqrestore(&chip->lock, flags);
309
+
310
+	return !val;
311
+}
312
+
306
313
 static void nsp_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
307
314
 {
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315
 	struct nsp_gpio *chip = gpiochip_get_data(gc);
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@@ -320,13 +327,6 @@
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 	struct nsp_gpio *chip = gpiochip_get_data(gc);
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328
 
322
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 	return !!(readl(chip->base + NSP_GPIO_DATA_IN) & BIT(gpio));
323
-}
324
-
325
-static int nsp_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
326
-{
327
-	struct nsp_gpio *chip = gpiochip_get_data(gc);
328
-
329
-	return irq_linear_revmap(chip->irq_domain, offset);
330
330
 }
331
331
 
332
332
 static int nsp_get_groups_count(struct pinctrl_dev *pctldev)
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@@ -613,10 +613,9 @@
613
613
 static int nsp_gpio_probe(struct platform_device *pdev)
614
614
 {
615
615
 	struct device *dev = &pdev->dev;
616
-	struct resource *res;
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616
 	struct nsp_gpio *chip;
618
617
 	struct gpio_chip *gc;
619
-	u32 val, count;
618
+	u32 val;
620
619
 	int irq, ret;
621
620
 
622
621
 	if (of_property_read_u32(pdev->dev.of_node, "ngpios", &val)) {
..
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@@ -631,15 +630,13 @@
631
630
 	chip->dev = dev;
632
631
 	platform_set_drvdata(pdev, chip);
633
632
 
634
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
635
-	chip->base = devm_ioremap_resource(dev, res);
633
+	chip->base = devm_platform_ioremap_resource(pdev, 0);
636
634
 	if (IS_ERR(chip->base)) {
637
635
 		dev_err(dev, "unable to map I/O memory\n");
638
636
 		return PTR_ERR(chip->base);
639
637
 	}
640
638
 
641
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
642
-	chip->io_ctrl = devm_ioremap_resource(dev, res);
639
+	chip->io_ctrl = devm_platform_ioremap_resource(pdev, 1);
643
640
 	if (IS_ERR(chip->io_ctrl)) {
644
641
 		dev_err(dev, "unable to map I/O memory\n");
645
642
 		return PTR_ERR(chip->io_ctrl);
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@@ -657,46 +654,47 @@
657
654
 	gc->free = gpiochip_generic_free;
658
655
 	gc->direction_input = nsp_gpio_direction_input;
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656
 	gc->direction_output = nsp_gpio_direction_output;
657
+	gc->get_direction = nsp_gpio_get_direction;
660
658
 	gc->set = nsp_gpio_set;
661
659
 	gc->get = nsp_gpio_get;
662
-	gc->to_irq = nsp_gpio_to_irq;
663
660
 
664
661
 	/* optional GPIO interrupt support */
665
662
 	irq = platform_get_irq(pdev, 0);
666
663
 	if (irq > 0) {
667
-		/* Create irq domain so that each pin can be assigned an IRQ.*/
668
-		chip->irq_domain = irq_domain_add_linear(gc->of_node, gc->ngpio,
669
-							 &irq_domain_simple_ops,
670
-							 chip);
671
-		if (!chip->irq_domain) {
672
-			dev_err(&pdev->dev, "Couldn't allocate IRQ domain\n");
673
-			return -ENXIO;
674
-		}
664
+		struct gpio_irq_chip *girq;
665
+		struct irq_chip *irqc;
675
666
 
676
-		/* Map each gpio to an IRQ and set the handler for gpiolib. */
677
-		for (count = 0; count < gc->ngpio; count++) {
678
-			int irq = irq_create_mapping(chip->irq_domain, count);
679
-
680
-			irq_set_chip_and_handler(irq, &nsp_gpio_irq_chip,
681
-						 handle_simple_irq);
682
-			irq_set_chip_data(irq, chip);
683
-		}
684
-
685
-		/* Install ISR for this GPIO controller. */
686
-		ret = devm_request_irq(&pdev->dev, irq, nsp_gpio_irq_handler,
687
-				       IRQF_SHARED, "gpio-a", chip);
688
-		if (ret) {
689
-			dev_err(&pdev->dev, "Unable to request IRQ%d: %d\n",
690
-				irq, ret);
691
-			goto err_rm_gpiochip;
692
-		}
667
+		irqc = &chip->irqchip;
668
+		irqc->name = "gpio-a";
669
+		irqc->irq_ack = nsp_gpio_irq_ack;
670
+		irqc->irq_mask = nsp_gpio_irq_mask;
671
+		irqc->irq_unmask = nsp_gpio_irq_unmask;
672
+		irqc->irq_set_type = nsp_gpio_irq_set_type;
693
673
 
694
674
 		val = readl(chip->base + NSP_CHIP_A_INT_MASK);
695
675
 		val = val | NSP_CHIP_A_GPIO_INT_BIT;
696
676
 		writel(val, (chip->base + NSP_CHIP_A_INT_MASK));
677
+
678
+		/* Install ISR for this GPIO controller. */
679
+		ret = devm_request_irq(dev, irq, nsp_gpio_irq_handler,
680
+				       IRQF_SHARED, "gpio-a", &chip->gc);
681
+		if (ret) {
682
+			dev_err(&pdev->dev, "Unable to request IRQ%d: %d\n",
683
+				irq, ret);
684
+			return ret;
685
+		}
686
+
687
+		girq = &chip->gc.irq;
688
+		girq->chip = irqc;
689
+		/* This will let us handle the parent IRQ in the driver */
690
+		girq->parent_handler = NULL;
691
+		girq->num_parents = 0;
692
+		girq->parents = NULL;
693
+		girq->default_type = IRQ_TYPE_NONE;
694
+		girq->handler = handle_bad_irq;
697
695
 	}
698
696
 
699
-	ret = gpiochip_add_data(gc, chip);
697
+	ret = devm_gpiochip_add_data(dev, gc, chip);
700
698
 	if (ret < 0) {
701
699
 		dev_err(dev, "unable to add GPIO chip\n");
702
700
 		return ret;
..
..
@@ -705,15 +703,10 @@
705
703
 	ret = nsp_gpio_register_pinconf(chip);
706
704
 	if (ret) {
707
705
 		dev_err(dev, "unable to register pinconf\n");
708
-		goto err_rm_gpiochip;
706
+		return ret;
709
707
 	}
710
708
 
711
709
 	return 0;
712
-
713
-err_rm_gpiochip:
714
-	gpiochip_remove(gc);
715
-
716
-	return ret;
717
710
 }
718
711
 
719
712
 static struct platform_driver nsp_gpio_driver = {