| .. | .. |
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| 13 | 13 | #include <linux/of.h> |
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| 14 | 14 | #include <linux/platform_device.h> |
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| 15 | 15 | #include <linux/pinctrl/pinctrl.h> |
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| 16 | +#include <linux/pinctrl/pinconf-generic.h> |
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| 16 | 17 | #include "pinctrl-owl.h" |
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| 17 | 18 | |
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| 18 | 19 | /* Pinctrl registers offset */ |
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| .. | .. |
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| 32 | 33 | #define PAD_SR0 (0x0270) |
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| 33 | 34 | #define PAD_SR1 (0x0274) |
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| 34 | 35 | #define PAD_SR2 (0x0278) |
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| 35 | | - |
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| 36 | | -#define OWL_GPIO_PORT_A 0 |
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| 37 | | -#define OWL_GPIO_PORT_B 1 |
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| 38 | | -#define OWL_GPIO_PORT_C 2 |
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| 39 | | -#define OWL_GPIO_PORT_D 3 |
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| 40 | | -#define OWL_GPIO_PORT_E 4 |
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| 41 | | -#define OWL_GPIO_PORT_F 5 |
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| 42 | 36 | |
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| 43 | 37 | #define _GPIOA(offset) (offset) |
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| 44 | 38 | #define _GPIOB(offset) (32 + (offset)) |
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| .. | .. |
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| 892 | 886 | static unsigned int sensor0_sr_pads[] = { SENSOR0_PCLK, |
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| 893 | 887 | SENSOR0_CKOUT }; |
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| 894 | 888 | |
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| 895 | | -#define MUX_PG(group_name, reg, shift, width) \ |
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| 896 | | - { \ |
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| 897 | | - .name = #group_name, \ |
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| 898 | | - .pads = group_name##_pads, \ |
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| 899 | | - .npads = ARRAY_SIZE(group_name##_pads), \ |
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| 900 | | - .funcs = group_name##_funcs, \ |
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| 901 | | - .nfuncs = ARRAY_SIZE(group_name##_funcs), \ |
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| 902 | | - .mfpctl_reg = MFCTL##reg, \ |
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| 903 | | - .mfpctl_shift = shift, \ |
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| 904 | | - .mfpctl_width = width, \ |
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| 905 | | - .drv_reg = -1, \ |
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| 906 | | - .drv_shift = -1, \ |
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| 907 | | - .drv_width = -1, \ |
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| 908 | | - .sr_reg = -1, \ |
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| 909 | | - .sr_shift = -1, \ |
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| 910 | | - .sr_width = -1, \ |
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| 911 | | - } |
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| 912 | | - |
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| 913 | | -#define DRV_PG(group_name, reg, shift, width) \ |
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| 914 | | - { \ |
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| 915 | | - .name = #group_name, \ |
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| 916 | | - .pads = group_name##_pads, \ |
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| 917 | | - .npads = ARRAY_SIZE(group_name##_pads), \ |
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| 918 | | - .mfpctl_reg = -1, \ |
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| 919 | | - .mfpctl_shift = -1, \ |
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| 920 | | - .mfpctl_width = -1, \ |
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| 921 | | - .drv_reg = PAD_DRV##reg, \ |
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| 922 | | - .drv_shift = shift, \ |
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| 923 | | - .drv_width = width, \ |
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| 924 | | - .sr_reg = -1, \ |
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| 925 | | - .sr_shift = -1, \ |
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| 926 | | - .sr_width = -1, \ |
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| 927 | | - } |
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| 928 | | - |
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| 929 | | -#define SR_PG(group_name, reg, shift, width) \ |
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| 930 | | - { \ |
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| 931 | | - .name = #group_name, \ |
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| 932 | | - .pads = group_name##_pads, \ |
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| 933 | | - .npads = ARRAY_SIZE(group_name##_pads), \ |
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| 934 | | - .mfpctl_reg = -1, \ |
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| 935 | | - .mfpctl_shift = -1, \ |
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| 936 | | - .mfpctl_width = -1, \ |
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| 937 | | - .drv_reg = -1, \ |
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| 938 | | - .drv_shift = -1, \ |
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| 939 | | - .drv_width = -1, \ |
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| 940 | | - .sr_reg = PAD_SR##reg, \ |
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| 941 | | - .sr_shift = shift, \ |
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| 942 | | - .sr_width = width, \ |
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| 943 | | - } |
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| 944 | 889 | |
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| 945 | 890 | /* Pinctrl groups */ |
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| 946 | 891 | static const struct owl_pingroup s900_groups[] = { |
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| .. | .. |
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| 1442 | 1387 | "sirq2_dummy", |
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| 1443 | 1388 | }; |
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| 1444 | 1389 | |
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| 1445 | | -#define FUNCTION(fname) \ |
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| 1446 | | - { \ |
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| 1447 | | - .name = #fname, \ |
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| 1448 | | - .groups = fname##_groups, \ |
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| 1449 | | - .ngroups = ARRAY_SIZE(fname##_groups), \ |
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| 1450 | | - } |
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| 1451 | | - |
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| 1452 | 1390 | static const struct owl_pinmux_func s900_functions[] = { |
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| 1453 | 1391 | [S900_MUX_ERAM] = FUNCTION(eram), |
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| 1454 | 1392 | [S900_MUX_ETH_RMII] = FUNCTION(eth_rmii), |
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| .. | .. |
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| 1500 | 1438 | [S900_MUX_SIRQ1] = FUNCTION(sirq1), |
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| 1501 | 1439 | [S900_MUX_SIRQ2] = FUNCTION(sirq2) |
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| 1502 | 1440 | }; |
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| 1503 | | -/* PAD PULL UP/DOWN CONFIGURES */ |
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| 1504 | | -#define PULLCTL_CONF(pull_reg, pull_sft, pull_wdt) \ |
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| 1505 | | - { \ |
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| 1506 | | - .reg = PAD_PULLCTL##pull_reg, \ |
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| 1507 | | - .shift = pull_sft, \ |
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| 1508 | | - .width = pull_wdt, \ |
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| 1509 | | - } |
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| 1510 | | - |
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| 1511 | | -#define PAD_PULLCTL_CONF(pad_name, pull_reg, pull_sft, pull_wdt) \ |
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| 1512 | | - struct owl_pullctl pad_name##_pullctl_conf \ |
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| 1513 | | - = PULLCTL_CONF(pull_reg, pull_sft, pull_wdt) |
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| 1514 | | - |
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| 1515 | | -#define ST_CONF(st_reg, st_sft, st_wdt) \ |
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| 1516 | | - { \ |
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| 1517 | | - .reg = PAD_ST##st_reg, \ |
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| 1518 | | - .shift = st_sft, \ |
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| 1519 | | - .width = st_wdt, \ |
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| 1520 | | - } |
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| 1521 | | - |
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| 1522 | | -#define PAD_ST_CONF(pad_name, st_reg, st_sft, st_wdt) \ |
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| 1523 | | - struct owl_st pad_name##_st_conf \ |
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| 1524 | | - = ST_CONF(st_reg, st_sft, st_wdt) |
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| 1525 | 1441 | |
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| 1526 | 1442 | /* PAD_PULLCTL0 */ |
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| 1527 | 1443 | static PAD_PULLCTL_CONF(ETH_RXER, 0, 18, 2); |
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| .. | .. |
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| 1639 | 1555 | static PAD_ST_CONF(I2S_BCLK0, 1, 1, 1); |
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| 1640 | 1556 | static PAD_ST_CONF(I2S_MCLK0, 1, 0, 1); |
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| 1641 | 1557 | |
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| 1642 | | -#define PAD_INFO(name) \ |
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| 1643 | | - { \ |
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| 1644 | | - .pad = name, \ |
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| 1645 | | - .pullctl = NULL, \ |
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| 1646 | | - .st = NULL, \ |
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| 1647 | | - } |
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| 1648 | | - |
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| 1649 | | -#define PAD_INFO_ST(name) \ |
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| 1650 | | - { \ |
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| 1651 | | - .pad = name, \ |
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| 1652 | | - .pullctl = NULL, \ |
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| 1653 | | - .st = &name##_st_conf, \ |
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| 1654 | | - } |
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| 1655 | | - |
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| 1656 | | -#define PAD_INFO_PULLCTL(name) \ |
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| 1657 | | - { \ |
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| 1658 | | - .pad = name, \ |
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| 1659 | | - .pullctl = &name##_pullctl_conf, \ |
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| 1660 | | - .st = NULL, \ |
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| 1661 | | - } |
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| 1662 | | - |
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| 1663 | | -#define PAD_INFO_PULLCTL_ST(name) \ |
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| 1664 | | - { \ |
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| 1665 | | - .pad = name, \ |
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| 1666 | | - .pullctl = &name##_pullctl_conf, \ |
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| 1667 | | - .st = &name##_st_conf, \ |
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| 1668 | | - } |
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| 1669 | | - |
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| 1670 | 1558 | /* Pad info table */ |
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| 1671 | | -static struct owl_padinfo s900_padinfo[NUM_PADS] = { |
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| 1559 | +static const struct owl_padinfo s900_padinfo[NUM_PADS] = { |
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| 1672 | 1560 | [ETH_TXD0] = PAD_INFO_ST(ETH_TXD0), |
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| 1673 | 1561 | [ETH_TXD1] = PAD_INFO_ST(ETH_TXD1), |
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| 1674 | 1562 | [ETH_TXEN] = PAD_INFO_ST(ETH_TXEN), |
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| .. | .. |
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| 1821 | 1709 | [SGPIO3] = PAD_INFO_PULLCTL_ST(SGPIO3) |
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| 1822 | 1710 | }; |
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| 1823 | 1711 | |
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| 1824 | | -#define OWL_GPIO_PORT(port, base, count, _outen, _inen, _dat, \ |
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| 1825 | | - _intc_ctl, _intc_pd, _intc_msk, _intc_type) \ |
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| 1826 | | - [OWL_GPIO_PORT_##port] = { \ |
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| 1827 | | - .offset = base, \ |
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| 1828 | | - .pins = count, \ |
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| 1829 | | - .outen = _outen, \ |
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| 1830 | | - .inen = _inen, \ |
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| 1831 | | - .dat = _dat, \ |
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| 1832 | | - .intc_ctl = _intc_ctl, \ |
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| 1833 | | - .intc_pd = _intc_pd, \ |
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| 1834 | | - .intc_msk = _intc_msk, \ |
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| 1835 | | - .intc_type = _intc_type, \ |
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| 1712 | +static const struct owl_gpio_port s900_gpio_ports[] = { |
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| 1713 | + OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x240, 0), |
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| 1714 | + OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x534, 0x204, 0x208, 0x23C, 0), |
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| 1715 | + OWL_GPIO_PORT(C, 0x0018, 12, 0x0, 0x4, 0x8, 0x52C, 0x200, 0x204, 0x238, 0), |
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| 1716 | + OWL_GPIO_PORT(D, 0x0024, 30, 0x0, 0x4, 0x8, 0x524, 0x1FC, 0x200, 0x234, 0), |
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| 1717 | + OWL_GPIO_PORT(E, 0x0030, 32, 0x0, 0x4, 0x8, 0x51C, 0x1F8, 0x1FC, 0x230, 0), |
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| 1718 | + OWL_GPIO_PORT(F, 0x00F0, 8, 0x0, 0x4, 0x8, 0x460, 0x140, 0x144, 0x178, 0) |
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| 1719 | +}; |
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| 1720 | + |
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| 1721 | +enum s900_pinconf_pull { |
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| 1722 | + OWL_PINCONF_PULL_HIZ, |
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| 1723 | + OWL_PINCONF_PULL_DOWN, |
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| 1724 | + OWL_PINCONF_PULL_UP, |
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| 1725 | + OWL_PINCONF_PULL_HOLD, |
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| 1726 | +}; |
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| 1727 | + |
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| 1728 | +static int s900_pad_pinconf_arg2val(const struct owl_padinfo *info, |
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| 1729 | + unsigned int param, |
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| 1730 | + u32 *arg) |
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| 1731 | +{ |
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| 1732 | + switch (param) { |
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| 1733 | + case PIN_CONFIG_BIAS_BUS_HOLD: |
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| 1734 | + *arg = OWL_PINCONF_PULL_HOLD; |
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| 1735 | + break; |
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| 1736 | + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: |
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| 1737 | + *arg = OWL_PINCONF_PULL_HIZ; |
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| 1738 | + break; |
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| 1739 | + case PIN_CONFIG_BIAS_PULL_DOWN: |
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| 1740 | + *arg = OWL_PINCONF_PULL_DOWN; |
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| 1741 | + break; |
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| 1742 | + case PIN_CONFIG_BIAS_PULL_UP: |
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| 1743 | + *arg = OWL_PINCONF_PULL_UP; |
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| 1744 | + break; |
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| 1745 | + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: |
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| 1746 | + *arg = (*arg >= 1 ? 1 : 0); |
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| 1747 | + break; |
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| 1748 | + default: |
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| 1749 | + return -ENOTSUPP; |
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| 1836 | 1750 | } |
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| 1837 | 1751 | |
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| 1838 | | -static const struct owl_gpio_port s900_gpio_ports[] = { |
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| 1839 | | - OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x240), |
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| 1840 | | - OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x534, 0x204, 0x208, 0x23C), |
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| 1841 | | - OWL_GPIO_PORT(C, 0x0018, 12, 0x0, 0x4, 0x8, 0x52C, 0x200, 0x204, 0x238), |
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| 1842 | | - OWL_GPIO_PORT(D, 0x0024, 30, 0x0, 0x4, 0x8, 0x524, 0x1FC, 0x200, 0x234), |
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| 1843 | | - OWL_GPIO_PORT(E, 0x0030, 32, 0x0, 0x4, 0x8, 0x51C, 0x1F8, 0x1FC, 0x230), |
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| 1844 | | - OWL_GPIO_PORT(F, 0x00F0, 8, 0x0, 0x4, 0x8, 0x460, 0x140, 0x144, 0x178) |
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| 1845 | | -}; |
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| 1752 | + return 0; |
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| 1753 | +} |
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| 1754 | + |
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| 1755 | +static int s900_pad_pinconf_val2arg(const struct owl_padinfo *padinfo, |
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| 1756 | + unsigned int param, |
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| 1757 | + u32 *arg) |
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| 1758 | +{ |
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| 1759 | + switch (param) { |
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| 1760 | + case PIN_CONFIG_BIAS_BUS_HOLD: |
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| 1761 | + *arg = *arg == OWL_PINCONF_PULL_HOLD; |
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| 1762 | + break; |
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| 1763 | + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: |
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| 1764 | + *arg = *arg == OWL_PINCONF_PULL_HIZ; |
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| 1765 | + break; |
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| 1766 | + case PIN_CONFIG_BIAS_PULL_DOWN: |
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| 1767 | + *arg = *arg == OWL_PINCONF_PULL_DOWN; |
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| 1768 | + break; |
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| 1769 | + case PIN_CONFIG_BIAS_PULL_UP: |
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| 1770 | + *arg = *arg == OWL_PINCONF_PULL_UP; |
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| 1771 | + break; |
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| 1772 | + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: |
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| 1773 | + *arg = *arg == 1; |
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| 1774 | + break; |
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| 1775 | + default: |
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| 1776 | + return -ENOTSUPP; |
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| 1777 | + } |
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| 1778 | + |
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| 1779 | + return 0; |
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| 1780 | +} |
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| 1846 | 1781 | |
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| 1847 | 1782 | static struct owl_pinctrl_soc_data s900_pinctrl_data = { |
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| 1848 | 1783 | .padinfo = s900_padinfo, |
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| .. | .. |
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| 1854 | 1789 | .ngroups = ARRAY_SIZE(s900_groups), |
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| 1855 | 1790 | .ngpios = NUM_GPIOS, |
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| 1856 | 1791 | .ports = s900_gpio_ports, |
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| 1857 | | - .nports = ARRAY_SIZE(s900_gpio_ports) |
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| 1792 | + .nports = ARRAY_SIZE(s900_gpio_ports), |
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| 1793 | + .padctl_arg2val = s900_pad_pinconf_arg2val, |
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| 1794 | + .padctl_val2arg = s900_pad_pinconf_val2arg, |
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| 1858 | 1795 | }; |
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| 1859 | 1796 | |
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| 1860 | 1797 | static int s900_pinctrl_probe(struct platform_device *pdev) |
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